CN1901228A - Semiconductor device and semiconductor device manufacturing method - Google Patents
Semiconductor device and semiconductor device manufacturing method Download PDFInfo
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- CN1901228A CN1901228A CN 200610091231 CN200610091231A CN1901228A CN 1901228 A CN1901228 A CN 1901228A CN 200610091231 CN200610091231 CN 200610091231 CN 200610091231 A CN200610091231 A CN 200610091231A CN 1901228 A CN1901228 A CN 1901228A
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Abstract
To dispose a back gate electrode forced to have a low resistance under a semiconductor layer to form thereon field effect transistors, while preventing the degradation of the crystal quality of the semiconductor layer to form thereon the field effect transistors. With respect to a semiconductor device, a buried oxide film 12 is formed on a single-crystal semiconductor substrate 11, and a first single-crystal semiconductor layer 13 constituting a back gate electrode is formed on the buried oxide film 12. Further, a buried oxide film 14 is formed on the first semiconductor layer 13, and second single-crystal semiconductor layers 15a, 15b subjected to a mesa-isolation are laminated on the buried oxide film 14. The film thicknesses of the second semiconductor layers 15a, 15b are made larger than that of the first semiconductor layer 13, and SOI transistors are formed respectively on the second semiconductor layers 15a, 15b.
Description
Technical field
The present invention relates to the manufacture method of a kind of semiconductor device and semiconductor device, it is particularly suitable for being applied in the formation method of SOI (Silicon On Insulator) transistorized back of the body grid (back gate) electrode.
Background technology
Be formed on the field-effect transistor on SOI (the Silicon On Insulator) substrate, the easiness, the nothing sealing that separate based on its element lock (latch up free), source/drain in conjunction with characteristics such as electric capacity are little, and its serviceability receives much concern.
In addition, for example in patent documentation 1, following a kind of method has been proposed, that is: in order on large-area dielectric film, to form crystallinity and the silicon thin film that has good uniformity, by noncrystalline or polysilicon layer to film forming on dielectric film, irradiation with ultraviolet rays Shu Jinhang pulse shape, thereby on dielectric film, form approximate foursquare unijunction crystal grain is configured to enclose the polysilicon film of gridiron pattern shape, then, by CMP (cmp), planarization is carried out on the surface of this polysilicon film.
[patent documentation 1]: the spy opens flat 10-261799 communique
Yet, have crystal boundary (grain boundaries), miniature twin crystal (microtwins), other various tiny flaws in the silicon thin film that on dielectric film, forms.Therefore, the field-effect transistor that forms on such silicon thin film is compared with the field-effect transistor that forms on complete monocrystalline silicon thin film, exists the problem of transistor characteristic deterioration.
In addition, will be formed under the stacked situation of field-effect transistor on the silicon thin film, field-effect transistor is positioned at lower floor.Therefore exist the flatness deterioration of the underlying insulation film that forms the upper strata silicon thin film, and the heat-treat condition during to formation upper strata silicon thin film etc. has produced restriction, the crystallinity of upper strata silicon thin film is than the problem of the crystallinity difference of lower floor silicon thin film.
And, in semiconductor integrated circuit in the past, when channel length is shortened, will make the rising characteristic deterioration of the drain current in subthreshold value zone.Therefore, exist following problems, that is: when influencing transistorized low voltage operating performance, increased by the time leakage current, thereby the increase of power consumption when not only causing work and standby and becomes the main cause of transistor damage.
Summary of the invention
Therefore, the objective of the invention is, the manufacture method of a kind of semiconductor device and semiconductor device is provided, it is in the crystalline deterioration of the semiconductor layer that suppresses the formation field-effect transistor, can be under the semiconductor layer that forms field-effect transistor, the back-gate electrode of configuration low resistanceization.
For addressing the above problem, semiconductor device according to an embodiment of the present invention has: the back-gate electrode that is made of the 1st single-crystal semiconductor layer that is formed on the 1st insulating barrier; Be formed on the 2nd insulating barrier on described the 1st single-crystal semiconductor layer; Be formed on described the 2nd insulating barrier, and the 2nd thin single-crystal semiconductor layer of described the 1st single-crystal semiconductor layer of Film Thickness Ratio; Be formed on the gate electrode on described the 2nd single-crystal semiconductor layer; Be formed on described the 2nd single-crystal semiconductor layer, and be configured in the source of described gate electrode side respectively.
Therefore, can improve the degree of freedom of configuration back-gate electrode, and can not be subjected to the restriction of the configuration of gate electrode, source/drain contact electrode etc., dispose back-gate electrode.Thereby, can improve the design freedom of field-effect transistor, and can utilize the back-gate electrode bias voltage to come the threshold voltage of controlling filed effect transistor, or utilize double-grid structure to improve the subthreshold value characteristic.
In addition, back-gate electrode is set, can utilizes back-gate electrode shielding drain potential by rear side at single-crystal semiconductor layer.Therefore, even applied at silicon film surface under the situation of drain potential, also can prevent at the biasing layer or the high concentration impurity diffusion layer of drain electrode and imbed the high voltage of generation at the interface of oxide-film from SOI.Its result can prevent biasing layer or high concentration impurity diffusion layer and the generation at the interface part highfield of imbedding oxide-film in drain electrode, thereby can realize withstand voltageization of the transistorized height of SOI.
In addition, can control the current potential of the transistorized zone of action of SOI, can carry out the transistorized threshold value control of SOI, and can improve the rising characteristic of the drain current in subthreshold value zone, simultaneously, can relax the electric field of drain electrode one lateral sulcus road end by back-gate electrode.Therefore, transistor can be worked under low-voltage state, can reduce by the time leakage current, in the time of power consumption in the time of can reducing work or standby, improve the voltage endurance of SOI field-effect transistor.
In addition, the thickness of the 1st single-crystal semiconductor layer by will forming back-gate electrode is done thicklyer than the thickness that forms transistorized the 2nd single-crystal semiconductor layer of SOI, can realize the low resistanceization of back-gate electrode.Therefore, can control the transistorized threshold position of SOI, and the area of back-gate electrode is increased, thereby can reduce the contact number that is connected with back-gate electrode, suppress the increase of chip size with low-voltage.
In addition, the semiconductor device according to one embodiment of the present invention is characterized in that, also has the wiring layer that described back-gate electrode is electrically connected with described gate electrode.
Therefore, back-gate electrode can be regulated and control become to have identical current potential with gate electrode, improve the control of channel region current potential.For this reason, the increase of chip size can be suppressed, the leakage current when ending can be reduced.Thereby the power consumption in the time of can reducing work or standby, high withstand voltageization of realization field-effect transistor.
In addition, the manufacture method according to the semiconductor device of one embodiment of the present invention comprises: the operation of film forming the 1st single-crystal semiconductor layer on single crystalline semiconductor substrate; On described the 1st single-crystal semiconductor layer, the operation of the 2nd single-crystal semiconductor layer that the film forming etch-rate is littler than described the 1st single-crystal semiconductor layer; On described the 2nd single-crystal semiconductor layer, film forming has the operation with the 3rd single-crystal semiconductor layer of the same composition of described the 1st single-crystal semiconductor layer; On described the 3rd single-crystal semiconductor layer, film forming has and the same composition of described the 2nd single-crystal semiconductor layer, and the operation of thin the 4th single-crystal semiconductor layer of described the 2nd single-crystal semiconductor layer of Film Thickness Ratio; Form to connect described the 1st to the 4th single-crystal semiconductor layer, and make the operation of the 1st groove that described single crystalline semiconductor substrate exposes; In described the 1st groove, form the operation that the described the 2nd and the 4th single-crystal semiconductor layer is supported on the supporter on the described single crystalline semiconductor substrate; Form the operation of the 2nd groove, the 2nd groove makes at least a portion of the described the 1st and the 3rd single-crystal semiconductor layer that have formed described supporter, exposes from the described the 2nd and the 4th single-crystal semiconductor layer; By the 1st and the 3rd single-crystal semiconductor layer being carried out selective etch, thereby respectively the described the 1st and the 3rd single-crystal semiconductor layer is removed, formed the operation of the 1st and the 2nd blank part via described the 2nd groove; By the thermal oxidation that described single crystalline semiconductor substrate, the described the 2nd and the 4th single-crystal semiconductor layer are carried out, thereby form the operation of imbedding oxide-film that is embedded in the described the 1st and the 2nd blank part respectively; By described the 4th single-crystal semiconductor layer is carried out thermal oxidation, thereby on described the 4th single-crystal semiconductor layer, form the operation of gate insulating film; Across described gate insulating film, on described the 4th single-crystal semiconductor layer, form the operation of gate electrode; With inject by described gate electrode is carried out ion as mask, thereby on described the 4th single-crystal semiconductor layer, form the operation of the source that is configured in described gate electrode side respectively.
Therefore, even on the 1st and the 3rd single-crystal semiconductor layer, difference is stacked under the situation of the 2nd and the 4th single-crystal semiconductor layer, also can pass through the 2nd groove, make etching solution touch the 1st and the 3rd single-crystal semiconductor layer, remove the 1st and the 3rd single-crystal semiconductor layer, keep the 2nd and the 4th single-crystal semiconductor layer, simultaneously, can form the oxide-film of imbedding in the 1st and the 2nd blank part that is embedded in respectively below the 2nd and the 4th single-crystal semiconductor layer.In addition, owing to formed the supporter that is embedded at the 1st groove, even thereby below the 2nd and the 4th single-crystal semiconductor layer, formed respectively under the situation of the 1st and the 2nd blank part, also can be at single crystalline semiconductor substrate upper support the 2nd and the 4th single-crystal semiconductor layer, and thicker by Film Thickness Ratio the 2nd single-crystal semiconductor layer that makes the 4th single-crystal semiconductor layer, can stably support the 4th single-crystal semiconductor layer.
Therefore, can be when reducing by the 2nd and the 4th single-crystal semiconductor layer generation defective, imbedding configuration the 2nd and the 4th single-crystal semiconductor layer on the oxide-film, and need not use the SOI substrate, just the back-gate electrode of low resistanceization can be disposed in the rear side of the 2nd single-crystal semiconductor layer, and the SOI transistor can be on the 2nd single-crystal semiconductor layer, formed.Its result can reduce cost, reduce the leakage current of SOI transistor when ending, and can realize withstand voltageization of the transistorized height of SOI.
In addition, the manufacture method according to the semiconductor device of one embodiment of the present invention is characterized in that described single crystalline semiconductor substrate and described the 2nd, the 4th single-crystal semiconductor layer are Si, and the described the 1st and the 3rd single-crystal semiconductor layer is SiGe.
Therefore, can between single crystalline semiconductor substrate, the 1st to the 4th single-crystal semiconductor layer, realize lattice match, and the etch-rate that can make the 1st and the 3rd single-crystal semiconductor layer big than single crystalline semiconductor substrate, the 2nd and the 4th single-crystal semiconductor layer.Therefore, can on the 1st and the 3rd single-crystal semiconductor layer, form the 2nd and the 4th good single-crystal semiconductor layer of crystalline quality respectively, thereby can under the situation of the quality that does not influence the 2nd and the 4th single-crystal semiconductor layer, realize the insulation between the 2nd and the 4th single-crystal semiconductor layer and the single crystalline semiconductor substrate.
In addition, manufacture method according to the semiconductor device of one embodiment of the present invention, it is characterized in that, have the operation that foreign ion is injected into described the 2nd single-crystal semiconductor layer, the stroke distances of this impurity is set at the position darker than the central authorities of the film thickness direction of described the 2nd single-crystal semiconductor layer.
Therefore, can suppress forming the damage that transistorized the 4th single-crystal semiconductor layer of SOI is produced, realize the low resistanceization of back-gate electrode, and can under the situation that does not make SOI characteristics of transistor deterioration, carry out far distance controlled to the transistorized threshold position of SOI with low-voltage.
Description of drawings
Fig. 1 is the profile of schematic configuration of the semiconductor device of expression the 1st execution mode of the present invention.
Fig. 2 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 3 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 4 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 5 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 6 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 7 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 8 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 9 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Figure 10 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Figure 11 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Figure 12 is the figure of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.
Among the figure: 11,31-single crystalline semiconductor substrate; 12,14,32,34-imbeds oxide-film; 13-the 1st single-crystal semiconductor layer; 15a, 15b-the 2nd single-crystal semiconductor layer; 33,35,51,52-single-crystal semiconductor layer; 16a, 16b, 41-gate insulating film; 17a, 17b, 42-gate electrode; 18a, 18b-sidewall; 19a, 19b, 43a-source layer; 20a, 20b, 43b-drain electrode layer; 36,37,38-groove; The 39-oxide-film; The 44-interlayer insulating film; 45-imbeds insulator; 45a, 45b-back of the body grid contact electrode; 46a-source electrode contact electrode; The 46b-contact electrode that drains; 53-sacrificial oxidation film (sacrificial oxide film); The 54-oxygen-proof film; The 56-supporter; 57a, 57b-blank part.
Embodiment
Below, with reference to accompanying drawing, the semiconductor device and the manufacture method thereof of embodiments of the present invention described.
Fig. 1 is the profile of general configuration of the semiconductor device of expression the 1st execution mode of the present invention.
In Fig. 1, on single crystalline semiconductor substrate 11, form and imbed oxide-film 12, imbedding the 1st single-crystal semiconductor layer 13 that forms the formation back-gate electrode on the oxide-film 12.And, on the 1st single-crystal semiconductor layer 13, form and imbed oxide-film 14.Imbed on the oxide-film 14 stacked by the 2nd single-crystal semiconductor layer 15a, the 15b of mesa-isolated.In addition, can use the material of Si as single crystalline semiconductor substrate the 11, the 1st single-crystal semiconductor layer 13 and the 2nd single-crystal semiconductor layer 15a, 15b.In addition, it is thicker to it is desirable to the thickness of Film Thickness Ratio the 1st single-crystal semiconductor layer 13 of the 2nd single-crystal semiconductor layer 15a, 15b.
Then, on the 2nd single-crystal semiconductor layer 15a, form gate electrode 17a, form sidewall 18a in the side of gate electrode 17a across gate insulating film 16a.Simultaneously, on the 2nd single-crystal semiconductor layer 15a, be formed with and be configured to source layer 19a and drain electrode layer 20a that gate electrode 17a is clipped in the middle.And, on the 2nd single-crystal semiconductor layer 15b, be formed with gate electrode 17b across gate insulating film 16b, form sidewall 18b in the side of gate electrode 17b.In addition, on the 2nd single-crystal semiconductor layer 15b, be formed with and be configured to source layer 19b and drain electrode layer 20b that gate electrode 17b is clipped in the middle.
Thus, on the 2nd single-crystal semiconductor layer 15a, 15b, can form the SOI transistor respectively, and, back-gate electrode can be disposed in the transistorized rear side of SOI.Therefore, can improve the degree of freedom of configuration back-gate electrode, thereby can make the configuration of back-gate electrode not be subjected to the restriction of the configuration of gate electrode 17a, 17b and source/drain polar contact etc.
Therefore, can improve the transistorized design freedom of SOI, and can utilize the back-gate electrode bias voltage to control the transistorized threshold voltage of SOI, perhaps utilize double-grid structure, improve its subthreshold value characteristic.
In addition, the rear side configuration back-gate electrode by at the 1st single-crystal semiconductor layer 15a, 15b can shield drain potential with back-gate electrode.Therefore, even applied under the situation of drain potential, also can prevent at drain electrode layer 20a, 20b and imbed the high voltage of generation at the interface of oxide-film 14 on surface from the silicon thin film of SOI.Its result can prevent to produce local highfield at drain electrode layer 20a, 20b and the interface of imbedding oxide-film 14, thereby can realize withstand voltageization of the transistorized height of SOI.
And, can utilize the current potential of the back-gate electrode control transistorized zone of action of SOI (active region), can carry out the transistorized threshold value control of SOI, improve the rising characteristic of the drain current in subthreshold value zone, and can relax the electric field of the raceway groove end of drain electrode layer 20a, 20b one side.Therefore, the SOI transistor is worked under low-voltage state, and can reduce the leakage current when ending.Power consumption in the time of can reducing work or standby simultaneously, improves the transistorized voltage endurance of SOI.
In addition, thicker by making the thickness of the 1st single-crystal semiconductor layer 13 that forms back-gate electrode than the thickness that forms transistorized the 2nd single-crystal semiconductor layer 15a of SOI, 15b, can realize the low resistanceization of back-gate electrode.Therefore, can enough low-voltages be controlled by the transistorized threshold position of SOI, and can realize the large tracts of landization of back-gate electrode, can reduce the number of connections that is connected in back-gate electrode, can suppress the increase of chip size.
Fig. 2 (a)～Figure 12 (a) is the vertical view of manufacture method of the semiconductor device of expression the 2nd execution mode of the present invention.Fig. 2 (b)～Figure 12 (b) is respectively the profile that the A1-A1 ' line～A11-A11 ' line in Fig. 2 (a)～Figure 12 (a) is cut open, and Fig. 2 (c)～Figure 12 (c) is respectively the profile that the B1-B1 ' line～B11-B11 ' line in Fig. 2 (a)～Figure 12 (a) is cut open.
In Fig. 2, on single crystalline semiconductor substrate 31,, single- crystal semiconductor layer 51,33,52,35 is stacked gradually by epitaxial growth.Here, the thickness of single-crystal semiconductor layer 33 can be thicker than the thickness of single-crystal semiconductor layer 35.And single-crystal semiconductor layer 51,52 can use the material of etch-rate greater than single crystalline semiconductor substrate 31 and single-crystal semiconductor layer 33,35.Particularly working as single crystalline semiconductor substrate 31 is under the situation of silicon, and 51, the 52 preferred SiGe that use make material as single-crystal semiconductor layer, and 33, the 35 preferred Si that use make material as single-crystal semiconductor layer.Therefore, can between single-crystal semiconductor layer 51,52 and single- crystal semiconductor layer 33,35, form lattice match, simultaneously, can guarantee the selection ratio between single-crystal semiconductor layer 51,52 and the single-crystal semiconductor layer 33,35.In addition, for the thickness of single- crystal semiconductor layer 51,33,52,35, can be set at for example degree of 1～100nm.
And, by the thermal oxidation of single-crystal semiconductor layer 35, form sacrificial oxidation film 53 on the surface of single-crystal semiconductor layer 35.Then, by methods such as CVD, all generating oxygen-proof film 54 on the sacrificial oxidation film 53.In addition, as oxygen-proof film 54, can use for example silicon nitride film.
Next, as shown in Figure 3,, oxygen-proof film 54, sacrificial oxidation film 53, single- crystal semiconductor layer 35,52,33,51 are carried out pattern form, form the groove 36 that single crystalline semiconductor substrate 31 is exposed along prescribed direction by utilization photoetching technique and etching technique.In addition, by under the situation about exposing, both can stop etching, also can form recess at single crystalline semiconductor substrate 31 by the over etching that single crystalline semiconductor substrate 31 is carried out to the surface of single crystalline semiconductor substrate 31 at single crystalline semiconductor substrate 31.And, can make the allocation position of groove 36 corresponding with the part of the element separated region of single-crystal semiconductor layer 33.
Then,, oxygen-proof film 54, sacrificial oxidation film 53, single-crystal semiconductor layer 35,52 are carried out pattern form by utilization photoetching technique and etching technique, form with groove 36 overlapping, than the wideer groove 37 of groove 36.Here, can make the allocation position of groove 37, corresponding with the element separated region of semiconductor layer 35.
And, also can replace the surface of single-crystal semiconductor layer 33 is exposed, stop etching on the surface of single-crystal semiconductor layer 52, also can carry out over etching, in the way of single-crystal semiconductor layer 52 to single-crystal semiconductor layer 52.Here, by stopping the etching of single-crystal semiconductor layer 52 on the way, can prevent that the surface of the single-crystal semiconductor layer 33 in the groove 36 from being exposed to the open air out.Therefore, when single-crystal semiconductor layer 51,52 being carried out etching and remove, can reduce single-crystal semiconductor layers 33 in the groove 36 and expose time in etching solution or etching gas to the open air, the single-crystal semiconductor layer 33 in can restrain tank 36 is by over etching.
Below, as shown in Figure 4,, forming supporter 56 at whole of single crystalline semiconductor substrate 31 by methods such as CVD, these supporter 56 landfills and are supported on single- crystal semiconductor layer 33,35 on the single crystalline semiconductor substrate 31 in groove 36,37.And, can use the material of silicon oxide layer as supporter 56.
Below, as shown in Figure 5, by utilization photoetching technique and etching technique, oxygen-proof film 54, sacrificial oxidation film 53, single- crystal semiconductor layer 35,52,33,51 are carried out pattern form, thereby, form the groove 38 that single crystalline semiconductor substrate 31 is exposed along the direction vertical with groove 36.And, under the situation that single crystalline semiconductor substrate 31 is exposed, can stop etching on the surface of single crystalline semiconductor substrate 31, also can be by single crystalline semiconductor substrate 31 be carried out over etching, and form recesses at single crystalline semiconductor substrate 31.In addition, can make the allocation position of groove 38, corresponding with the element separated region of single- crystal semiconductor layer 33,35.
Below, as shown in Figure 6, by groove 38, by etching solution is contacted with single-crystal semiconductor layer 51,52, thereby single-crystal semiconductor layer 51,52 is removed in etching, thereby between single crystalline semiconductor substrate 31 and single-crystal semiconductor layer 33, form blank part 57a, between single- crystal semiconductor layer 33,35, also form blank part 57b simultaneously.
Here, owing in groove 36,37, be provided with supporter 56, even under single-crystal semiconductor layer 51,52 removed situations, also can support semiconductor layer 33,35 on single crystalline semiconductor substrate 31, and, owing to except groove 36,37, also be provided with groove 38 in addition, thereby can make the single-crystal semiconductor layer 51,52 that under single- crystal semiconductor layer 33,35, disposes respectively can touch etching solution.Therefore, can under the condition of the crystalline quality that does not influence single- crystal semiconductor layer 33,35, realize the insulation between single- crystal semiconductor layer 33,35 and the single crystalline semiconductor substrate 31.
In addition, be the Si material at single crystalline semiconductor substrate 31, single- crystal semiconductor layer 33,35, single-crystal semiconductor layer 51,52 is under the situation of SiGe material, preferably uses the etching solution of hydrofluoric acid-nitric acid as single-crystal semiconductor layer 51,52.Therefore, the selection of Si and SiGe ratio can be set between 1: 100～1000, like this, promptly can remove single-crystal semiconductor layer 51,52, can suppress the over etching to single crystalline semiconductor substrate 31 and single- crystal semiconductor layer 33,35 again.
Below, as shown in Figure 7, by single crystalline semiconductor substrate 31 and single- crystal semiconductor layer 33,35 are carried out thermal oxidation, form in the blank part 57a between single crystalline semiconductor substrate 31 and single-crystal semiconductor layer 33 and imbed oxide-film 32, also form in the blank part 57b between single- crystal semiconductor layer 33,35 simultaneously and imbed oxide-film 34.And, in thermal oxidation, imbed under the situation of oxide- film 32,34 and form by single crystalline semiconductor substrate 31 and single- crystal semiconductor layer 33,35, imbed characteristic in order to improve it, preferred use can provide the method for the low temperature wet oxidation of the threshold of reaction.Here, form under the situation of imbedding oxide- film 32,34 in thermal oxidation by single crystalline semiconductor substrate 31 and single- crystal semiconductor layer 33,35, single crystalline semiconductor substrate 31 and single- crystal semiconductor layer 33,35 in the groove 38 are oxidized, form oxide-film 39 on the sidewall in groove 38.
Thus, the thickness of imbedding oxide- film 32,34 that forms during according to the thermal oxidation of the thickness of the single- crystal semiconductor layer 33,35 when the epitaxial growth and single- crystal semiconductor layer 33,35, thickness that can separate provision single- crystal semiconductor layer 33,35 after element separation.Therefore, can control accurately, in the discrete discrepancy of the thickness that reduces single- crystal semiconductor layer 33,35, can do single- crystal semiconductor layer 33,35 thinner the thickness of single-crystal semiconductor layer 33,35.And, owing on single-crystal semiconductor layer 35, be provided with oxygen-proof film 54, so the surface that can prevent single-crystal semiconductor layer 35 by thermal oxidation, and can form in the rear side of single-crystal semiconductor layer 35 and imbed oxide-film 34.
In addition, because the thickness of single-crystal semiconductor layer 33 is done thicklyer than the thickness of single-crystal semiconductor layer 35, even thereby below single- crystal semiconductor layer 33,35, formed respectively under the situation of blank part 57a, 57b, on single crystalline semiconductor substrate 31, also can stably support single- crystal semiconductor layer 33,35, single- crystal semiconductor layer 33,35 and imbed more even that the thickness of oxide- film 32,34 can do.
Below, as shown in Figure 8, adopt methods such as CVD, on supporter 56, pile up and imbed insulator 45, and with it with groove 38 landfills.In addition, can be with silicon oxide film as the material of imbedding insulator 45.
Below, as shown in Figure 9, by using CMP methods such as (cmps), to imbedding insulator 45 and supporter 56 is implemented filmings, and remove oxygen-proof film 54 and sacrificial oxidation film 53, thereby the surface of single-crystal semiconductor layer 35 is exposed.Then, by in single-crystal semiconductor layer 33, carrying out As, P, B, BF
2Ion Deng impurity injects IP1, impurity is imported the inside of single-crystal semiconductor layer 33.Here, for the stroke distances Rp that in single-crystal semiconductor layer 33, carries out the impurity that ion injects, preferably set in the darker position of central authorities than the film thickness direction of single-crystal semiconductor layer 33.
Like this, can suppress forming the damage that the transistorized single-crystal semiconductor layer 35 of SOI causes, simultaneously can also realize having low resistanceization as the single-crystal semiconductor layer 33 of back-gate electrode function, can be under the situation that does not make SOI characteristics of transistor deterioration, with the transistorized threshold position of low-voltage control SOI.
Below, as shown in figure 10,, form gate insulating film 41 on the surface of single-crystal semiconductor layer 35 by the thermal oxidation that the surface of single-crystal semiconductor layer 35 is carried out.And,, on the single-crystal semiconductor layer 35 that is formed with gate insulating film 41, form polysilicon layer by methods such as CVD.Then, by utilization photoetching technique and etching technique polysilicon layer is carried out pattern and form, thereby on single-crystal semiconductor layer 35, form gate electrode 42.
Below, as shown in figure 11, by gate electrode 42 as mask, in single-crystal semiconductor layer 35, carry out As, P, B, BF
2Inject IP2 in the ion of impurity, thereby on single-crystal semiconductor layer 35, form source layer 43a and the drain electrode layer 43b that gate electrode 42 is clipped in the middle and is configured.
Below, as shown in figure 12,, on gate electrode 42, pile up interlayer insulating film 44 by methods such as CVD.Then, on interlayer insulating film 44, form back of the body grid contact electrode 45a, 45b, it is embedded in interlayer insulating film 44 and supporter 56, and be connected with single-crystal semiconductor layer 33, and, form source electrode contact electrode 46a and drain electrode contact electrode 46b on interlayer insulating film 44, it is embedded in interlayer insulating film 44, and is connected with source layer 43a and drain electrode layer 43b respectively.
Like this, can reduce the generation of the defective of single- crystal semiconductor layer 33,35, configuration single- crystal semiconductor layer 33,35 on the oxide- film 32,34 can imbedded, do not use the SOI substrate, just can dispose the back-gate electrode of low resistanceization in the rear side of single-crystal semiconductor layer 35, and, can on single-crystal semiconductor layer 33, form the SOI transistor.Its result can suppress cost and rise, can reduce the SOI transistor by the time leakage current, and realize withstand voltageization of the transistorized height of SOI.
In addition, also can gate electrode 42 be electrically connected with single-crystal semiconductor layer 35 by back of the body grid contact electrode 45a, 45b.Therefore, back-gate electrode can be regulated and control become to have identical current potential with gate electrode 42, improve the ability of control channel region current potential.Therefore, can suppress the increase of chip size, reduce by the time leakage current, in the time of can reducing work or the power consumption during standby the time, realize high withstand voltageization of field-effect transistor.
Claims (5)
1. semiconductor device has:
The back-gate electrode that constitutes by the 1st single-crystal semiconductor layer that is formed on the 1st insulating barrier;
Be formed on the 2nd insulating barrier on described the 1st single-crystal semiconductor layer;
Be formed on described the 2nd insulating barrier, and the 2nd thin single-crystal semiconductor layer of described the 1st single-crystal semiconductor layer of Film Thickness Ratio;
Be formed on the gate electrode on described the 2nd single-crystal semiconductor layer; With
Be formed on described the 2nd single-crystal semiconductor layer, and be configured in the source of described gate electrode side respectively.
2. semiconductor device according to claim 1 is characterized in that also having:
The wiring layer that described back-gate electrode is electrically connected with described gate electrode.
3. the manufacture method of a semiconductor device comprises:
The operation of film forming the 1st single-crystal semiconductor layer on single crystalline semiconductor substrate;
On described the 1st single-crystal semiconductor layer, the operation of the 2nd single-crystal semiconductor layer that the film forming etch-rate is littler than described the 1st single-crystal semiconductor layer;
On described the 2nd single-crystal semiconductor layer, film forming has the operation with the 3rd single-crystal semiconductor layer of the same composition of described the 1st single-crystal semiconductor layer;
On described the 3rd single-crystal semiconductor layer, film forming has and the same composition of described the 2nd single-crystal semiconductor layer, and the operation of thin the 4th single-crystal semiconductor layer of described the 2nd single-crystal semiconductor layer of Film Thickness Ratio;
Form to connect described the 1st to the 4th single-crystal semiconductor layer, and make the operation of the 1st groove that described single crystalline semiconductor substrate exposes;
In described the 1st groove, form the operation that the described the 2nd and the 4th single-crystal semiconductor layer is supported on the supporter on the described single crystalline semiconductor substrate;
Form the operation of the 2nd groove, the 2nd groove makes at least a portion of the described the 1st and the 3rd single-crystal semiconductor layer that have formed described supporter, exposes from the described the 2nd and the 4th single-crystal semiconductor layer;
By the 1st and the 3rd single-crystal semiconductor layer being carried out selective etch, thereby respectively the described the 1st and the 3rd single-crystal semiconductor layer is removed, formed the operation of the 1st and the 2nd blank part via described the 2nd groove;
By described semiconductor substrate, the described the 2nd and the 4th single-crystal semiconductor layer are carried out thermal oxidation, thereby form the operation of imbedding oxide-film that is embedded in the described the 1st and the 2nd blank part respectively;
By described the 4th single-crystal semiconductor layer is carried out thermal oxidation, thereby on described the 4th single-crystal semiconductor layer, form the operation of gate insulating film;
Across described gate insulating film, on described the 4th single-crystal semiconductor layer, form the operation of gate electrode; With
Inject by described gate electrode is carried out ion as mask, thereby form the operation of the source that is configured in described gate electrode side respectively at described the 4th single-crystal semiconductor layer.
4. the manufacture method of semiconductor device according to claim 3 is characterized in that,
Described single crystalline semiconductor substrate and described the 2nd, the 4th single-crystal semiconductor layer are Si, and the described the 1st and the 3rd single-crystal semiconductor layer is SiGe.
5. according to the manufacture method of claim 3 or 4 described semiconductor devices, it is characterized in that,
Have the operation that foreign ion is injected into described the 2nd single-crystal semiconductor layer, the stroke distances of this impurity is set at the position darker than the central authorities of the film thickness direction of described the 2nd single-crystal semiconductor layer.
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