CN108054132A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN108054132A CN108054132A CN201711329059.5A CN201711329059A CN108054132A CN 108054132 A CN108054132 A CN 108054132A CN 201711329059 A CN201711329059 A CN 201711329059A CN 108054132 A CN108054132 A CN 108054132A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 152
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000002955 isolation Methods 0.000 claims abstract description 33
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 239000011148 porous material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
Semiconductor devices of the present invention and preparation method thereof, including：Semiconductor substrate is provided, including substrate, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer stacked gradually；The first fleet plough groove isolation structure is formed in second semiconductor layer；First fleet plough groove isolation structure, second insulating layer and the first semiconductor layer are etched, exposes first insulating layer, forms groove；Filled media layer forms the second fleet plough groove isolation structure in the trench, and second fleet plough groove isolation structure isolates remaining first semiconductor layer with substrate with first insulating layer；Through-hole structure or epitaxial layer are formed in the semiconductor substrate, is electrically picked out first semiconductor layer using the through-hole structure or epitaxial layer.In the present invention, the first semiconductor layer is completely isolated, and serves as backgate control, improves the driving current of transistor, is reduced OFF state electric leakage, is improved transistor characteristic.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
SOI is introduced between top layer semiconductors (being known as active layer) and substrate layer (can be semiconductor or dielectric)
Dielectric buried layer, by semiconductor devices or circuit production in active layer.Between integrated circuit mesohigh device, low-voltage circuit usually
Isolated using isolation channel, then isolated between active layer and substrate layer by dielectric layer.Therefore, with body silicon (semiconductor) skill
Art is compared, and SOI technology is small with ghost effect, and leakage current is small, and integrated level is high, capability of resistance to radiation is by force and without silicon-controlled self-locking
The advantages that effect, obtains extensive concern and application in fields such as high speed, high temperature, low-power consumption and radioresistances.
The key of SOI power integrated circuit technique be realize high voltage, low-power consumption and high voltage unit and low voltage unit it
Between be effectively isolated.It in SOI MOSFET elements, is usually biased in substrate layer, for increasing the control of grid, improves device
The performance of part.However, the isolation between different biass is generally realized by reversed PN, cause layout difficult and has electric leakage.
The content of the invention
It is an object of the invention to provide a kind of semiconductor devices and preparation method thereof, are buried with solving medium in the prior art
The technical issues of effect of leakage device transistor characteristic of layer.
In order to solve the above technical problems, the present invention provides a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, the semiconductor substrate includes the substrate, the first insulating layer, the first semiconductor that stack gradually
Layer, second insulating layer and the second semiconductor layer；
The first fleet plough groove isolation structure is formed in second semiconductor layer；
First fleet plough groove isolation structure, second insulating layer and the first semiconductor layer are etched, exposes described first absolutely
Edge layer forms groove；
In the trench filled media layer formed the second fleet plough groove isolation structure, second fleet plough groove isolation structure with
First insulating layer isolates remaining first semiconductor layer with substrate；
Through-hole structure or epitaxial layer are formed in the semiconductor substrate, using the through-hole structure or epitaxial layer by described in
First semiconductor layer electrically picks out.
Optionally, when first semiconductor layer is electrically picked out using through-hole structure, formed the through-hole structure it
Before further include：
Grid is formed in second semiconductor layer；
Ion implanting is carried out to the second semiconductor layer of the grid both sides, is respectively formed source region and drain region.
Optionally, when first semiconductor layer is electrically picked out using epitaxial layer, after the epitaxial layer is formed also
Including：
Grid is formed in second semiconductor layer；
Ion implanting is carried out to the second semiconductor layer of the grid both sides, is respectively formed source region and drain region.
Optionally, first insulating layer is silica, and thickness is 5nm~20nm.
Optionally, first semiconductor layer is monocrystalline silicon, and thickness is 10nm~30nm.
Optionally, the second insulating layer is silica, and thickness is 5nm~20nm.
Optionally, second semiconductor layer is monocrystalline silicon, and thickness is 10nm~30nm.
Correspondingly, the present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include substrate, the first insulating layer；
Positioned at the first semiconductor layer of the first insulating layer upper graphic distribution；
Positioned at the second semiconductor layer of the first semiconductor layer, there is the first shallow trench around second semiconductor layer
Isolation structure；
There is second insulating layer between first semiconductor layer and the second semiconductor layer；
There is the second fleet plough groove isolation structure between first semiconductor layer.
Optionally, further include：Positioned at the grid of second semiconductor layer；Positioned at the grid both sides source region and
Drain region.
Optionally, further include：Through-hole structure or epitaxial layer in the semiconductor substrate, using the through-hole structure
Or epitaxial layer electrically picks out first semiconductor layer.
Compared with prior art, semiconductor devices of the invention and preparation method thereof has the advantages that：
In the present invention, semiconductor substrate is using the substrate of stacking, the first insulating layer, the first semiconductor layer, second insulating layer
And second semiconductor layer structure, it is respectively formed the first fleet plough groove isolation structure, the second fleet plough groove isolation structure, and the second shallow ridges
Recess isolating structure isolates remaining first semiconductor layer with substrate with the first insulating layer.In the present invention, the first semiconductor layer quilt
It is completely isolated, backgate control is served as, improves the driving current of transistor, reduces OFF state electric leakage, improves transistor characteristic.
Description of the drawings
Fig. 1 is the flow chart of the semiconductor device fabrication processes in one embodiment of the invention；
Fig. 2 is the schematic diagram of semiconductor substrate in one embodiment of the invention；
Fig. 3 is the schematic diagram that the first fleet plough groove isolation structure is formed in one embodiment of the invention；
Fig. 4 is the schematic diagram that groove is formed in one embodiment of the invention；
Fig. 5 is the schematic diagram that the second fleet plough groove isolation structure is formed in one embodiment of the invention；
Fig. 6 is that grid, source region and the schematic diagram in drain region are formed in one embodiment of the invention；
Fig. 7 is diagrammatic cross-sections of the Fig. 6 along AA ' lines in one embodiment of the invention.
Specific embodiment
The schematic diagram of the semiconductor devices of the present invention is described in more detail below in conjunction with schematic diagram, wherein representing
The preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still real
The advantageous effects of the existing present invention.Therefore, description below is appreciated that for the widely known of those skilled in the art, and simultaneously
Not as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.It will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is, in semiconductor devices provided and preparation method thereof, provides semiconductor substrate, wraps
Include the substrate stacked gradually, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer；Described second
The first fleet plough groove isolation structure is formed in semiconductor layer；Etch first fleet plough groove isolation structure, second insulating layer and first
Semiconductor layer exposes first insulating layer, forms groove；In the trench filled media layer formed the second shallow trench every
From structure, second fleet plough groove isolation structure isolates remaining first semiconductor layer with substrate with first insulating layer；
Through-hole structure or epitaxial layer are formed in the semiconductor substrate, is led using the through-hole structure or epitaxial layer by described the first half
Body layer electrically picks out.In the present invention, the first semiconductor layer is completely isolated, and serves as backgate control, improves the driving electricity of transistor
Stream reduces OFF state electric leakage, improves transistor characteristic.
Semiconductor devices of the present invention and preparation method thereof is specifically described below in conjunction with attached drawing, Fig. 1 is preparation work
The method flow diagram of skill, Fig. 2~7 are the corresponding schematic diagram of each step, and preparation process of the invention includes the following steps：
Step S1 is performed, refering to what is shown in Fig. 2, providing semiconductor substrate 100, the semiconductor substrate 100 includes layer successively
Folded substrate 101, the first insulating layer 102, the first semiconductor layer 103,104 and second semiconductor layer 105 of second insulating layer.Its
In, substrate can be silicon substrate, first insulating layer 102 be silica, thickness be 5nm~20nm, first semiconductor
Layer 103 is monocrystalline silicon, and thickness is 10nm~30nm, and the second insulating layer 104 is silica, and thickness is 5nm~20nm, described
Second semiconductor layer 105 is monocrystalline silicon, and thickness is 10nm~30nm.That is, the semiconductor substrate in the present invention is SOIOI
Structure.
Step S2 is performed, refering to what is shown in Fig. 3, forming the first fleet plough groove isolation structure in second semiconductor layer 105
106, first shallow ditch groove structure 106 is formed using chemical vapor deposition silica.
Step S3 is performed, refering to what is shown in Fig. 4, the first fleet plough groove isolation structure 106, second insulating layer described in etched portions
104 and first semiconductor layer 103, first insulating layer 102 is exposed, forms groove 107.Specifically, the first shallow trench every
It can be realized by dry etch process from structure 106, second insulating layer 104, in etching process, retained close to the second semiconductor
First fleet plough groove isolation structure of layer prevents from damaging the second semiconductor layer during the first semiconductor layer of etching；First semiconductor
Layer 103 is realized by wet processing.The width of the groove 107 can be with 50nm~100nm.
Perform step S4, refering to what is shown in Fig. 5, be filled up completely in the groove 107 dielectric layer formed the second shallow trench every
From structure 108, second shallow ditch groove structure 108 is formed using chemical vapor deposition silica.
Step S5 is performed, refering to what is shown in Fig. 6, forming device architecture on the semiconductor substrate, specifically：Described
Two semiconductor layers, 105 top forms grid 109, and the grid 109 includes grid oxic horizon and polysilicon layer, to the grid
Second semiconductor layer 105 of 109 both sides carries out ion implanting, is respectively formed source region 110 and drain region 111.Then, with reference to 7 institute of figure
Show, remaining first semiconductor layer 103 is electrically picked out.Through-hole structure 113 is formed in the semiconductor substrate, using described
Through-hole structure 113 electrically picks out first semiconductor layer, that is, etches the second fleet plough groove isolation structure and second insulating layer, shape
Into contact hole or through hole, and metal layer is filled in the trench and forms through-hole structure 113, using through-hole structure 113 by described first
Semiconductor layer 103 electrically picks out.In the present invention, the first semiconductor layer is completely isolated, and is served as backgate control, is improved transistor
Driving current reduces OFF state electric leakage, improves transistor characteristic.
However, for step S5, it, in another embodiment of the invention can also be first by first with reference to shown in figure 6, Fig. 7
Semiconductor layer electrically picks out, and forms device architecture afterwards.Specifically：Epitaxial layer is first formed in the semiconductor substrate, for example, it is more
Crystal silicon epitaxial layer is electrically picked out first semiconductor layer 103 using epitaxial layer.Then, in second semiconductor layer 105
Top forms grid 109, and the grid 109 includes grid oxic horizon and polysilicon layer, to the second the half of 109 both sides of grid
Conductor layer 105 carries out ion implanting, is respectively formed source region 110 and drain region 111.In same the present embodiment, the first semiconductor layer
It is completely isolated, serves as backgate control, improve the driving current of transistor, reduce OFF state electric leakage, improve transistor characteristic.
Correspondingly, with reference to shown in figure 6, Fig. 7, another aspect of the present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include substrate 101, the first insulating layer 102；
Positioned at the first semiconductor layer 103 of 102 upper graphic of the first insulating layer distribution；
The second semiconductor layer 105 above the first semiconductor layer 103 has around second semiconductor layer 105
First fleet plough groove isolation structure 106；
There is second insulating layer 104 between first semiconductor layer, 103 and second semiconductor layer 105；
There is the second fleet plough groove isolation structure 108 between first semiconductor layer 103.
Further, semiconductor devices of the invention further includes：Grid above second semiconductor layer 105
110；Positioned at the source region 110 of 109 both sides of grid and drain region 111.
Further, semiconductor devices of the invention further includes：Through-hole structure or outer in the semiconductor substrate
Prolong layer 112, electrically picked out first semiconductor layer 103 using the through-hole structure or epitaxial layer 112.
In conclusion in semiconductor devices provided by the invention and preparation method thereof, semiconductor substrate is using the lining being stacked
Bottom, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer structure, be respectively formed the first shallow trench every
Remaining the first half are led from structure, the second fleet plough groove isolation structure, and the second fleet plough groove isolation structure and the first insulating layer
Body layer is isolated with substrate.In the present invention, the first semiconductor layer is completely isolated, and serves as backgate control, improves the driving of transistor
Electric current reduces OFF state electric leakage, improves transistor characteristic.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
Claims (10)
1. a kind of preparation method of semiconductor devices, which is characterized in that including：
There is provided semiconductor substrate, the semiconductor substrate include stack gradually substrate, the first insulating layer, the first semiconductor layer,
Second insulating layer and the second semiconductor layer；
The first fleet plough groove isolation structure is formed in second semiconductor layer；
First fleet plough groove isolation structure, second insulating layer and the first semiconductor layer are etched, exposes first insulating layer,
Form groove；
In the trench filled media layer formed the second fleet plough groove isolation structure, second fleet plough groove isolation structure with it is described
First insulating layer isolates remaining first semiconductor layer with substrate；
Through-hole structure or epitaxial layer are formed in the semiconductor substrate, using the through-hole structure or epitaxial layer by described first
Semiconductor layer electrically picks out.
2. the preparation method of semiconductor devices as described in claim 1, which is characterized in that using through-hole structure by described first
When semiconductor layer electrically picks out, further included before the through-hole structure is formed：
Grid is formed in second semiconductor layer；
Ion implanting is carried out to the second semiconductor layer of the grid both sides, is respectively formed source region and drain region.
3. the preparation method of semiconductor devices as described in claim 1, which is characterized in that using epitaxial layer by described the first half
When conductor layer electrically picks out, further included after the epitaxial layer is formed：
Grid is formed in second semiconductor layer；
Ion implanting is carried out to the second semiconductor layer of the grid both sides, is respectively formed source region and drain region.
4. the preparation method of semiconductor devices as described in claim 1, which is characterized in that first insulating layer is oxidation
Silicon, thickness are 5nm~20nm.
5. the preparation method of semiconductor devices as described in claim 1, which is characterized in that first semiconductor layer is monocrystalline
Silicon, thickness are 10nm~30nm.
6. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the second insulating layer is oxidation
Silicon, thickness are 5nm~20nm.
7. the preparation method of semiconductor devices as described in claim 1, which is characterized in that second semiconductor layer is monocrystalline
Silicon, thickness are 10nm~30nm.
8. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include substrate, the first insulating layer；
Positioned at the first semiconductor layer of the first insulating layer upper graphic distribution；
There is the isolation of the first shallow trench positioned at the second semiconductor layer of the first semiconductor layer, around second semiconductor layer
Structure；
There is second insulating layer between first semiconductor layer and the second semiconductor layer；
There is the second fleet plough groove isolation structure between first semiconductor layer.
9. semiconductor devices as claimed in claim 8, which is characterized in that further include：Positioned at second semiconductor layer
Grid；Source region and drain region positioned at the grid both sides.
10. semiconductor devices as claimed in claim 8, which is characterized in that further include：It is logical in the semiconductor substrate
Pore structure or epitaxial layer are electrically picked out first semiconductor layer using the through-hole structure or epitaxial layer.
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| CN201711329059.5A CN108054132A (en) | 2017-12-13 | 2017-12-13 | Semiconductor devices and preparation method thereof |
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| CN109767985A (en) * | 2019-01-22 | 2019-05-17 | 上海华虹宏力半导体制造有限公司 | A kind of silicon-on-insulator RF switching devices and its manufacturing method |
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| CN107123619A (en) * | 2016-02-24 | 2017-09-01 | 格罗方德半导体公司 | The method for forming isolation structure in Semiconductor substrate on insulator |
| CN107946230A (en) * | 2017-11-15 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108550591A (en) * | 2018-06-20 | 2018-09-18 | 上海华虹宏力半导体制造有限公司 | SOI substrate structure and preparation method thereof, semiconductor devices and preparation method thereof |
| CN109767985A (en) * | 2019-01-22 | 2019-05-17 | 上海华虹宏力半导体制造有限公司 | A kind of silicon-on-insulator RF switching devices and its manufacturing method |
| CN109767985B (en) * | 2019-01-22 | 2022-02-15 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switch device and manufacturing method thereof |
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