CN108074965A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN108074965A CN108074965A CN201711330960.4A CN201711330960A CN108074965A CN 108074965 A CN108074965 A CN 108074965A CN 201711330960 A CN201711330960 A CN 201711330960A CN 108074965 A CN108074965 A CN 108074965A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000000926 separation method Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 238000002955 isolation Methods 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims 1
- 239000011148 porous material Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
Semiconductor devices of the present invention and preparation method thereof, including：Semiconductor substrate is provided, including substrate, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer stacked gradually；It is formed in part semiconductor substrate surface and sacrifices grid；Ion implanting carries out semiconductor substrate using high current oxygen plasma, injection depth corresponds to the first semiconductor layer；Grid is sacrificed in removal, and carries out thermal anneal process, and oxidation, which does not cover, sacrifices the corresponding first semiconductor layer formation oxide layer of grid, and oxide layer, the first insulating layer and second insulating layer separation layer isolate the first semiconductor layer of part sacrificed below grid with substrate；Through-hole structure or epitaxial layer are formed in semiconductor substrate, the first semiconductor layer is electrically picked out.In the present invention, isolated using the first semiconductor layer that body end electrically picks out is made by separation layer with substrate, serve as backgate control, suitable bias voltage can be loaded as needed, prevent from leaking electricity, improve the radiofrequency characteristics of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
SOI is introduced between top layer semiconductors (being known as active layer) and substrate layer (can be semiconductor or dielectric)
Dielectric buried layer, by semiconductor devices or circuit production in active layer.Between integrated circuit mesohigh device, low-voltage circuit usually
Isolated using isolation channel, then isolated between active layer and substrate layer by dielectric layer.Therefore, with body silicon (semiconductor) skill
Art is compared, and SOI technology is small with ghost effect, and leakage current is small, and integrated level is high, capability of resistance to radiation is by force and without silicon-controlled self-locking
The advantages that effect, obtains extensive concern and application in fields such as high speed, high temperature, low-power consumption and radioresistances.
The key of SOI power integrated circuit technique be realize high voltage, low-power consumption and high voltage unit and low voltage unit it
Between be effectively isolated.It in SOI MOSFET elements, is usually biased in substrate layer, for increasing the control of grid, improves device
The performance of part.However, the isolation between different biass is generally realized by reversed PN, cause layout difficult and has electric leakage.
The content of the invention
It is an object of the invention to provide a kind of semiconductor devices and preparation method thereof, are buried with solving medium in the prior art
The technical issues of effect of leakage device radiofrequency characteristics of layer.
In order to solve the above technical problems, the present invention provides a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, the semiconductor substrate includes the substrate, the first insulating layer, the first semiconductor that stack gradually
Layer, second insulating layer and the second semiconductor layer；
In part, the semiconductor substrate surface, which is formed, sacrifices grid；
Ion implanting carries out the semiconductor substrate using high current oxygen plasma, injection depth corresponds to described first
Semiconductor layer；
The sacrifice grid is removed, and carries out thermal anneal process, oxidation does not cover the sacrifice grid corresponding the first half
Conductor layer forms oxide layer, and the oxide layer, the first insulating layer and second insulating layer separation layer will sacrifice the part below grid
First semiconductor layer is isolated with the substrate；
Through-hole structure or epitaxial layer are formed in the semiconductor substrate, using the through-hole structure or epitaxial layer by described in
First semiconductor layer electrically picks out.
Optionally, further included after carrying out thermal anneal process to the semiconductor substrate：
Second semiconductor layer is etched, forms groove, the groove is filled and forms fleet plough groove isolation structure；
In part, the semiconductor substrate surface forms grid；
Ion implanting is carried out to the second semiconductor layer of the grid both sides, is respectively formed source region and drain region.
Optionally, first insulating layer is silica, and thickness is 5nm~20nm.
Optionally, first semiconductor layer is monocrystalline silicon, and thickness is 10nm~30nm.
Optionally, the second insulating layer is silica, and thickness is 5nm~20nm.
The preparation method of semiconductor devices as described in claim 1, which is characterized in that second semiconductor layer is single
Crystal silicon, thickness are 10nm~30nm.
Local accent, another aspect of the present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include substrate, separation layer and the second semiconductor layer；
Positioned at the grid of the semiconductor substrate surface；
There is the first semiconductor layer being located at below the grid, the separation layer is by described the first half in the separation layer
Conductor layer is kept apart with the substrate.
Optionally, further include：Fleet plough groove isolation structure around the grid；Source region positioned at the grid both sides
And drain region.
Optionally, further include：Through-hole structure or epitaxial layer in the semiconductor substrate, using the through-hole structure
Or epitaxial layer electrically picks out first semiconductor layer.
Compared with prior art, semiconductor devices of the invention and preparation method thereof has the advantages that：
In the present invention, semiconductor substrate is using the substrate of stacking, the first insulating layer, the first semiconductor layer, second insulating layer
And second semiconductor layer structure, and the first semiconductor layer of oxidized portion so that the first semiconductor layer electrically picked out as body end
Isolated by separation layer with substrate, serve as backgate control, suitable bias voltage, anti-leak-stopping can be loaded as needed
Electricity improves the radiofrequency characteristics of device.
Description of the drawings
Fig. 1 is the flow chart of the semiconductor device fabrication processes in one embodiment of the invention；
Fig. 2 is the schematic diagram of semiconductor substrate in one embodiment of the invention；
Fig. 3 is the schematic diagram of separation layer in one embodiment of the invention；
Fig. 4 is the schematic diagram of semiconductor devices in one embodiment of the invention；
Fig. 5 is diagrammatic cross-sections of the Fig. 4 along AA ' lines in one embodiment of the invention.
Specific embodiment
The schematic diagram of the semiconductor devices of the present invention is described in more detail below in conjunction with schematic diagram, wherein representing
The preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still real
The advantageous effects of the existing present invention.Therefore, description below is appreciated that for the widely known of those skilled in the art, and simultaneously
Not as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.It will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is, in semiconductor devices provided and preparation method thereof, provides semiconductor substrate, wraps
Include the substrate stacked gradually, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer；Partly partly leading
Structure base board surface, which is formed, sacrifices grid；Ion implanting is carried out to semiconductor substrate using oxygen plasma；Grid is sacrificed in removal, and
Thermal anneal process is carried out, oxidation, which does not cover, sacrifices the corresponding first semiconductor layer formation oxide layer of grid, the oxide layer, first
Insulating layer and second insulating layer separation layer isolate the first semiconductor layer of part sacrificed below grid with substrate；In semiconductor
Through-hole structure or epitaxial layer are formed in substrate, is electrically picked out the first semiconductor layer using through-hole structure or epitaxial layer.The present invention
In so that isolated as the first semiconductor layer that body end electrically picks out by separation layer with substrate, serve as backgate control, energy
It is enough to load suitable bias voltage as needed, it prevents from leaking electricity, improves the radiofrequency characteristics of device.
Semiconductor devices of the present invention and preparation method thereof is specifically described below in conjunction with attached drawing, Fig. 1 is preparation work
The method flow diagram of skill, Fig. 2~5 are the corresponding schematic diagram of each step, and preparation process of the invention includes the following steps：
Step S1 is performed, refering to what is shown in Fig. 2, providing semiconductor substrate 100, the semiconductor substrate 100 includes layer successively
Folded substrate 101, the first insulating layer 102, the first semiconductor layer 103,104 and second semiconductor layer 105 of second insulating layer.Its
In, substrate can be silicon substrate, first insulating layer 102 be silica, thickness be 5nm~20nm, first semiconductor
Layer 103 is monocrystalline silicon, and thickness is 10nm~30nm, and the second insulating layer 104 is silica, and thickness is 5nm~20nm, described
Second semiconductor layer 105 is monocrystalline silicon, and thickness is 10nm~30nm.That is, the semiconductor substrate in the present invention is SOIOI
Structure.
Step S2 is performed, with continued reference to shown in Fig. 2, is formed on part 100 surface of semiconductor substrate and sacrifices grid
106.Specifically, in 105 surface deposit polycrystalline silicon layer of the second semiconductor layer, and grid is sacrificed in graphical polysilicon layer, formation.
Step S3 is performed, refering to what is shown in Fig. 3, using high current oxygen plasma (O+plasma) to the semiconductor substrate
100 carry out ion implanting, and injection depth corresponds to first semiconductor layer, and oxygen plasma can be stopped by sacrificing grid 106, be protected
Stay the first semiconductor layer of part not oxidized.
Step S4 is performed, with continued reference to shown in Fig. 3, removes the sacrifice grid 106, and the to carrying out O +ion implanted
Semi-conductor layer carries out thermal anneal process, and corresponding first semiconductor layer around the sacrifice grid 106 is not covered so as to aoxidize
103 form oxide layer, and the oxide layer, the first insulating layer and second insulating layer separation layer 107 will sacrifice 106 lower section of grid
The first semiconductor layer 103 ' of part is isolated with the substrate 101.
Then, refering to what is shown in Fig. 4, also being wrapped after carrying out ion implanting to the semiconductor substrate 100 using oxygen plasma
It includes：
Second semiconductor layer 105 is etched, forms groove, the groove is filled and forms fleet plough groove isolation structure 107；
Grid 106 ' is formed at the former position for sacrificing grid 106；
Ion implanting is carried out to the second semiconductor layer 105 of the 106 ' both sides of grid, is respectively formed source region (Source)
109 and drain region (Drain) 110.
Step S5 is performed, remaining first semiconductor layer is electrically picked out.Refering to what is shown in Fig. 5, in the semiconductor
Through-hole structure 111 is formed in substrate 100, that is, etches fleet plough groove isolation structure and separation layer 107, forms contact hole or through hole, and
Metal layer is filled in the trench and forms through-hole structure, is electrically picked out first semiconductor layer using through-hole structure.However,
In another embodiment of the present invention, epitaxial layer, such as polysilicon epitaxial layer can also be formed in the semiconductor substrate, is used
Epitaxial layer electrically picks out first semiconductor layer 103 '.In the present invention so that electrically picked out as body end (Body)
Semi-conductor layer 103 ' is isolated by separation layer 107 with substrate 101, serves as backgate control, can load conjunction as needed
Suitable bias voltage prevents from leaking electricity, and improves the radiofrequency characteristics of device.
Correspondingly, with reference to shown in figure 4, Fig. 5, the present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include substrate 101,107 and second semiconductor layer 105 of separation layer；
Positioned at the grid 106 ' of the semiconductor substrate surface；
There is the first semiconductor layer 103 ' for being located at 106 lower section of grid, the separation layer in the separation layer 107
107 keep apart first semiconductor layer 103 ' and the substrate 101.
Further, semiconductor devices of the invention further includes：Shallow trench isolation junction around the grid 106 '
Structure 108, positioned at the source region 109 of the grid both sides and drain region 110.
Further, semiconductor devices of the invention further includes：Through-hole structure 111 in the semiconductor substrate,
First semiconductor layer 103 ' is electrically picked out using through-hole structure 111.On the other hand the semiconductor devices of the present invention also wraps
It includes：Epitaxial layer in the semiconductor substrate is electrically picked out first semiconductor layer using epitaxial layer.
In conclusion in semiconductor devices provided by the invention and preparation method thereof, semiconductor substrate is using the lining being stacked
Bottom, the first insulating layer, the first semiconductor layer, second insulating layer and the second semiconductor layer structure, and the first semiconductor of oxidized portion
Layer so that isolated as the first semiconductor layer that body end electrically picks out by separation layer with substrate, serve as backgate control, energy
It is enough to load suitable bias voltage as needed, it prevents from leaking electricity, improves the radiofrequency characteristics of device.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
Claims (9)
1. a kind of preparation method of semiconductor devices, which is characterized in that including：
There is provided semiconductor substrate, the semiconductor substrate include stack gradually substrate, the first insulating layer, the first semiconductor layer,
Second insulating layer and the second semiconductor layer；
In part, the semiconductor substrate surface, which is formed, sacrifices grid；
Ion implanting carries out the semiconductor substrate using high current oxygen plasma, injection depth corresponds to described the first half and leads
Body layer；
The sacrifice grid is removed, and carries out thermal anneal process, oxidation does not cover corresponding first semiconductor of the sacrifice grid
Layer forms oxide layer, and the oxide layer, the first insulating layer and second insulating layer separation layer will sacrifice the part first below grid
Semiconductor layer is isolated with the substrate；
Through-hole structure or epitaxial layer are formed in the semiconductor substrate, using the through-hole structure or epitaxial layer by described first
Semiconductor layer electrically picks out.
2. the preparation method of semiconductor devices as described in claim 1, which is characterized in that heat is carried out to the semiconductor substrate
It is further included after annealing：
Second semiconductor layer is etched, forms groove, the groove is filled and forms fleet plough groove isolation structure；
In part, the semiconductor substrate surface forms grid；Ion note is carried out to the second semiconductor layer of the grid both sides
Enter, be respectively formed source region and drain region.
3. the preparation method of semiconductor devices as described in claim 1, which is characterized in that first insulating layer is oxidation
Silicon, thickness are 5nm~20nm.
4. the preparation method of semiconductor devices as described in claim 1, which is characterized in that first semiconductor layer is monocrystalline
Silicon, thickness are 10nm~30nm.
5. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the second insulating layer is oxidation
Silicon, thickness are 5nm~20nm.
6. the preparation method of semiconductor devices as described in claim 1, which is characterized in that second semiconductor layer is monocrystalline
Silicon, thickness are 10nm~30nm.
7. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include substrate, separation layer and the second semiconductor layer；
Positioned at the grid of the semiconductor substrate surface；
There is the first semiconductor layer being located at below the grid, the separation layer is by first semiconductor in the separation layer
Layer is kept apart with the substrate.
8. semiconductor devices as claimed in claim 7, which is characterized in that further include：Shallow trench around the grid
Isolation structure；Source region and drain region positioned at the grid both sides.
9. semiconductor devices as claimed in claim 7, which is characterized in that further include：It is logical in the semiconductor substrate
Pore structure or epitaxial layer are electrically picked out first semiconductor layer using the through-hole structure or epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711330960.4A CN108074965A (en) | 2017-12-13 | 2017-12-13 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711330960.4A CN108074965A (en) | 2017-12-13 | 2017-12-13 | Semiconductor devices and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108074965A true CN108074965A (en) | 2018-05-25 |
Family
ID=62158457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711330960.4A Pending CN108074965A (en) | 2017-12-13 | 2017-12-13 | Semiconductor devices and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109767985A (en) * | 2019-01-22 | 2019-05-17 | 上海华虹宏力半导体制造有限公司 | A kind of silicon-on-insulator RF switching devices and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102590A (en) * | 1999-09-29 | 2001-04-13 | Agency Of Ind Science & Technol | Method for fabrication of semiconductor device |
| JP2003324199A (en) * | 2002-05-01 | 2003-11-14 | Sony Corp | Method for manufacturing semiconductor device |
| CN102945851A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Silicon on insulator structure and semiconductor device structure |
-
2017
- 2017-12-13 CN CN201711330960.4A patent/CN108074965A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102590A (en) * | 1999-09-29 | 2001-04-13 | Agency Of Ind Science & Technol | Method for fabrication of semiconductor device |
| JP2003324199A (en) * | 2002-05-01 | 2003-11-14 | Sony Corp | Method for manufacturing semiconductor device |
| CN102945851A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Silicon on insulator structure and semiconductor device structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109767985A (en) * | 2019-01-22 | 2019-05-17 | 上海华虹宏力半导体制造有限公司 | A kind of silicon-on-insulator RF switching devices and its manufacturing method |
| CN109767985B (en) * | 2019-01-22 | 2022-02-15 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switch device and manufacturing method thereof |
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