KR100559115B1 - Fabrication Method of MOSFET - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and by manufacturing a device having a gate shape of a 'T' shape using an SOI substrate to which silicon and silicon germanium epitaxy technology are applied, a conventional 'T' shape While retaining the characteristics of the gate device, the channel uses a thin epitaxially grown silicon epi layer to make the fully depleted type of operation desirable for ultra-fine field effect transistors. The use of epitaxially grown silicon germanium epilayers reduces the source / drain series resistance, and further improves the process for forming the region where the channel of the field effect transistor is to be formed, thereby improving the thickness of the silicon layer in the channel region. It provides a way to implement uniformity and reproducibility.

Electric field, Effect, Transistor, Sidewalls, Germanium, Epitaxy, SOI

Description

Fabrication Method of MOSFET

1 to 14 are cross-sectional views showing the manufacturing process of the field effect transistor according to the present invention.

15 is an electrical characteristic chart comparing the characteristics of the linear region transconductance in the case of a silicon substrate and in the case of using silicon germanium.

<Description of the symbols for the main parts of the drawings>

DESCRIPTION OF SYMBOLS 1 Handle silicon substrate 2 First silicon oxide film

3: host silicon substrate 3 ': portion of host silicon substrate including silicon buffer layer 4: silicon germanium epi layer

5: silicon epi layer 6: second silicon oxide film

7: Line indicating peak value of hydrogen ion concentration

8 silicon oxide film buffer layer 9 silicon nitride film layer

10: first sidewall 11: gate insulating film

12 gate electrode 13 second side wall

14: silicide layer

The present invention relates to a method for manufacturing a field effect transistor, and more specifically, to implement a silicon on insulator (SOI) substrate by applying silicon and germanium epitaxy technology The present invention relates to a method of manufacturing a metal-oxide-semiconductor field effect transistor (hereinafter referred to as a 'MOSFET') having a 'T'-shaped gate shape.

In general, MOSFETs have been reduced in device size while reducing gate length of devices as part of high performance and high integration. In order to implement a transistor having a very small channel length, there has also been a need to effectively suppress a short channel effect in which the potential of the channel region is affected by the drain voltage.

As a way to effectively suppress such short channel effects, a method of making MOSFETs on SOI substrates instead of bulk silicon has been studied for several years.

In the case of a MOSFET fabricated on an SOI substrate, device characteristics may vary according to the fully depleted type and partially depleted type operating modes as follows.

First, a device having a fully depleted mode of operation does not generate floating body characteristics such as a kink effect due to the floating of the substrate as the channel is completely depleted, and a subthreshold characteristic. And short channel characteristics. In addition, the drain saturation current is increased due to an increase in channel mobility due to a lower vertical electric field. However, devices with this fully depleted mode of operation have a very large source / drain series resistance in the SOI substrate used for the fully depleted operation, resulting in a small drain current, and a silicide process in the source / drain regions of the MOSFET device manufacturing process. This thin SOI substrate makes it difficult to apply, but rather has the disadvantage that junction breakdown can occur.

In contrast, a device having a partially depleted mode of operation has the opposite characteristics of the advantages and disadvantages of the device having a fully depleted mode of operation described above. In addition, a device having a partially depleted mode of operation may cause the substrate voltage to become unstable due to the floating body, which may adversely affect the MOSFET circuit design.

As a result, a method of fabricating a MOSFET having a very small channel length on an SOI substrate is required to develop a process capable of overcoming the disadvantages of a device performing a fully depleted operation.

In addition, the gate forming method of the MOSFET has been used for several years ago by forming the gate through partial oxidation and optical method (US Patent No. 6,060,749), and using the sidewall made in the channel direction than the originally designed gate length A study for forming a reduced gate structure (Japanese Laid-Open Patent Publication H07-038095) has been proposed, but the need for process improvement has been raised in order to use it as an actual device fabrication.

In addition, the present applicant has proposed a method of manufacturing a MOSFET having a 'T' gate shape through an improved process than Japanese Patent Application Publication No. 10-2002-26415 through Japanese Patent Application Publication No. H07-038095.

However, in Korean Patent Application No. 10-2002-26415, the source / drain has a limit in reducing the series resistance of the source / drain by using the silicon layer as it is, and the nitride film sequentially removed in forming the region where the gate is to be formed. It was difficult to uniformly form the thickness T ₂ of the second silicon layer in the channel region over the entire wafer by performing the process only by dry etching the second silicon layer using the superoxide film as a mask (usually a semiconductor dry type). In the etching process, the uniformity according to the wafer position is about 10-15% of the standard deviation), and also, in view of the reproducibility of the manufacturing process, a predetermined thickness of the second silicon layer in the channel region is required for the MOSFET fabricated on the SOI substrate to be fully depleted. T ₂ ) should be guaranteed, which is conventionally dependent on the etch rate and therefore the line width of the etching equipment or defined grooves. Due to the difference in the process environment such as the difference in the loading effect according to (L1), there was a problem that it is difficult to accurately reproduce the thickness T ₂ of the second silicon layer in the channel region.

Accordingly, the present invention has been made to solve the problems described above, by applying a silicon and silicon germanium epitaxy technology to implement an SOI substrate, through which the channel is thin epitaxially grown silicon of SOI By using epitaxial layers and source / drain epitaxially grown silicon germanium epitaxial layers, the series resistance of the source / drain is reduced, further improving the process for forming the region where the channel of the field effect transistor is to be formed. The purpose of the present invention is to provide a method for fabricating a silicon layer of a channel region with uniformity and reproducibility, thereby providing an improved method of manufacturing a MOSFET.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, as shown in FIG. 1, two bulk silicon substrates are used to artificially prepare an SOI substrate. The handle silicon substrate 1 obtains a high quality first silicon oxide layer 2 through a thermal oxidation process or the like. At this time, the oxidation process for the first silicon oxide layer may be a dry or wet method, and the thickness of the final first silicon oxide layer is preferably 100 nm or more, which is preferable for the desired device characteristics and subsequent processes.

Meanwhile, a silicon buffer layer having a thickness of about 15 to 40 nm is deposited on the host silicon substrate 3, and then silicon germanium epi deposition and silicon epi deposition are sequentially performed. In this case, the composition ratio of silicon and germanium of the silicon germanium epitaxial layer 4 is preferably set to about 0.7 in Si _X Ge _1-X to about 0.7, and to be implemented as a field effect transistor having a gate length of 40 nm or less. The thickness of the silicon germanium epitaxial layer 4 is 30 nm or more and the thickness of the silicon epitaxial layer 5 is 10 nm or less, respectively, to reduce the subsequent process and desired device characteristics, that is, the source / drain series resistance, and the MOSFET is completely depleted. It is desirable to work with. More specifically, in the MOSFET structure using the SOI substrate, the silicon layer thickness of the channel region must satisfy 1/4 of the gate length in order for the device to operate in a fully depleted type. It is important to fit.

Subsequently, a second silicon oxide layer 6 is deposited on the silicon epitaxial layer 5, and hydrogen ions are implanted into the entire upper surface of the oxide layer. In this case, the second silicon oxide layer 6 facilitates later bonding to the handle silicon substrate 1 and prevents damage to the silicon epitaxial layer 5 during hydrogen ion implantation and bonding to the handle silicon substrate. Do it. In this case, the deposition of the second silicon oxide layer may use chemical vapor deposition, but it is possible to produce a high quality thin film having better interfacial properties through oxidation. In particular, when using a low temperature ozone oxidation process, it is a low temperature thermal process of 600 ℃ or less, which can make a high quality oxide film of uniform and very thin thickness (a few nm level). The interface state between the oxide layer and the silicon epi layer can be improved while less affecting the substrate. The deposited silicon film may be used to bond the handle silicon substrate and the host silicon substrate through the following process, but in order to form a thicker oxide film, an additional chemical vapor deposition process may be performed to obtain a few nm oxide film. It is also possible to make an oxide film having a thickness of 10 to 50 nm and proceed with the subsequent bonding process. Since the hydrogen ion implantation is to separate a part of the host substrate after bonding with the handle silicon substrate, the peak value of the implanted hydrogen ion concentration is formed beyond the silicon germanium layer 5 as shown by the dotted line 7 of FIG. 1. Ion implantation energy should be controlled as much as possible. For example, a silicon buffer layer of about 15 to 40 nm is disposed on a host substrate, and a silicon germanium epi layer of about 30 nm, a silicon epi layer of less than 10 nm, and an oxide layer of about 10 to 50 nm are deposited thereon. When hydrogen ions are injected at an energy of 150-200 keV at a dose of 1x10 ¹⁶ / cm ² or more, it is appropriate.

The hydrogen ion implantation may be performed before the deposition of the silicon buffer layer on the host silicon substrate 3 in a reversed order. By doing so, it is possible to prevent damage to the silicon epitaxial layer 5 due to hydrogen ion injection as much as possible, and also to lower the dose energy (100 to 150 keV). However, there is a limitation in that a low temperature process must be performed to minimize post-diffusion of hydrogen ions when depositing the silicon buffer layer / silicon germanium epi layer / silicon epi layer / second silicon oxide layer that is performed after hydrogen ion implantation. Therefore, in this embodiment, in particular, the deposition of the second silicon oxide film layer is an ozone oxidation process rather than a normal thermal process. oxidation) should be used.

Thereafter, the two silicon substrates obtained above are combined through a thermal annealing process, and then a thermal annealing process in a nitrogen atmosphere is performed to partially cover the host substrate with a dotted line 7 which is a peak of an ion implanted hydrogen concentration. Are separated from the host substrate associated with the handle silicon substrate. At this time, the thermal process for bonding is performed through annealing at 250 ° C. for at least 4 hours, and the thermal process for separation of host silicon is preferably performed at about 550 ° C. for 10 minutes in a nitrogen atmosphere. In this case, as shown in FIG. 2, the second silicon oxide layer 6, the silicon epitaxial layer 5, and the silicon germanium epitaxially deposited on the host substrate are formed on the first silicon oxide layer 2 of the handle silicon substrate 1. Only part 3 'of the host silicon substrate, including layer 4, and the silicon buffer layer is left.

Next, a portion 3 'of the host silicon substrate including the silicon buffer layer remaining on the silicon germanium epi layer of FIG. 2 is removed to complete the SOI substrate to which the silicon germanium epi layer is exposed (FIG. 3). To this end, when the silicon substrate of FIG. 2 is immersed in a solution containing 10% KOH, the silicon is etched at about 30 nm per minute at room temperature, and the selectivity of silicon and silicon germanium is 20: 1, so that the silicon germanium epi layer 4 is excellent. As an etch stop layer, only a portion 3 'of the host silicon substrate including the silicon buffer layer on the silicon germanium epi layer 4 may be removed as shown in FIG. 3.

Subsequently, the silicon oxide film buffer layer 8 and the silicon nitride film layer 9 are sequentially deposited on the top of FIG. 3 (FIG. 4). At this time, if the silicon oxide film buffer layer 8 is about 10 nm, the silicon nitride film layer 9 is preferably 50 to 70 nm.

Thereafter, an etching mask is formed by a photolithography process, and then the silicon nitride layer 9 and the silicon oxide buffer layer 8 are sequentially etched according to the mask pattern to expose the silicon germanium epitaxial layer 4 and the width of L1. The branches form grooves (FIG. 5). L1 becomes the gate length seen from the top of the finally completed device.

Subsequently, the open germanium epi layer 4 is selectively removed (FIG. 6). In this case, by performing dry etching and wet etching in parallel, process uniformity and reproducibility can be secured, and deformation of the groove pattern can be minimized. For example, first, 80% of the thickness T1 is removed by dry etching to reduce the damage of the groove pattern, and the remaining 20% is immersed in an aqueous solution of HF: H ₂ O ₂ : CH ₃ COOH = 1: 2: 3 to wet silicon. Germanium can be removed. Wet etching under these conditions has a high etch rate of about 100 nm per minute for silicon germanium, but has a high selectivity of 100: 1 for silicon, resulting in little damage to the silicon epitaxial layer 5 of thickness T2. By using wet etching in the second half, it is also possible to prevent the ion damage problem of the crystal of the silicon epi layer 5 which may occur in dry etching.

Thereafter, an inverted sidewall 10 is formed in the groove as the first sidewall using the insulating film (FIG. 7). The reverse side wall 10 may form an insulating film such as a silicon oxide film or a silicon nitride film by vapor deposition and anisotropic etching. At this time, the width L3 of the reverse side wall becomes an important variable that determines the gate length viewed from the channel. The width L3 of the reverse side wall is determined according to the deposition thickness and the anisotropic etch rate of the insulating film. Thus, the channel length can be easily adjusted by controlling the deposition and etching of the insulating film. Can be reduced.

Next, channel ion implantation may be performed on the upper front surface of FIG. 7 (FIG. 8). This is because a MOSFET having a thin channel (T ₂ ) having a high threshold voltage by itself has no high threshold voltage. Therefore, in a MOSFET device requiring a low threshold voltage, a channel ion injection is not required. In the case of the need to control the amount of energy, an appropriate dose and energy channel ion implantation process may be required. When channel ion implantation is performed, the source / drain connection is more effectively broken in the channel region. This is because the implanted ions are allowed only to the silicon region opened by the reverse side wall, not the source / drain covered with the nitride film.

Subsequently, a high quality gate insulating film 11 is formed through a thermal oxidation process (Fig. 9). At this time, the thickness of the gate insulating film is an important parameter that determines the performance of the device. Therefore, the thickness of the gate insulating film is determined according to the gate length L2 seen in the final channel.

Subsequently, the material 12 to be used as the gate electrode is deposited on the entire upper surface of FIG. 9, and then etched so that the gate material remains only in the groove (FIG. 10). The gate material may be made of metal or polycrystalline silicon, and the etching of the gate material may be performed by an etch-back or chemical mechanical polishing (CMP) process. At this time, the silicon nitride film 9 serves as an etch stop layer of the etch-back or CMP process.

Next, the silicon germanium epitaxial layer 4 is exposed in the region to act as a source / drain by simultaneously or sequentially removing the silicon nitride layer 9 and the silicon oxide layer 8 serving as a buffer (FIG. 11). Here, the silicon nitride film may be removed by wet etching of phosphate, and the silicon oxide film may be removed by dry etching or wet etching.

Subsequently, the gate and the source / drain are simultaneously doped through ion implantation (FIG. 12). This simplifies the device fabrication process, as doping is not required for the source / drain extension region, unlike MOSFETs in planar structures.

After this, the second sidewall 13 may be further formed on both sides of the gate electrode for a back-end-of-line BEOL (FIG. 13). The sidewalls formed here may be used separately or simultaneously with a silicon oxide film or a silicon nitride film as an insulating film.

Next, a subsequent annealing process is performed to heal damage from the ion implantation process and the dry etching process previously performed and to electrically activate the implanted ions (dopant).

Finally, after removing the natural oxide film formed during the process, a silicide process is performed to prepare a subsequent metal process by forming a silicide layer 14 on top of the source / drain and the gate electrode (FIG. 14). An aqueous solution of NH ₄ F: HF = 50: 1 may be used to remove the native oxide film. Other subsequent metal processes follow the back-end-of-line (BEOL) of a typical device line.

The present invention, as in the prior art, by forming the gate shape 'T' shape to reduce the resistance of the gate electrode to facilitate the formation of a very small channel, as well as the following excellent process improvement effect.

First, although there is a limit in reducing a series resistance of a source / drain by using a silicon layer of SOI as a source / drain, in the present invention, a series of source / drain by using a silicon germanium epitaxial layer thickened by epitaxy. The resistance can be greatly reduced. This is because silicon germanium has much better carrier mobility than conventional bulk silicon. Improving the mobility of the carrier, that is, electrons or holes, results in a difference in transconductance, and consequently, improves the current driving capability of the device. The comparison of the characteristics of the linear region transconductance in the case of the silicon substrate and the silicon germanium is shown in FIG. 15.

Second, in forming the region where the gate is to be formed, the silicon germanium is selectively wet-etched using an aqueous solution having a high etching selectivity with silicon, thereby dramatically improving the uniformity of the entire wafer and the reproducibility of the process. It can be increased, and compared with conventional dry etching, there is an advantage that can greatly reduce the crystal defect of the silicon epi layer.

Lastly, the epi layer of SOI is formed into a double layer of thin silicon layer and thick silicon germanium layer, and the thin silicon layer is used as the channel region. When the channel region is made of the germanium layer, the energy gap is shortened due to the reduction of the energy gap. It is possible to prevent the deterioration of the characteristics and to form a thinner channel region than the conventional silicon epilayer, as well as to ensure a predetermined thickness of the silicon region of the channel region for the MOSFET fabricated on the SOI substrate to operate in a fully depleted type. There is an advantage. Accordingly, the silicon epitaxial thickness can be adjusted by an error of several nm or less, thereby enabling the implementation of a MOSFET having a gate length of 10 nm or less.                     

Although the present invention has been described in detail only with respect to specific examples, it will be apparent to those skilled in the art that various changes and modifications can be made within the spirit of the present invention, and such changes and modifications are within the scope of the claims according to the following claims.

Claims (12)

A first step of forming an SOI substrate comprising a silicon layer, a first silicon oxide layer, a second silicon oxide layer, a silicon epi layer, and a silicon germanium epi layer; A silicon oxide buffer layer and a silicon nitride layer are sequentially deposited on the SOI substrate, and a gate is formed by sequentially etching the silicon nitride layer, the silicon oxide buffer layer, and the silicon germanium epitaxial layer to expose the silicon epitaxial layer according to a predetermined pattern. Forming a region to be; A third step of forming a pair of first sidewalls to surround a portion of the silicon nitride film on both sides of an upper portion of the silicon epitaxial layer that is spaced apart from each other inside the region where the gate is to be formed; Forming a gate insulating film on the first sidewall and the exposed silicon layer epitaxial layer; Depositing a gate material on the entire surface, and removing and planarizing the gate material to expose the upper surface of the silicon nitride layer; A sixth step of forming a source / drain and a gate electrode by removing the silicon germanium epitaxial layer to be exposed by etching the silicon nitride layer and the silicon oxide buffer layer; A seventh step of performing an ion implantation process on the front surface; And a silicide process on the entire surface to form a silicide layer on top of the source / drain and gate electrodes. The method of claim 1, Between the third and fourth stages, And adding a channel ion implantation process on the front surface. The method according to claim 1 or 2, Between the seventh and eighth stages, And depositing an insulating film on the entire surface, and etching back the insulating film to form a pair of second sidewalls on the outside of the gate. The method of claim 3, wherein And adding an annealing process immediately before the silicide process of the eighth step. The method of claim 4, wherein Formation of the SOI substrate of the first step, Performing a thermal oxidation process on a handle silicon substrate to form a silicon layer and a first silicon oxide layer; Depositing a silicon buffer layer on a host silicon substrate and then sequentially depositing a silicon germanium epi layer and a silicon epi layer by an epi process; First to third steps of depositing a second silicon oxide layer on the silicon epitaxial layer of the host silicon substrate and implanting hydrogen ions into the entire surface; The two substrates are joined by a thermal annealing process so that the second silicon oxide layer of the host silicon substrate is positioned on the first silicon oxide layer of the handle silicon substrate, and then a portion of the host substrate is further subjected to a thermal annealing process in a nitrogen atmosphere. Separating steps 1-4; And a first to fifth step of removing the portion of the host substrate and the remaining silicon buffer layer on the silicon germanium epitaxial layer by wet etching the bonded substrate. The method of claim 4, wherein Formation of the SOI substrate of the first step, Performing a thermal oxidation process on a handle silicon substrate to form a silicon layer and a first silicon oxide layer; Injecting hydrogen ions into the upper front surface of the host silicon substrate; Depositing a silicon buffer layer on the host substrate implanted with the hydrogen ions, and then sequentially depositing a silicon germanium epi layer and a silicon epi layer by an epi process, and then depositing a second silicon oxide layer on the silicon epi layer. Steps 1-3; The two substrates are joined by a thermal annealing process so that the second silicon oxide layer of the host silicon substrate is positioned on the first silicon oxide layer of the handle silicon substrate, and then a portion of the host substrate is further subjected to a thermal annealing process in a nitrogen atmosphere. Separating steps 1-4; And a first to fifth step of removing the portion of the host substrate and the remaining silicon buffer layer on the silicon germanium epitaxial layer by wet etching the bonded substrate. The method according to claim 5 or 6, And depositing the second silicon oxide layer in the first to third steps using an oxidation process and / or chemical vapor deposition. The method of claim 7, wherein The method of manufacturing a field effect transistor according to claim 1, wherein the oxidation process of steps 1-3 is an oxidation process using ozone. The method according to any one of claims 5, 6 and 8, The composition ratio of the silicon germanium epi layer is Si _x Ge _1-X x is about 0.7, the thickness of the silicon epi layer is 1/4 of the gate length, The thermal process for the combination of the first step 1-4 is performed for about 4 hours at 250 ℃, the thermal process for separation is carried out for 10 minutes at 550 ℃ in a nitrogen atmosphere, The wet etching of the first to fifth steps uses a solution in which 10% KOH is dissolved. The method of claim 9, The silicon germanium epitaxial layer etching of the second step is A first step of removing the part of the silicon germanium epitaxial layer by anisotropic dry etching; The method of claim 2, wherein the remaining portion of the silicon germanium epitaxial layer is removed by wet etching. The method of claim 10, The wet etching of the second step 2-2 is a method of manufacturing a field effect transistor, characterized in that using an aqueous solution of HF: H ₂ O ₂ : CH ₃ COOH = 1: 2: 3. The method of claim 10, The gate material of the fifth step is selected from metal or polycrystalline silicon, and the planarization method is selected from an etch back process or a CMP process.

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