CN1967884A - Manufacturing method for LED flip-chip - Google Patents
Manufacturing method for LED flip-chip Download PDFInfo
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- CN1967884A CN1967884A CNA2005101104757A CN200510110475A CN1967884A CN 1967884 A CN1967884 A CN 1967884A CN A2005101104757 A CNA2005101104757 A CN A2005101104757A CN 200510110475 A CN200510110475 A CN 200510110475A CN 1967884 A CN1967884 A CN 1967884A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000003466 welding Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 230000005496 eutectics Effects 0.000 claims abstract description 12
- 238000002360 preparation method Methods 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 230000001105 regulatory effect Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 241000196324 Embryophyta Species 0.000 description 6
- 241000218202 Coptis Species 0.000 description 5
- 235000002991 Coptis groenlandica Nutrition 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000000605 extraction Methods 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
The invention relates to a method for producing LED face-down chip, wherein it comprises that; preparing large LED chip matched in eutectic welding electrode, and relative silicon substrate; preparing metal conductive layer and lead-out conductive layer, with ultrasonic metal ball welding point; then using eutectic welding face-down machine, to weld large LED chip and silicon substrate. The invention can reduce voltage, to reduce the heat and improve reliability.
Description
Technical field
The present invention relates to a kind of production process of semiconductor device method, particularly relate to the preparation method of a kind of LED flip-chip (Flip-Chip).
Background technology
Semiconductor lighting is one of the high-tech sector of tool development prospect of 21 century, and the popularization along with semiconductor lighting is used will play key effect in research, production and the downstream application Products Development of chip technology.
At present, traditional Sapphire Substrate GaN high-power chip, electrode is positioned on the exiting surface of chip.About 30% light is absorbed by the P electrode, and because the limited conductivity of P-GaN layer, requirement precipitates the metal level of one deck electric current diffusion again at the P-GaN laminar surface.This current-diffusion layer is made up of Ni/Au (nickel/gold), can cover a part of light, thereby reduces the light extraction efficiency of chip.In order to reduce radiative absorption, the thickness of current extending should reduce to the hundreds of nanometer.The minimizing of thickness has limited current-diffusion layer again conversely in all even ability that spreads big electric current reliably of P-GaN laminar surface, and influences the forward voltage of high-power chip.Therefore this P type contact structures have restricted the operating power of led chip.The heat of simultaneously this structure pn knot is derived by Sapphire Substrate and is gone, and thermally conductive pathways is longer.Because sapphire thermal conductivity coefficient is than metal low (35W/mK), therefore, the led chip thermal resistance of this structure can be bigger.In addition, the P electrode of this structure and lead-in wire also can block part light and enter device package, and are coated with last layer epoxy resin usually above the positive assembling structure, and the epoxy resin capacity of heat transmission is very poor, causes the difficult problem of heat radiation, influences the performance parameter and the reliability of device.So this packed LED chip all constitutes considerable influence from device architecture itself to aspects such as device power, light extraction efficiency and hot propertys.In order to overcome these deficiencies of positive cartridge chip, flip-chip has been invented by U.S. Lumileds company.BUMP corresponding on several BUMP (gold goal) that weld on the high-power LED chip electrode and the silicon substrate welds together by eutectic, silicon substrate is by adhesives and device inside is heat sink bonds together, light takes out from Sapphire Substrate, needn't take out from current-diffusion layer.Owing to do not get light from current-diffusion layer, lighttight like this current-diffusion layer can be thickeied, and increases the current density of flip-chip.This structure can also directly be led the heat of pn knot to the high silicon substrate of thermal conductivity coefficient (for 145W/mK) by metal salient point simultaneously, and radiating effect is more excellent; And between pn knot and P electrode, increased a reflector layer, and eliminated being in the light of electrode and lead-in wire simultaneously, therefore this structure has the characteristic of aspect optimums such as electricity, light, heat.
But how to improve the forward voltage of chip in the flip-chip manufacturing process, the indirect chip cooling problem of improving improves the quality of flip-chip, is a several main difficult problem that faces in the device manufacturing process.The voltage height of high-power chip, principal element are the resistance height, and this is by extension itself, electrode design and making, upside-down mounting welding and decision.Under nominal working conditions, the heat that the resistance height can make LED produce is excessive, so cause the junction temperature of device too high, the light extraction efficiency of device descends, reliability reduces.
Summary of the invention
Technical problem to be solved by this invention provides a kind of preparation method of LED flip-chip, and it can make high power LED flip-chip reduce voltage, and the heat that LED is produced reduces, and improves the reliability of flip-chip.
For solving the problems of the technologies described above, the preparation method of LED flip-chip of the present invention adopts following technical scheme, at first, prepares the large scale led chip with suitable eutectic welding electrode; Prepare the silicon substrate of corresponding size simultaneously, and on silicon substrate, produce the golden conductive layer that welds for eutectic and draw conductive layer; Then, utilize the eutectic welding equipment that large scale led chip and silicon substrate are welded together.
Adopt method of the present invention can reduce the voltage of big merit LED flip-chip, optimized heat radiation simultaneously.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is voltage and a P number of electrodes graph of relation before and after the upside-down mounting;
Fig. 2 is voltage and a Wire-Bond ball size relationship curve chart before and after the upside-down mounting;
Fig. 3 is voltage and a ultrasonic power graph of relation before and after the upside-down mounting;
Fig. 4 be before and after the upside-down mounting voltage and weld time graph of relation;
Fig. 5 is voltage and a welding temperature graph of relation before and after the upside-down mounting;
Fig. 6 is a prior art flip chip structure schematic diagram.
Embodiment
The preparation method of LED flip-chip of the present invention comprises the steps, at first prepares large scale (the 1000 μ m * 1000 μ m) led chip (flip LED) with suitable eutectic welding electrode.Prepare the silicon substrate of corresponding size (1200 μ m * 1400 μ m) simultaneously, and on silicon substrate, produce the golden conductive layer (being the N electrode) that welds for eutectic and draw conductive layer (being the P electrode).Adopt kind of a ball machine, at described golden conductive layer and draw conductive layer and produce ultrasonic gold ball bonding point.Then, utilize eutectic welding equipment upside-down mounting machine, large scale led chip and silicon substrate are welded together.Adopt chip testing machine to test after the preparation of LED flip-chip is finished, analyze photoelectric parameter.
Embodiment one, increases the quantity of P electrode.
The described technological parameter that large scale led chip and silicon substrate are welded together is as follows:
Utilization kind of ball machine is selected gold thread 1.0mil for use, plants 150 ℃～200 ℃ of bulb temperatures, makes the size Control of Wire-Bond ball (ultrasonic spun gold ball) at Φ 80 μ m by regulating technological parameter.Die-Bond (upside-down mounting welding) machine ultrasonic power is 0.6W～1.6W, and be 200ms～500ms weld time, and welding temperature is 100 ℃～250 ℃.The quantity of planting ball metal P electrode on the silicon substrate is 4～12.The large scale led chip of choosing the voltage unanimity again welds.
The crystal grain V that under the prerequisite of other parameter constant, records as seen from Figure 1 by the quantity that increases the P electrode
F(forward voltage) value, and mutual difference DELTA V
FWherein, adopt difference DELTA V between 4 P electrodes and 12 the P electrodes
FBe 0.4V.
The quantity that increases the P electrode makes electric current be distributed to the entire chip from a plurality of P electrodes respectively easily, has optimized current path, and the operating current after the increasing is evenly distributed in the current-diffusion layer on P-GaN surface, obtains electric current consistency preferably.
Embodiment two, strengthen the size (Φ 100 μ m～Φ 160 μ m) of Wire-Bond ball.
The described technological parameter that large scale led chip and silicon substrate are welded together is as follows:
Adopt kind of a ball machine, select the gold thread size (1.0mil, 1.2mil, 1.5mil, 2.0mil) of different size for use, (10w～50w), plant the ball time and (20ms～60ms), plant ball pressure and (20g～50g), burn the ball time (600 μ s～900 μ s) with different kind ball power, by regulating the Wire-Bond ball that above-mentioned parameter obtains different size, strengthen the size (Φ 100 μ m～Φ 160 μ m) of Wire-Bond ball.Die-Bond board ultrasonic power is 1.0W, and be 300ms weld time, and welding temperature is 100 ℃.Choose the large scale led chip of voltage unanimity again, the silicon substrate with the Wire-Bond ball with Φ 100 μ m～Φ 160 μ m welds respectively.
The crystal grain V that under the prerequisite of other parameter constant, records as seen from Figure 2 by the size that strengthens the Wire-Bond ball
F(forward voltage) value, and mutual difference DELTA V
FWherein, the difference DELTA V when the diameter of Wire-Bond ball is respectively Φ 100 μ m and Φ 160 μ m
FBe about 0.1V.
The heat of pn knot directly can better be led to the high silicon substrate of thermal conductivity coefficient by metal salient point by the size that strengthens the Wire-Bond ball on the P electrode, radiating effect is more excellent.
Embodiment three, regulate the ultrasonic power of Die-bond machine.
Adopt kind of a ball machine, select gold thread 1.0mil for use, plant 150 ℃～200 ℃ of bulb temperatures, make the size Control of Wire-Bond ball at Φ 80 μ m by regulating technological parameter.Be 200ms～500ms weld time, and welding temperature is 100 ℃～250 ℃, regulates the ultrasonic power of Die-bond board, and scope is 0.6W～1.6W.The large scale led chip of choosing the voltage unanimity welds.
The crystal grain V that under the prerequisite of other parameter constant, records as seen from Figure 3 by the ultrasonic power of regulating the Die-bond machine
F(forward voltage) value, and mutual difference DELTA V
FWherein, the difference DELTA V when ultrasonic power is respectively 0.6W and 1.6W
FValue is about 0.1V.
Embodiment four, regulate the weld time of Die-bond machine.
Adopt kind of a ball machine, select gold thread 1.0mil for use, plant 150 ℃～200 ℃ of bulb temperatures, make the size Control of Wire-Bond ball at Φ 80 μ m by regulating technological parameter.
Die-Bond board ultrasonic power is 0.6W～1.6W, and welding temperature is 100 ℃～250 ℃, regulates the weld time of Die-bond board, and scope is 500ms～100ms.The large scale led chip of choosing the voltage unanimity welds.
The crystal grain V that under the prerequisite of other parameter constant, records as seen from Figure 4 by the weld time of regulating the Die-bond machine
F(forward voltage) value, and mutual difference DELTA V
FWherein, the difference DELTA V when be respectively 100ms and 500ms weld time
FValue is about 0.1V.
Embodiment five, regulate the welding temperature of Die-bond machine.
Adopt kind of a ball machine, select gold thread 1.0mil for use, plant 150 ℃～200 ℃ of bulb temperatures, make the size Control of Wire-Bond ball at Φ 80 μ m by regulating technological parameter.
Die-Bond machine ultrasonic power is 0.6W～1.6W, and regulate the welding temperature of Die-bond machine at 200ms～400ms weld time, and scope is 250 ℃～50 ℃.The large scale led chip of choosing the voltage unanimity welds.
The crystal grain V that under the prerequisite of other parameter constant, records as seen from Figure 5 by the welding temperature of regulating the Die-bond machine
F(forward voltage) value, and mutual difference DELTA V
FWherein, the difference DELTA V when welding temperature is respectively 50 ℃ and 250 ℃
FValue is about 0.1V.
Regulate the Die-bond machine ultrasonic power, to reduce weld time, reduce the welding temperature purpose be the damaged condition that reduces in manufacturing process core intragranular bilge construction, controls the volume resistance of conductor itself well.If do not control volume resistance well, can cause conductor itself to produce a large amount of heats, accelerate the duplet lattice collisions.Can reduce electronics and hole-recombination probability like this, influence the light extraction efficiency and the life-span of core grain.Therefore high-power chip voltage be can reduce by three kinds of technological parameters more than regulating the Die-Bond machine, light extraction efficiency and reliability improved.
Claims (6)
1, a kind of preparation method of LED flip-chip, it is characterized in that: comprise the steps, at first prepare large scale led chip with suitable eutectic welding electrode, prepare the silicon substrate of corresponding size simultaneously, and on silicon substrate, produce for the golden conductive layer of eutectic welding and draw conductive layer, and at described golden conductive layer and draw conductive layer and produce ultrasonic gold ball bonding point; Then, utilize eutectic welding equipment upside-down mounting machine, large scale led chip and silicon substrate are welded together.
2, the preparation method of LED flip-chip as claimed in claim 1 is characterized in that: the described technological parameter that large scale led chip and silicon substrate are welded together is as follows:
Die-Bond machine ultrasonic power is 0.6W～1.6W, and be 200ms～500ms weld time, and welding temperature is 100 ℃～250 ℃, and the Wire-Bond ball is of a size of Φ 80 μ m; The quantity of P electrode is 4～12 on the silicon substrate.
3, the preparation method of LED flip-chip as claimed in claim 1 is characterized in that: the described technological parameter that large scale led chip and silicon substrate are welded together is as follows:
Die-Bond board ultrasonic power is 1.0W, and be 300ms weld time, and welding temperature is 100 ℃, and the Wire-Bond ball is of a size of Φ 100 μ m～Φ 160 μ m.
4, the preparation method of LED flip-chip as claimed in claim 1, it is characterized in that: regulate the ultrasonic power of Die-bond machine, scope is 0.6W～1.6W, and be 200ms～500ms weld time, welding temperature is 100 ℃～250 ℃, and the Wire-Bond ball is of a size of Φ 80 μ m.
5, the preparation method of LED flip-chip as claimed in claim 1, it is characterized in that: Die-Bond machine ultrasonic power is 0.6W～1.6W, welding temperature is 100 ℃～250 ℃, the Wire-Bond ball is of a size of Φ 80 μ m, regulate the weld time of Die-bond machine, scope is 500ms～100ms.
6, the preparation method of LED flip-chip as claimed in claim 1, it is characterized in that: Die-Bond machine ultrasonic power is 0.6W～1.6W, be 200ms～400ms weld time, the Wire-Bond ball is of a size of Φ 80 μ m, regulate the welding temperature of Die-bond machine, scope is 250 ℃～50 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101104757A CN100468796C (en) | 2005-11-17 | 2005-11-17 | Manufacturing method for LED flip-chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101104757A CN100468796C (en) | 2005-11-17 | 2005-11-17 | Manufacturing method for LED flip-chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1967884A true CN1967884A (en) | 2007-05-23 |
| CN100468796C CN100468796C (en) | 2009-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101104757A Expired - Fee Related CN100468796C (en) | 2005-11-17 | 2005-11-17 | Manufacturing method for LED flip-chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265865A (en) * | 2019-05-23 | 2019-09-20 | 深圳新飞通光电子技术有限公司 | A kind of assemble method of the biradical seat of chip of laser |
| CN111653660A (en) * | 2019-03-04 | 2020-09-11 | 昆山工研院新型平板显示技术中心有限公司 | Micro light-emitting diode display panel and manufacturing method thereof |
-
2005
- 2005-11-17 CN CNB2005101104757A patent/CN100468796C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653660A (en) * | 2019-03-04 | 2020-09-11 | 昆山工研院新型平板显示技术中心有限公司 | Micro light-emitting diode display panel and manufacturing method thereof |
| CN110265865A (en) * | 2019-05-23 | 2019-09-20 | 深圳新飞通光电子技术有限公司 | A kind of assemble method of the biradical seat of chip of laser |
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| Publication number | Publication date |
|---|---|
| CN100468796C (en) | 2009-03-11 |
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