CN1964184A - An amplifier for analog-digital converter - Google Patents
An amplifier for analog-digital converter Download PDFInfo
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- CN1964184A CN1964184A CN 200510110154 CN200510110154A CN1964184A CN 1964184 A CN1964184 A CN 1964184A CN 200510110154 CN200510110154 CN 200510110154 CN 200510110154 A CN200510110154 A CN 200510110154A CN 1964184 A CN1964184 A CN 1964184A
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- nmos pass
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Abstract
The related amplifier for ADC comprises: a first differential input part, a cascade current mirror between the output of last part and a first reference potential, a first amplification part for cascade current source between the first input part and a second reference potential, a second differential input part connected with the first input part, and a second amplification part of a second current magnetic mirror.
Description
[technical field]
The invention relates to analog to digital converter with amplifier.Say so in more detail about obtaining at the analog to digital converter of a large amount of production figures television receptions employed low-voltage, high input range and high-gain during with amplifier with VSB/QAM.
[background technology]
Recently, there is fast development trend in Digital Television market, has increased the multiple function of Digital Television, is because used the above chip of about millions of doors.If also increase the function of the VSB mode of using aerial wave number word television reception mode, die size can be geometric ways and increase.
So, in order to reduce the size of chip, so use (0.35um=〉0.18) owing to can reduce present flow process.But, the minimizing of this flow process, the effect that reduces the digital circuit size is very obvious, very unfavorable to analog circuit simultaneously.When reducing flow process, reduce the rated power supply utmost point, very difficult to the operation meeting of analog circuit.In this limited reason is that to have adopted designing technique be the design of analog digital interpreter of the aerial ripple receiving chip of Digital Television of the 1.8V2Vpp input mobility scale of 0.18um.
It to be as shown in Figure 1 analog to digital converter that past is normally used, and at this, the employed part of amplifier is that sampling keeps (sample and hold) amplifier and multiple digital analog converter partly.
The structure of this common analog to digital converter as shown in Figure 2.
But this mode in the input range of the 0.18um 1.8V power supply utmost point, when using 2Vpp, with the above resolution of 10 bits, can not obtain the above signal to noise ratio of 60db.
That is, in 4 sections transistors that amplifier constitutes, use under the situation of 1.8V the big slightly power supply utmost point of 1.8/4=0.45V of the Vds in each transistor.But this power supply utmost point output change can not obtain reducing in each transistorized zone of saturation under the situation of 2Vpp.Therefore, under the situation of design 10 bit moduli transducers,, can produce the signal band signal to noise ratio of 8 bits when stating as a result in the use though can surpass the above signal band signal to noise ratio of 12 bits.So, in the Digital Television receiving chip of the striograph that must keep high image quality, can not use.
High-efficiency amplifier when the analog to digital converter of design low-voltage high image resolution, must use in sampling amplifier and multiple analog to digital converter.If it is the above-mentioned supply power utmost point is very low, inapplicable to existing equipment structure.
[summary of the invention]
Therefore, purpose of the present invention addresses the above problem exactly, provides a kind of at design necessary amplifier with low-voltage, broad change input range and high-gain during analog to digital converter.
To achieve these goals, according to analog to digital converter amplifier of the present invention, it is characterized in that it comprises following part:
By the first differential input unit, in first enlarging section that the cascode current mirror that is electrically connected between the output of the first differential input unit and first reference potential, the cascode current source that is electrically connected between the output of the above-mentioned first differential input unit and second reference potential are constituted; By second enlarging section that the output of above-mentioned first enlarging section is constituted as the second differential input part of input, second current mirror that is electrically connected with the above-mentioned second differential input part.
The invention is characterized in that it comprises the bias circuit that activates above-mentioned cascode current mirror and above-mentioned first, second differential input part successively.
In the middle of the present invention, the above-mentioned first differential input part preferably includes: first, second transistor that is provided with the gateway that is electrically connected with differential input; The 3rd transistor that is electrically connected with above-mentioned first, second transistorized source electrode.And the above-mentioned the 3rd transistorized source electrode preferably links to each other with above-mentioned bias circuit with above-mentioned first reference potential with gateway.
In the present invention, above-mentioned first enlarging section and above-mentioned second enlarging section preferably also comprise common feedback circuit.
In the present invention, the second differential input part preferably includes: the 8th and the 9th transistor that the gateway that is electrically connected with the output of above-mentioned first enlarging section is set; And the tenth transistor that is electrically connected with the above-mentioned the 8th and the 9th transistorized source electrode.
In the present invention, the output of first enlarging section preferably also comprises resistance and the capacitor that uses serial arrangement to be connected with above-mentioned the 8th, the 9th transistor drain.
In the present invention, preferably include the 5th and the 6th transistor that source electrode links to each other with first reference potential and drains and link to each other with each efferent in second current mirror.
As mentioned above, utilize the present invention can solve the problem that sampling the most difficult when design simulation-digital block keeps amplifier and reduces multiple digital-to-analog interpreter supply power.
[description of drawings]
Fig. 1 is the schematic diagram that the part of using amplifier in the existing analog to digital converter is shown.
Fig. 2 is the circuit diagram of existing amplifier.
Fig. 3 is to be the circuit diagram of first enlarging section of foundation with one embodiment of the present of invention.
Fig. 4 is to be the circuit diagram of second enlarging section of foundation with one embodiment of the present of invention.
[embodiment]
Below with reference to accompanying drawings the present invention is described in more details.
Fig. 3 is to be the circuit diagram of first enlarging section in the amplifier in the analog to digital converter of foundation with one embodiment of the present of invention.
In the above-described embodiments, first enlarging section of amplifier comprises the first differential input part 301 and cascode current mirror 302, cascode current source 303 and bias circuit (not shown).
The foregoing description can obtain high-gain at input signal.
As shown in Figure 3, N-channel input part and P-channel input part are presented as with a circuit in first enlarging section.
Also comprise first nmos pass transistor to the, three nmos pass transistor (N1-in the above-mentioned first differential input part 301
-N3).The gateway of the gateway of the above-mentioned first nmos pass transistor N1 and the above-mentioned second nmos pass transistor N2 is transfused to voltage.The source electrode of the source electrode of the above-mentioned first nmos pass transistor N1 and above-mentioned NMOS2 transistor N2 links to each other with the drain electrode of above-mentioned the 3rd nmos pass transistor N3 jointly.The drain electrode of the above-mentioned first nmos pass transistor N1 links to each other with the ONP node, and the drain electrode of the above-mentioned second nmos pass transistor N2 links to each other with the OPP node.Be transfused to bias voltage on the gateway of above-mentioned the 3rd nmos pass transistor N3, and its drain electrode links to each other with above-mentioned cascode current source 303.Said structure has constituted the N-channel input of the first differential input part 301.
In addition, after the drain electrode of above-mentioned first nmos pass transistor N1 and the above-mentioned second nmos pass transistor N2 and the drain electrode of the 3rd nmos pass transistor N3 linked to each other jointly, above-mentioned cascode current source 303 linked to each other with the second reference potential VSS.Said structure has constituted the P-channel input of the first differential input part 301.
Comprise first to fourth transistor (P1-at above-mentioned cascode current mirror 302
-P4).
Be transfused to bias voltage in the gateway of an above-mentioned PMOS transistor P1 and above-mentioned the 2nd PMOS transistor P2.Be connected the first reference potential VDD on the gateway of an above-mentioned PMOS transistor P1 and above-mentioned the 2nd PMOS transistor P2.The drain electrode of an above-mentioned PMOS transistor P1 links to each other with the ONP node with above-mentioned the 3rd PMOS transistor drain, and the drain electrode of above-mentioned the 2nd PMOS transistor P2 links to each other with the OPP node with the transistorized source electrode of above-mentioned the 4th PMOS.Be transfused to bias voltage on above-mentioned the 3rd PMOS transistor P3 and the 4th PMOS transistor P4, above-mentioned the 3rd PMOS transistor P3 links to each other with the ON node.Above-mentioned the 4th PMOS transistor drain links to each other with the OP node.
Above-mentioned cascode current source 303 and the 4th is to 7NMOS transistor P4
-P7 links to each other.
In the gateway of above-mentioned the 4th nmos pass transistor P4 and the 5th nmos pass transistor P5, be transfused to bias voltage bp1 and bp2.The gateway of above-mentioned the 4th nmos pass transistor P4 links to each other with the ON node, and the drain electrode of above-mentioned the 5th nmos pass transistor P5 links to each other with the OP node.The source electrode of above-mentioned the 4th nmos pass transistor P4 links to each other with the drain electrode of above-mentioned the 6th nmos pass transistor P6, and the source electrode of above-mentioned the 5th nmos pass transistor P5 links to each other with the drain electrode of above-mentioned 7NMOS transistor P7.The drain electrode of above-mentioned the 6th nmos pass transistor P6 links to each other with the drain electrode of above-mentioned the 3rd nmos pass transistor P3 jointly with the drain electrode of 7NMOS transistor P7.
In addition, the drain electrode of the drain electrode of the transistorized P1 of above-mentioned PMOS1 and the transistorized P2 of above-mentioned the 2nd PMOS links to each other with above-mentioned first reference potential.The source electrode of above-mentioned PMOS3 transistor P3 and above-mentioned PMOS the 4th transistor P4 links to each other with drain electrode.The above-mentioned the 4th to 7NMOS transistor P4
-The drain electrode of P7 links to each other with the above-mentioned second reference potential VSS.
Be connected the first common mode feedback circuit CMF1 on the gateway of the gateway of above-mentioned the 6th nmos pass transistor P6 and above-mentioned 7NMOS transistor P7.
Fig. 4 is to be the second enlarging section schematic diagram in the amplifier in the analog to digital converter of foundation with one embodiment of the present of invention.
In the above-described embodiments, second enlarging section comprises the second differential input part 401 and second current mirror 402.
The foregoing description has carried out the demonstration of summary to utilized signal after high-gain is amplified and the circuit that utilizes required gain and swing to regulate by first enlarging section.
Shown in Fig. 3 b, the above-mentioned second differential input part comprises the 8th to the tenth nmos pass transistor N8
-N10.The gateway of above-mentioned the 8th nmos pass transistor N8 links to each other with above-mentioned ON node.The gateway of above-mentioned the 9th nmos pass transistor N9 links to each other with above-mentioned OP node.The source electrode of above-mentioned the 8th nmos pass transistor N8 links to each other with the drain electrode of above-mentioned the tenth nmos pass transistor N10 jointly with the source electrode of above-mentioned the 9th nmos pass transistor N9.The source electrode of above-mentioned the tenth nmos pass transistor N10 links to each other with the above-mentioned second reference potential VSS.The drain electrode of above-mentioned NMOS8 transistor N8 and NMOS9 transistor N9 links to each other with N-channel lead-out terminal with P-channel lead-out terminal.
In addition, above-mentioned the 8th to the tenth nmos pass transistor N8
-Connecting the above-mentioned first reference potential VDD in the drain electrode of N10 jointly.
Above-mentioned second current mirror 402 comprises the 5th PMOS transistor P5 and the 6th PMOS transistor P6.
The gateway of above-mentioned the 5th PMOS transistor P5 and the transistorized gateway of above-mentioned the 6th PMOS are transfused to bias voltage bp1 jointly.The drain electrode of above-mentioned the 5th PMOS transistor P5 and the 6th PMOS transistor P6 links to each other with the above-mentioned first reference potential VDD.The source electrode of above-mentioned the 5th PMOS transistor P5 and the 6th PMOS transistor P6 links to each other with each lead-out terminal.
In addition, the drain electrode of above-mentioned the 5th PMOS transistor P5 and the 6th PMOS transistor P6 links to each other with the above-mentioned first reference potential VDD.
Resistance and capacitor are being connected in series between the gateway of above-mentioned the 8th nmos pass transistor N8 and the 9th nmos pass transistor and the drain electrode.
Rely on said structure in first enlarging section, to obtain gain, and obtain gain littler and output hunting range than first enlarging section in second enlarging section.
If think further to understand the running of above-mentioned amplifier, reach 90dB, the maximum 800MHz of bandwidth approximately by the DC current gain of 2 sections amplifiers that constituted.That is, can obtain the effect of low-voltage, cataclysm scope, high-gain.So, under the situation of using 1.8V to operate, in first enlarging section, carry out DC current gain, and can access little DC current gain and big hunting range in second enlarging section.When the power supply of use 1.8V is supplied with in first enlarging section, each 4 sections transistorized drain-source voltage Vds (drain source voltage) respectively have the voltage of 0.45V, and this voltage makes transistor be in the zone of saturation when amplifier is operated usually.In existing amplifier, transistor can form saturation condition under dc state, but the swing of signal is under the situation of 2Vpp, can not form the zone of saturation.As long as import 2Vpp, just can make output node ON, OP have the hunting range of 2Vpp/1000 on first enlarging section that provides in the present invention.
This is because it links to each other with second enlarging section and has formed feedback, so the swing of first enlarging section can occupy 60dB in 90dB.Therefore, the swing of ON, OP node does not almost reach above-mentioned 2Vpp/1000 degree.So, use 1.8V to operate and do not have obstacle fully.
As shown in Figure 4, second enlarging section has the DC current gain of 30dB, and when input 1.8V power supply, the output swing of 2Vpp just can optionally be operated.Even under the situation of 2Vpp, also there is the Vds that can put 1Vpp more than needed between the 8th nmos pass transistor of the 5th PMOS transistor of each output node outp, outn top, the 6th PMOS transistor and bottom, the 9th nmos pass transistor.That is, output node OUPP is since 0.9 voltage, and the scope that can change is that a side of top PMOS transistor one side 1.4V, following nmos pass transistor is 0.4V, and each PMOS transistor and NMOS crystal all have the zone of saturation in this case.
By above-mentioned description, the related work personnel can carry out various change and modification fully in the scope that does not depart from this invention technological thought.
Therefore, the technical scope of this invention is not limited to the content on the specification, must determine its technical scope according to interest field.
Claims (7)
1, a kind of analog to digital converter amplifier is characterized in that, comprises following two parts:
First enlarging section comprises the first differential input part, at the cascode current mirror that is electrically connected between the output of the above-mentioned first differential input part and first reference potential, the cascode current source that is electrically connected between the output of the above-mentioned first differential input part and second reference potential;
Second enlarging section comprises that output with above-mentioned first amplifier is as second differential input part of input and second current mirror that is electrically connected with the above-mentioned second differential input part.
2, analog to digital converter amplifier according to claim 1, it is characterized in that: described device also comprises:
Activate the bias circuit of described cascode current source, described cascode current mirror and first, second differential input part successively.
3, analog to digital converter amplifier according to claim 2 is characterized in that:
Comprise first, second nmos pass transistor that is provided with the gateway that is electrically connected with differential input part and the 3rd nmos pass transistor that is electrically connected with the source electrode of described first, second nmos pass transistor in the described first differential input part, and the source electrode of above-mentioned the 3rd nmos pass transistor links to each other with above-mentioned bias circuit with above-mentioned first reference potential with gateway.
4, analog to digital converter amplifier according to claim 2 is characterized in that:
Described first enlarging section and described second enlarging section are also with the common mode feedback circuit.
5, analog to digital converter amplifier according to claim 1 is characterized in that:
The second differential input part also comprises the 8th, the 9th nmos pass transistor that is provided with the gateway that is electrically connected with the output of above-mentioned first enlarging section and the tenth nmos pass transistor that is electrically connected with the source electrode of above-mentioned the 8th, the 9th nmos pass transistor.
6, analog to digital converter amplifier according to claim 5 is characterized in that:
The drain electrode of the output of described first enlarging section and above-mentioned the 8th, the 9th nmos pass transistor (drain) also comprises resistance and the capacitor to be connected in series.
7, analog to digital converter amplifier according to claim 1 is characterized in that:
Second current mirror also comprises the 5th and the 6th PMOS transistor that source electrode links to each other with first reference potential and drains and link to each other with each output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101101547A CN100481720C (en) | 2005-11-09 | 2005-11-09 | An amplifier for analog-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101101547A CN100481720C (en) | 2005-11-09 | 2005-11-09 | An amplifier for analog-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1964184A true CN1964184A (en) | 2007-05-16 |
| CN100481720C CN100481720C (en) | 2009-04-22 |
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ID=38083122
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101101547A Expired - Fee Related CN100481720C (en) | 2005-11-09 | 2005-11-09 | An amplifier for analog-digital converter |
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| Country | Link |
|---|---|
| CN (1) | CN100481720C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800550A (en) * | 2010-03-10 | 2010-08-11 | 浙江大学 | Input buffer circuit for high-speed pipeline analog-to-digital converter |
| CN102545791A (en) * | 2010-12-15 | 2012-07-04 | 联发科技股份有限公司 | Push-pull low noise amplifier and amplifier |
| CN102629856A (en) * | 2012-04-24 | 2012-08-08 | 成都启臣微电子有限公司 | Low-voltage differential signal receiver |
-
2005
- 2005-11-09 CN CNB2005101101547A patent/CN100481720C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800550A (en) * | 2010-03-10 | 2010-08-11 | 浙江大学 | Input buffer circuit for high-speed pipeline analog-to-digital converter |
| CN101800550B (en) * | 2010-03-10 | 2012-10-03 | 浙江大学 | Input buffer circuit for high-speed pipeline analog-to-digital converter |
| CN102545791A (en) * | 2010-12-15 | 2012-07-04 | 联发科技股份有限公司 | Push-pull low noise amplifier and amplifier |
| CN102545791B (en) * | 2010-12-15 | 2014-12-03 | 联发科技股份有限公司 | Push-pull low noise amplifier and amplifier |
| CN102629856A (en) * | 2012-04-24 | 2012-08-08 | 成都启臣微电子有限公司 | Low-voltage differential signal receiver |
| CN102629856B (en) * | 2012-04-24 | 2015-04-22 | 成都启臣微电子有限公司 | Low-voltage differential signal receiver |
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| Publication number | Publication date |
|---|---|
| CN100481720C (en) | 2009-04-22 |
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Granted publication date: 20090422 Termination date: 20091209 |