CN101557216B - Comparator and D-class audio power amplifier comprising comparator - Google Patents
Comparator and D-class audio power amplifier comprising comparator Download PDFInfo
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- CN101557216B CN101557216B CN2009101266247A CN200910126624A CN101557216B CN 101557216 B CN101557216 B CN 101557216B CN 2009101266247 A CN2009101266247 A CN 2009101266247A CN 200910126624 A CN200910126624 A CN 200910126624A CN 101557216 B CN101557216 B CN 101557216B
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Abstract
The invention discloses a comparator and a D-class audio power amplifier comprising the comparator; the comparator comprises an input circuit used for receiving a differential signal and generating anamplified output signal, a delay adjusting circuit used for setting a delay window and adjusting the output signal of the input circuit, and an output circuit used for receiving the output signal of the input circuit and generating an output signal with wide amplitude. The comparator and the D-class audio power amplifier provide the comparator which can work normally in a wide voltage range from a power voltage to a ground voltage; with the adjustment of the delay adjusting circuit, the delay window can be set precisely, thereby suppressing noise well; and the output circuit can response quickly and is characterized by large output swing amplitude.
Description
Technical field
The present invention relates generally to field of analog integrated circuit, and particularly a kind of wide common mode is imported the hysteresis voltage comparator and comprised the D genus audio power amplifier of this comparator.
Background technology
Traditional category-A, category-B or AB class audio amplifier directly amplify analog signal, and amplifier must operate at the linear amplification district.Though the AB class audio amplifier has higher fidelity, power dissipation is very big, and conversion efficiency has not met the needs of green energy conservation less than 50%.The D class A amplifier A then has huge advantage by comparison, it is operated in the characteristic of on off state, make its theoretical efficiency can reach 100%, in the actual conditions also more than 80%, thereby reduced power dissipation greatly, also reduced simultaneously chip and the shared area of PCB (Printed Circuit Board, printed circuit board (PCB)), under the main trend that volume is little, low in energy consumption, efficient is high that current electron trade is pursued, had broad application prospects.
In the D genus audio power amplifier, by audio signal and high frequency fixed frequency signal are compared, digital audio and video signals has been converted into PWM (Pulse Width Modulation as a result, pulse-width modulation) signal, the pwm signal that forms is the fixed carrier frequency (usually at hundreds of kHz) of variable impulse width, by power MOSFET pwm signal is amplified then, the pwm signal after the amplification removes carrier frequency by the LC low pass filter again, recovers the original base band audio signal and removes to drive loud speaker.
Adopting the core cell circuit of the D genus audio power amplifier of PWM pattern is the PWM comparator, because the performance of PWM comparator directly has influence on the output performance of D genus audio power amplifier.So the PWM comparator of a suitable D genus audio power amplifier is considerable, yet the PWM comparator as the D genus audio power amplifier has its particular performances requirement, mainly show: common-mode input range is wide, gain is high, response is fast, output voltage swing is big, and the ability of high inhibition noise will be arranged.
In the existing all kinds of comparator, the single difference input pattern of most employings does not have big common-mode input range.
Fig. 2 is the structural circuit figure of existing a kind of comparator.This comparator comprises: differential MOS transistor MN211, the MN22 of a pair of N raceway groove connect into a pair of P channel type MOS transistor MP23, MP24 and the current source I25 of current mirror.In this structure, use the differential MOS transistor MN21 of a pair of N raceway groove, MN22 is as input, the grid of MN21 is equivalent to positive input terminal 205, the grid of MN22 is equivalent to negative input end 206, the connected node of MP24 and MN22 is equivalent to positive output terminal 207, and the connected node of MP23 and MN21 is equivalent to negative output terminal 208, and its common mode electrical level is V
SS+ V
DS+ V
GS＜V
CM＜V
DD
Fig. 3 is the structural circuit figure of existing another kind of comparator.This comparator comprises: differential MOS transistor MP33, the MP34 of a pair of P raceway groove, a pair of N channel type MOS transistor MN31, MN32 and the constant current source 135 of the current mirror of connection.In this structure, use the differential MOS transistor MP33 of a pair of P raceway groove, MP34 is as input, the grid of MP33 is equivalent to positive input terminal 309, the grid of MP34 is equivalent to negative input end 311, the connected node of MP34 and MN32 is equivalent to positive output terminal 312, and the connected node of MP33 and MN31 is equivalent to negative output terminal 310.Its common mode electrical level is V
SS＜V
CM＜V
DD-| V
DS|-| V
GS|.
During above-mentioned comparator operate as normal, the common mode input is limited in V
SS+ V
DS+ V
GS＜V
CM＜V
DDOr V
SS＜V
CM＜V
DD-| V
DS|-| V
GS|, can not satisfy the requirement of the wide common mode input of PWM comparator.Output voltage swing and noise also are to limit its main cause as the PWM comparator simultaneously, thereby above-mentioned comparator can not satisfy the requirement of PWM comparator in the D genus audio power amplifier.
Summary of the invention
The present invention proposes a kind of comparator and comprises the D genus audio power amplifier of this comparator, can not only work under wide common mode electrical level, and have high-gain, inhibition noise ability characteristics strong, low in energy consumption.
The technical scheme of the embodiment of the invention is achieved in that
A kind of comparator comprises:
Input circuit, be used to receive differential signal, produce and amplify output signal, wherein, described input circuit comprises first nmos pass transistor, second nmos pass transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the grid of described first nmos pass transistor is connected first input end as described input circuit with the transistorized grid of described the 4th PMOS, the grid of described second nmos pass transistor is connected second input terminal as described input circuit with the transistorized grid of described the 3rd PMOS, described input circuit receives described differential signal by described first input end and described second input terminal;
Sluggish regulating circuit is used to be provided with retarding window, regulates the output signal of described input circuit;
Output circuit is used to receive the output signal of described input circuit, produces output signal;
Wherein, described sluggish regulating circuit comprises the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the tenth PMOS transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Connect described second lead-out terminal behind transistorized grid of described the 5th PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 6th PMOS, described the 7th PMOS transistor drain, the transistorized grid of described the 8th PMOS, described the 11 nmos pass transistor is connected to described the 5th PMOS transistor drain;
Connect described first lead-out terminal behind transistorized grid of described the tenth PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 9th PMOS, described the 8th PMOS transistor drain, the transistorized grid of described the 7th PMOS, described the 16 nmos pass transistor is connected to described the tenth PMOS transistor drain;
Connect described the 3rd lead-out terminal behind the grid of described the tenth bi-NMOS transistor and the drain electrode short circuit, the grid of the grid of described the 11 nmos pass transistor, the drain electrode of described the 13 nmos pass transistor, described the 14 nmos pass transistor is connected to the drain electrode of described the tenth bi-NMOS transistor;
Connect described the 4th lead-out terminal behind the grid of described the 15 nmos pass transistor and the drain electrode short circuit, the grid of the grid of described the 16 nmos pass transistor, the drain electrode of described the 14 nmos pass transistor, described the 13 nmos pass transistor is connected to the drain electrode of described the 15 nmos pass transistor;
The source electrode of the source electrode of the source electrode of described the 11 nmos pass transistor, described the tenth bi-NMOS transistor, the source electrode of described the 13 nmos pass transistor, the source electrode of described the 14 nmos pass transistor, the source electrode of described the 15 nmos pass transistor, described the 16 nmos pass transistor connects earthed voltage respectively;
The transistorized source electrode of described the 5th PMOS, the transistorized source electrode of described the 6th PMOS, the transistorized source electrode of described the 7th PMOS, the transistorized source electrode of described the 8th PMOS, the transistorized source electrode of described the 9th PMOS, the transistorized source electrode of described the tenth PMOS connect supply voltage VDD respectively.。
Preferably, described input circuit is configured to complementary differential pair form, its common-mode input voltage range from supply voltage VDD to earthed voltage.
Preferably, described input circuit also comprises first current source and second current source, the partner differential transistor of second conduction type of the partner differential transistor of first conduction type of described first nmos pass transistor and described second nmos pass transistor, described the 3rd PMOS transistor and described the 4th PMOS transistor;
The source electrode of the source electrode of described first nmos pass transistor and described second nmos pass transistor is connected with the positive pole of described second current source, the transistorized source electrode of described the 3rd PMOS is connected with the negative pole of described first current source with the transistorized source electrode of described the 4th PMOS, the negative pole of described second current source connects earthed voltage, and the positive pole of described first current source meets supply voltage VDD;
The drain electrode of described first nmos pass transistor is as first lead-out terminal, the drain electrode of described second nmos pass transistor is as second lead-out terminal, described the 4th PMOS transistor drain is as the 3rd lead-out terminal, and described the 3rd PMOS transistor drain is as the 4th lead-out terminal.
Preferably, described the 7th PMOS transistor is identical with the transistorized breadth length ratio of described the 8th PMOS, described the 5th PMOS transistor is identical with the transistorized breadth length ratio of described the 9th PMOS, described the tenth bi-NMOS transistor is identical with the breadth length ratio of described the 15 nmos pass transistor, described the 13 nmos pass transistor is identical with the breadth length ratio of described the 14 nmos pass transistor, by the retarding window that is symmetrically formed symmetry of described transistor size.
Preferably, described output circuit comprises the 17 nmos pass transistor, the 18 nmos pass transistor, the 19 PMOS transistor and the 20 PMOS transistor;
Transistorized grid of described the 19 PMOS and drain electrode short circuit, the drain electrode of described the 17 nmos pass transistor connects described the 19 PMOS transistor drain, the transistorized grid of described the 20 PMOS connects the transistorized grid of described the 19 PMOS, described the 20 PMOS transistor drain connects the lead-out terminal of the drain electrode of described the 18 nmos pass transistor as described output circuit, be used to produce output signal, the transistorized source electrode of described the 19 PMOS connects power supply, the transistorized source electrode of described the 20 PMOS connects power supply, the source ground of described the 17 nmos pass transistor, the source ground of described the 18 nmos pass transistor, the grid of described the 17 nmos pass transistor connects described the 3rd lead-out terminal, and the grid of described the 18 nmos pass transistor connects described the 4th lead-out terminal.
A kind of D genus audio power amplifier comprises comparator, and described comparator comprises:
Input circuit, be used to receive differential signal, produce and amplify output signal, wherein, described input circuit comprises first nmos pass transistor, second nmos pass transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the grid of described first nmos pass transistor is connected first input end as described input circuit with the transistorized grid of described the 4th PMOS, the grid of described second nmos pass transistor is connected second input terminal as described input circuit with the transistorized grid of described the 3rd PMOS, described input circuit receives described differential signal by described first input end and described second input terminal;
Sluggish regulating circuit is used to be provided with retarding window, regulates the output signal of described input circuit;
Output circuit is used to receive the output signal of described input circuit, produces output signal;
Wherein, described sluggish regulating circuit comprises the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the tenth PMOS transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Connect described second lead-out terminal behind transistorized grid of described the 5th PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 6th PMOS, described the 7th PMOS transistor drain, the transistorized grid of described the 8th PMOS, described the 11 nmos pass transistor is connected to described the 5th PMOS transistor drain;
Connect described first lead-out terminal behind transistorized grid of described the tenth PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 9th PMOS, described the 8th PMOS transistor drain, the transistorized grid of described the 7th PMOS, described the 16 nmos pass transistor is connected to described the tenth PMOS transistor drain;
Connect described the 3rd lead-out terminal behind the grid of described the tenth bi-NMOS transistor and the drain electrode short circuit, the grid of the grid of described the 11 nmos pass transistor, the drain electrode of described the 13 nmos pass transistor, described the 14 nmos pass transistor is connected to the drain electrode of described the tenth bi-NMOS transistor;
Connect described the 4th lead-out terminal behind the grid of described the 15 nmos pass transistor and the drain electrode short circuit, the grid of the grid of described the 16 nmos pass transistor, the drain electrode of described the 14 nmos pass transistor, described the 13 nmos pass transistor is connected to the drain electrode of described the 15 nmos pass transistor;
The source electrode of the source electrode of the source electrode of described the 11 nmos pass transistor, described the tenth bi-NMOS transistor, the source electrode of described the 13 nmos pass transistor, the source electrode of described the 14 nmos pass transistor, the source electrode of described the 15 nmos pass transistor, described the 16 nmos pass transistor connects earthed voltage respectively;
The transistorized source electrode of described the 5th PMOS, the transistorized source electrode of described the 6th PMOS, the transistorized source electrode of described the 7th PMOS, the transistorized source electrode of described the 8th PMOS, the transistorized source electrode of described the 9th PMOS, the transistorized source electrode of described the tenth PMOS connect supply voltage VDD respectively.
Preferably, described input circuit is configured to complementary differential pair form, its common-mode input voltage range from supply voltage VDD to earthed voltage.
Preferably, described input circuit also comprises first current source and second current source, the partner differential transistor of second conduction type of the partner differential transistor of first conduction type of described first nmos pass transistor and described second nmos pass transistor, described the 3rd PMOS transistor and described the 4th PMOS transistor;
The source electrode of the source electrode of described first nmos pass transistor and described second nmos pass transistor is connected with the positive pole of described second current source, the transistorized source electrode of described the 3rd PMOS is connected with the negative pole of described first current source with the transistorized source electrode of described the 4th PMOS, the negative pole of described second current source connects earthed voltage, and the positive pole of described first current source meets supply voltage VDD;
The drain electrode of described first nmos pass transistor is as first lead-out terminal, the drain electrode of described second nmos pass transistor is as second lead-out terminal, described the 4th PMOS transistor drain is as the 3rd lead-out terminal, and described the 3rd PMOS transistor drain is as the 4th lead-out terminal.
Preferably, described the 7th PMOS transistor is identical with the transistorized breadth length ratio of described the 8th PMOS, described the 5th PMOS transistor is identical with the transistorized breadth length ratio of described the 9th PMOS, described the tenth bi-NMOS transistor is identical with the breadth length ratio of described the 15 nmos pass transistor, described the 13 nmos pass transistor is identical with the breadth length ratio of described the 14 nmos pass transistor, by the retarding window that is symmetrically formed symmetry of described transistor size.
Preferably, described output circuit comprises the 17 nmos pass transistor, the 18 nmos pass transistor, the 19 PMOS transistor and the 20 PMOS transistor;
Transistorized grid of described the 19 PMOS and drain electrode short circuit, the drain electrode of described the 17 nmos pass transistor connects described the 19 PMOS transistor drain, the transistorized grid of described the 20 PMOS connects the transistorized grid of described the 19 PMOS, described the 20 PMOS transistor drain connects the lead-out terminal of the drain electrode of described the 18 nmos pass transistor as described output circuit, be used to produce output signal, the transistorized source electrode of described the 19 PMOS connects power supply, the transistorized source electrode of described the 20 PMOS connects power supply, the source ground of described the 17 nmos pass transistor, the source ground of described the 18 nmos pass transistor, the grid of described the 17 nmos pass transistor connects described the 3rd lead-out terminal, and the grid of described the 18 nmos pass transistor connects described the 4th lead-out terminal.
The invention provides a kind of input voltage range and be supply voltage to earthed voltage on a large scale in the comparator of operate as normal, adjusting by sluggish regulating circuit, retarding window can be set accurately, thereby good restraining noise, output circuit not only responds soon, and has the big characteristics of output voltage swing.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the composition structure chart of a kind of comparator first embodiment of the present invention;
Fig. 2 is the structural circuit figure of existing a kind of comparator;
Fig. 3 is the structural circuit figure of existing another kind of comparator;
Fig. 4 is the physical circuit figure of input circuit in a kind of comparator of the present invention;
Fig. 5 is the physical circuit figure of sluggish regulating circuit in a kind of comparator of the present invention;
Fig. 6 is the physical circuit figure of output circuit in a kind of comparator of the present invention;
Fig. 7 is the physical circuit figure of a kind of comparator of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
At first technical term involved in the present invention is described:
MOS:metal oxide semiconductor, metal-oxide semiconductor (MOS);
CMOS:complementary metal-oxide semiconductor, complementary metal oxide semiconductors (CMOS);
PMOS:P-channel metal oxide semiconductor FET, the P-channel metal-oxide-semiconductor field-effect transistor;
NMOS:N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor.
With reference to Fig. 1, show the composition structure chart of a kind of comparator first embodiment of the present invention.Described comparator comprises input circuit 110, sluggish regulating circuit 120 and output circuit 130.
Described input circuit 110 is used to receive differential signal IN1, the IN2 that wide common mode is imported, and described input circuit 110 adopts complementary differential pair form.
Described input circuit 110 adopts complementary differential pair form, receives the input of differential signal IN1, IN2, and described input circuit 110 is configured to common-mode input voltage range from the supply voltage to the earthed voltage.
Described input circuit 110 comprises the differential transistor of a pair of first conduction type, the differential transistor of a pair of second conduction type;
The differential transistor complementation of the differential transistor of described a pair of first conduction type and described a pair of second conduction type is sampled to the differential signal of described wide common mode input.
Described sluggish regulating circuit 120 is used to be provided with retarding window, regulates the output of described input circuit 110.
Described output circuit 130 is used to receive the output signal of described input circuit 110, produces wide amplitude of oscillation output signal C1.
With reference to Fig. 4, show the physical circuit figure of input circuit in a kind of comparator of the present invention.
Described input circuit 110 comprises the first nmos pass transistor MN41, the second nmos pass transistor MN42, the 3rd PMOS transistor MP43, the 4th PMOS transistor MP44, the first current source I405 and the first current source I406, the differential transistor of described a pair of first conduction type is made up of described first nmos pass transistor MN41 and the described second nmos pass transistor MN42, and the differential transistor of described a pair of second conduction type is made up of described the 3rd PMOS transistor MP43 and described the 4th PMOS transistor MP44.
The grid of the grid of the described first nmos pass transistor MN41 and described the 4th PMOS transistor MP44 is connected first input end as described input circuit 110, the grid of the grid of the described second nmos pass transistor MN42 and described the 3rd PMOS transistor MP43 is connected second input terminal as described input circuit 110, and described input circuit 110 receives differential signal IN1, the IN2 of wide common mode input by described first input end and described second input terminal.
The source electrode of the source electrode of the described first nmos pass transistor MN41 and the described second nmos pass transistor MN42 is connected with the positive pole of the described first current source I406, the source electrode of the source electrode of described the 3rd PMOS transistor MP43 and described the 4th PMOS transistor MP44 is connected with the negative pole of the described first current source I405, the negative pole of the described first current source I406 connects earthed voltage, and the positive pole of the described first current source I405 connects supply voltage.
The drain electrode of the described first nmos pass transistor MN41 forms first lead-out terminal 401, the drain electrode of the described second nmos pass transistor MN42 forms second lead-out terminal 402, the drain electrode of described the 4th PMOS transistor MP44 forms the 3rd lead-out terminal 403, and the drain electrode of described the 3rd PMOS transistor MP43 forms the 4th lead-out terminal 404.
As input circuit, can be divided into three service areas in its common-mode input range: when the input of lower common-mode voltage, i.e. common-mode voltage V
CM＜V
SS+ V
DS+ V
GSThe time, described the 3rd PMOS transistor MP43 and described the 4th PMOS transistor MP44 conducting, described first nmos pass transistor MN41 and the described second nmos pass transistor MN42 end, and bias current is provided by the described first current source I405.
When the input of higher common-mode voltage, i.e. common-mode voltage V
CM＞V
DD-| V
DS|-| V
GS| the time, described first nmos pass transistor MN41 and the described second nmos pass transistor MN42 conducting, described the 3rd PMOS transistor MP43 and described the 4th PMOS transistor MP44 end, and bias current is provided by the first current source I406.
When common mode input is V
SS+ V
DS+ V
GS＜V
CM＜V
DD-| V
DS|-| V
GS|, be that common mode input is when intermediate range, the described first nmos pass transistor MN41, the described second nmos pass transistor MN42, described the 3rd PMOS transistor MP43 and described the 4th all conductings of PMOS transistor MP44, bias current is provided jointly by described first current source I405 and the described first current source I406.
Adopt the input structure of this nmos pass transistor and the complementation of PMOS transistor, can realize in the scope of common mode input from the supply voltage to the earthed voltage performance requirement of input circuit operate as normal.
With reference to Fig. 5, show the physical circuit figure of sluggish regulating circuit in a kind of comparator of the present invention.
Described sluggish regulating circuit 120 comprises the 5th PMOS transistor MP501, the 6th PMOS transistor MP502, the 7th PMOS transistor MP503, the 8th PMOS transistor MP504, the 9th PMOS transistor MP505, the tenth PMOS transistor MP506, the 11 nmos pass transistor MN507, the tenth bi-NMOS transistor MN508, the 13 nmos pass transistor MN509, the 14 nmos pass transistor MN510, the 15 nmos pass transistor MN511 and the 16 nmos pass transistor MN512.
Connect described second lead-out terminal 402 behind the grid of described the 5th PMOS transistor MP501 and the drain electrode short circuit, the drain electrode of the drain electrode of the grid of described the 6th PMOS transistor MP502, described the 7th PMOS transistor MP503, the transistorized grid of described the 8th PMOS, described the 11 nmos pass transistor MN507 is connected to the drain electrode of described the 5th PMOS transistor MP501.
Connect described first lead-out terminal 401 behind the grid of described the tenth PMOS transistor MP506 and the drain electrode short circuit, the drain electrode of the drain electrode of the grid of described the 9th PMOS transistor MP505, described the 8th PMOS transistor MP504, the grid of described the 7th PMOS transistor MP503, described the 16 nmos pass transistor MN512 is connected to the drain electrode of described the tenth PMOS transistor MP506.
Connect described the 3rd lead-out terminal 403 behind the grid of described the tenth bi-NMOS transistor MN508 and the drain electrode short circuit, the grid of the grid of described the 11 nmos pass transistor MN507, the drain electrode of described the 13 nmos pass transistor MN509, described the 14 nmos pass transistor MN510 is connected to the drain electrode of described the tenth bi-NMOS transistor MN508.
Connect described the 4th lead-out terminal 404 behind the grid of described the 15 nmos pass transistor MN511 and the drain electrode short circuit, the grid of described the 16 nmos pass transistor MN512, the drain electrode of described the 14 nmos pass transistor MN510, the grid of described the 13 nmos pass transistor MN509 are connected to the drain electrode of described the 15 nmos pass transistor MN511.
The source electrode of the source electrode of described the 11 nmos pass transistor MN507, described the tenth bi-NMOS transistor MN508, the source electrode of described the 13 nmos pass transistor MN509, the source electrode of described the 14 nmos pass transistor MN510, the source electrode of described the 15 nmos pass transistor MN511, the source electrode of described the 16 nmos pass transistor MN512 connect earthed voltage respectively.
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of described the 5th PMOS transistor MP501, described the 6th PMOS transistor MP502, described the 7th PMOS transistor MP503, described the 8th PMOS transistor MP504, described the 9th PMOS transistor MP505, described the tenth PMOS transistor MP506 connects supply voltage respectively.
Wherein, described the 7th PMOS transistor MP503 is identical with the breadth length ratio of described the 8th PMOS transistor MP504, described the 5th PMOS transistor MP501 is identical with the breadth length ratio of described the 9th PMOS transistor MP505, described the tenth bi-NMOS transistor MN508 is identical with the breadth length ratio of described the 15 nmos pass transistor MN511, described the 13 nmos pass transistor MN509 is identical with the breadth length ratio of described the 14 nmos pass transistor MN510, by the retarding window that is symmetrically formed symmetry of described transistor size.Adopt described sluggish regulating circuit can well suppress noise.
Referring to Fig. 6, show the physical circuit figure of output circuit in a kind of comparator of the present invention.
Described output circuit 130 comprises the 17 nmos pass transistor MN615, the 18 nmos pass transistor MN616, the 19 PMOS transistor MP617 and the 20 PMOS transistor MP618.
The grid of described the 19 PMOS transistor MP617 and drain electrode short circuit, the drain electrode of described the 17 nmos pass transistor MN615 connects the drain electrode of described the 19 PMOS transistor MP617, the grid of described the 20 PMOS transistor MP618 connects the grid of described the 19 PMOS transistor MP617, the drain electrode of described the 20 PMOS transistor MP618 connects the lead-out terminal of the drain electrode of described the 18 nmos pass transistor MN616 as described output circuit 130, be used to export wide amplitude of oscillation output signal C1, the source electrode of described the 19 PMOS transistor MP617 connects power supply, the source electrode of described the 20 PMOS transistor MP618 connects power supply, the source ground of described the 17 nmos pass transistor MN615, the source ground of described the 18 nmos pass transistor MN616, the grid of described the 17 nmos pass transistor MN615 connects described the 3rd lead-out terminal 403, and the grid of described the 18 nmos pass transistor MN616 connects described the 4th lead-out terminal 404.
Adopt described output circuit 130, can improve output voltage swing, satisfy the requirement of wide amplitude of oscillation output.
The invention provides a kind of input voltage range and be supply voltage to earthed voltage on a large scale in the comparator of operate as normal, adjusting by sluggish regulating circuit, retarding window can be set accurately, thereby good restraining noise, output circuit not only responds soon, and has the big characteristics of output voltage swing.
Based on above reason, wide common mode input hysteresis voltage comparator of the present invention is applied to D class audio frequency PWM comparator and is undoubtedly optimal selection.Certainly also be not limited thereto the application in field, have under the situation of identical performance requirement, comparator of the present invention can be suitable for.
The invention also discloses a kind of D genus audio power amplifier, described D genus audio power amplifier comprises the described comparator of above each embodiment, considers for length, does not repeat them here, and gets final product with reference to the description of front relevant portion.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a comparator is characterized in that, comprising:
Input circuit, be used to receive differential signal, produce and amplify output signal, wherein, described input circuit comprises first nmos pass transistor, second nmos pass transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the grid of described first nmos pass transistor is connected first input end as described input circuit with the transistorized grid of described the 4th PMOS, the grid of described second nmos pass transistor is connected second input terminal as described input circuit with the transistorized grid of described the 3rd PMOS, described input circuit receives described differential signal by described first input end and described second input terminal;
Sluggish regulating circuit is used to be provided with retarding window, regulates the output signal of described input circuit;
Output circuit is used to receive the output signal of described input circuit, produces output signal;
Wherein, described sluggish regulating circuit comprises the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the tenth PMOS transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Connect described second lead-out terminal behind transistorized grid of described the 5th PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 6th PMOS, described the 7th PMOS transistor drain, the transistorized grid of described the 8th PMOS, described the 11 nmos pass transistor is connected to described the 5th PMOS transistor drain;
Connect described first lead-out terminal behind transistorized grid of described the tenth PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 9th PMOS, described the 8th PMOS transistor drain, the transistorized grid of described the 7th PMOS, described the 16 nmos pass transistor is connected to described the tenth PMOS transistor drain;
Connect described the 3rd lead-out terminal behind the grid of described the tenth bi-NMOS transistor and the drain electrode short circuit, the grid of the grid of described the 11 nmos pass transistor, the drain electrode of described the 13 nmos pass transistor, described the 14 nmos pass transistor is connected to the drain electrode of described the tenth bi-NMOS transistor;
Connect described the 4th lead-out terminal behind the grid of described the 15 nmos pass transistor and the drain electrode short circuit, the grid of the grid of described the 16 nmos pass transistor, the drain electrode of described the 14 nmos pass transistor, described the 13 nmos pass transistor is connected to the drain electrode of described the 15 nmos pass transistor;
The source electrode of the source electrode of the source electrode of described the 11 nmos pass transistor, described the tenth bi-NMOS transistor, the source electrode of described the 13 nmos pass transistor, the source electrode of described the 14 nmos pass transistor, the source electrode of described the 15 nmos pass transistor, described the 16 nmos pass transistor connects earthed voltage respectively;
The transistorized source electrode of described the 5th PMOS, the transistorized source electrode of described the 6th PMOS, the transistorized source electrode of described the 7th PMOS, the transistorized source electrode of described the 8th PMOS, the transistorized source electrode of described the 9th PMOS, the transistorized source electrode of described the tenth PMOS connect supply voltage VDD respectively.
2. comparator according to claim 1 is characterized in that:
Described input circuit is configured to complementary differential pair form, its common-mode input voltage range from supply voltage VDD to earthed voltage.
3. comparator according to claim 2 is characterized in that:
Described input circuit also comprises first current source and second current source, the partner differential transistor of second conduction type of the partner differential transistor of first conduction type of described first nmos pass transistor and described second nmos pass transistor, described the 3rd PMOS transistor and described the 4th PMOS transistor;
The source electrode of the source electrode of described first nmos pass transistor and described second nmos pass transistor is connected with the positive pole of described second current source, the transistorized source electrode of described the 3rd PMOS is connected with the negative pole of described first current source with the transistorized source electrode of described the 4th PMOS, the negative pole of described second current source connects earthed voltage, and the positive pole of described first current source meets supply voltage VDD;
The drain electrode of described first nmos pass transistor is as first lead-out terminal, the drain electrode of described second nmos pass transistor is as second lead-out terminal, described the 4th PMOS transistor drain is as the 3rd lead-out terminal, and described the 3rd PMOS transistor drain is as the 4th lead-out terminal.
4. comparator according to claim 1 is characterized in that:
Described the 7th PMOS transistor is identical with the transistorized breadth length ratio of described the 8th PMOS, described the 5th PMOS transistor is identical with the transistorized breadth length ratio of described the 9th PMOS, described the tenth bi-NMOS transistor is identical with the breadth length ratio of described the 15 nmos pass transistor, described the 13 nmos pass transistor is identical with the breadth length ratio of described the 14 nmos pass transistor, by the retarding window that is symmetrically formed symmetry of described transistor size.
5. comparator according to claim 4 is characterized in that:
Described output circuit comprises the 17 nmos pass transistor, the 18 nmos pass transistor, the 19 PMOS transistor and the 20 PMOS transistor;
Transistorized grid of described the 19 PMOS and drain electrode short circuit, the drain electrode of described the 17 nmos pass transistor connects described the 19 PMOS transistor drain, the transistorized grid of described the 20 PMOS connects the transistorized grid of described the 19 PMOS, described the 20 PMOS transistor drain connects the lead-out terminal of the drain electrode of described the 18 nmos pass transistor as described output circuit, be used to produce output signal, the transistorized source electrode of described the 19 PMOS connects power supply, the transistorized source electrode of described the 20 PMOS connects power supply, the source ground of described the 17 nmos pass transistor, the source ground of described the 18 nmos pass transistor, the grid of described the 17 nmos pass transistor connects described the 3rd lead-out terminal, and the grid of described the 18 nmos pass transistor connects described the 4th lead-out terminal.
6. a D genus audio power amplifier is characterized in that, comprises comparator, and described comparator comprises:
Input circuit, be used to receive differential signal, produce and amplify output signal, wherein, described input circuit comprises first nmos pass transistor, second nmos pass transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the grid of described first nmos pass transistor is connected first input end as described input circuit with the transistorized grid of described the 4th PMOS, the grid of described second nmos pass transistor is connected second input terminal as described input circuit with the transistorized grid of described the 3rd PMOS, described input circuit receives described differential signal by described first input end and described second input terminal;
Sluggish regulating circuit is used to be provided with retarding window, regulates the output signal of described input circuit;
Output circuit is used to receive the output signal of described input circuit, produces output signal;
Wherein, described sluggish regulating circuit comprises the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the tenth PMOS transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Connect described second lead-out terminal behind transistorized grid of described the 5th PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 6th PMOS, described the 7th PMOS transistor drain, the transistorized grid of described the 8th PMOS, described the 11 nmos pass transistor is connected to described the 5th PMOS transistor drain;
Connect described first lead-out terminal behind transistorized grid of described the tenth PMOS and the drain electrode short circuit, the drain electrode of the transistorized grid of described the 9th PMOS, described the 8th PMOS transistor drain, the transistorized grid of described the 7th PMOS, described the 16 nmos pass transistor is connected to described the tenth PMOS transistor drain;
Connect described the 3rd lead-out terminal behind the grid of described the tenth bi-NMOS transistor and the drain electrode short circuit, the grid of the grid of described the 11 nmos pass transistor, the drain electrode of described the 13 nmos pass transistor, described the 14 nmos pass transistor is connected to the drain electrode of described the tenth bi-NMOS transistor;
Connect described the 4th lead-out terminal behind the grid of described the 15 nmos pass transistor and the drain electrode short circuit, the grid of the grid of described the 16 nmos pass transistor, the drain electrode of described the 14 nmos pass transistor, described the 13 nmos pass transistor is connected to the drain electrode of described the 15 nmos pass transistor;
The source electrode of the source electrode of the source electrode of described the 11 nmos pass transistor, described the tenth bi-NMOS transistor, the source electrode of described the 13 nmos pass transistor, the source electrode of described the 14 nmos pass transistor, the source electrode of described the 15 nmos pass transistor, described the 16 nmos pass transistor connects earthed voltage respectively;
The transistorized source electrode of described the 5th PMOS, the transistorized source electrode of described the 6th PMOS, the transistorized source electrode of described the 7th PMOS, the transistorized source electrode of described the 8th PMOS, the transistorized source electrode of described the 9th PMOS, the transistorized source electrode of described the tenth PMOS connect supply voltage VDD respectively.
7. D genus audio power amplifier according to claim 6 is characterized in that:
Described input circuit is configured to complementary differential pair form, its common-mode input voltage range from supply voltage VDD to earthed voltage.
8. D genus audio power amplifier according to claim 7 is characterized in that:
Described input circuit also comprises first current source and second current source, the partner differential transistor of second conduction type of the partner differential transistor of first conduction type of described first nmos pass transistor and described second nmos pass transistor, described the 3rd PMOS transistor and described the 4th PMOS transistor;
The source electrode of the source electrode of described first nmos pass transistor and described second nmos pass transistor is connected with the positive pole of described second current source, the transistorized source electrode of described the 3rd PMOS is connected with the negative pole of described first current source with the transistorized source electrode of described the 4th PMOS, the negative pole of described second current source connects earthed voltage, and the positive pole of described first current source meets supply voltage VDD;
The drain electrode of described first nmos pass transistor is as first lead-out terminal, the drain electrode of described second nmos pass transistor is as second lead-out terminal, described the 4th PMOS transistor drain is as the 3rd lead-out terminal, and described the 3rd PMOS transistor drain is as the 4th lead-out terminal.
9. D genus audio power amplifier according to claim 6 is characterized in that:
Described the 7th PMOS transistor is identical with the transistorized breadth length ratio of described the 8th PMOS, described the 5th PMOS transistor is identical with the transistorized breadth length ratio of described the 9th PMOS, described the tenth bi-NMOS transistor is identical with the breadth length ratio of described the 15 nmos pass transistor, described the 13 nmos pass transistor is identical with the breadth length ratio of described the 14 nmos pass transistor, by the retarding window that is symmetrically formed symmetry of described transistor size.
10. D genus audio power amplifier according to claim 9 is characterized in that:
Described output circuit comprises the 17 nmos pass transistor, the 18 nmos pass transistor, the 19 PMOS transistor and the 20 PMOS transistor;
Transistorized grid of described the 19 PMOS and drain electrode short circuit, the drain electrode of described the 17 nmos pass transistor connects described the 19 PMOS transistor drain, the transistorized grid of described the 20 PMOS connects the transistorized grid of described the 19 PMOS, described the 20 PMOS transistor drain connects the lead-out terminal of the drain electrode of described the 18 nmos pass transistor as described output circuit, be used to produce output signal, the transistorized source electrode of described the 19 PMOS connects power supply, the transistorized source electrode of described the 20 PMOS connects power supply, the source ground of described the 17 nmos pass transistor, the source ground of described the 18 nmos pass transistor, the grid of described the 17 nmos pass transistor connects described the 3rd lead-out terminal, and the grid of described the 18 nmos pass transistor connects described the 4th lead-out terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101266247A CN101557216B (en) | 2009-03-05 | 2009-03-05 | Comparator and D-class audio power amplifier comprising comparator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101266247A CN101557216B (en) | 2009-03-05 | 2009-03-05 | Comparator and D-class audio power amplifier comprising comparator |
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| Publication Number | Publication Date |
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| CN101557216A CN101557216A (en) | 2009-10-14 |
| CN101557216B true CN101557216B (en) | 2011-12-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101902215B (en) * | 2010-08-02 | 2012-09-26 | 中颖电子股份有限公司 | Four-input terminal comparator |
| JP6651835B2 (en) * | 2015-03-13 | 2020-02-19 | ヤマハ株式会社 | Power amplifier |
| EP3116127B1 (en) * | 2015-07-08 | 2018-09-12 | Power Integrations Switzerland GmbH | Receiver circuit |
| CN109714031B (en) * | 2018-12-11 | 2023-03-17 | 中山芯达电子科技有限公司 | Rail-to-rail high-performance comparator |
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