CN100578924C

CN100578924C - Output stage circuit, power amplifying circuit and processing method of electric signal

Info

Publication number: CN100578924C
Application number: CN200710076335A
Authority: CN
Inventors: 熊涛
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2007-07-03
Filing date: 2007-07-03
Publication date: 2010-01-06
Anticipated expiration: 2027-07-03
Also published as: CN101110575A

Abstract

The invention provides an output stage circuit of a power amplifier and a processing method of an electric signal. In the technical solution provided by the embodiment of the present invention, when the circuit is static, the switch circuit is controlled by the output signal to conduct, thereby generating a shunt current, and the current shunted by the shunt current is amplified as the output terminal current; and when the circuit is in operation, The switch circuit is turned off, and the current is directly amplified without shunting as the driving current. Therefore, the technical solution provided by the embodiment of the present invention can effectively reduce the quiescent current of the circuit while ensuring the driving capability, thereby reducing the quiescent power consumption.

Description

Output-stage circuit, power amplification circuit and electric signal processing method

Technical field

The present invention relates to electronic circuit technology, more specifically, relate to a kind of output-stage circuit and electric signal processing method of power amplifier.

Background technology

In some application of analog integrated circuit, to output driving force the requirement meeting than higher, the for example driving of the loud speaker in the voice applications, earphone, load resistance has only tens even several ohm, drive circuit need provide tens even the output current of hundreds of milliampere, require again simultaneously to guarantee that output has enough low linear distortion, and, require circuit to have very low quiescent dissipation especially along with the application that gets more and more now on handheld device.

At present the output amplifier that uses has category-A, and three kinds of structures of category-B and AB class are introduced a kind of export structure of traditional AB power-like amplifier below.

As shown in Figure 1, P type amplifier 321 is formed voltage follower structure with PMOS (P-channel metal-oxide-semiconductor) driving transistors (being called for short P type driving tube) 327: wherein the output of P type amplifier 321 links to each other with the grid of P type driving tube 327, the drain electrode of the in-phase input end of P type amplifier 321 and P type driving tube 327 is connected in the output 302 of voltage follower structure, the negative-phase input of P type amplifier 321 links to each other with the input 301 of voltage follower, and the source electrode of P type driving tube 327 links to each other with voltage source 103; Equally, N type amplifier 311 is also formed voltage follower structure with NMOS (N NMOS N-channel MOS N) driving transistors (being called for short N type driving tube) 317: wherein the output of N type amplifier 311 links to each other with the grid of N type driving tube 317, the drain electrode of the in-phase input end of N type amplifier 311 and N type driving tube 317 is connected in the output 302 that voltage follow plays structure, the negative-phase input of N type amplifier 311 links to each other with the input 301 that voltage follow rises, and the source electrode of N type driving tube 317 links to each other with earth terminal 100.Entire circuit is to be made of two voltage follower circuits that are operated in different input voltage ranges, and output voltage equates with input voltage.

Wherein P type amplifier 321 as shown in Figure 2: be the load by the 7th NMOS pipe the 410 and the 8th NMOS pipe 411 differential configurations that constitute by the 7th PMOS pipe the 412 and the 8th PMOS pipe 413 current mirrors that constitute, the source electrode of the source electrode of the 7th PMOS pipe 412 and the 8th PMOS pipe 413 is connected in voltage source 103, the source electrode and first bias current sources 403 of the source electrode of the 7th NMOS pipe 410 and the 8th NMOS pipe 411 are connected in node 422, the other end of first bias current sources 403 links to each other with common 100, the drain electrode of the grid of the grid of the 7th PMOS pipe 412 and the 8th PMOS pipe 413 and the 7th NMOS pipe 410 is connected in node 426, the grid of the 7th NMOS pipe 410 links to each other with the in-phase input end 420 of P type amplifier 321, the grid of the 8th NMOS pipe 411 links to each other with the inverting input 421 of P type amplifier 321, and the drain electrode of the 8th PMOS pipe 413 links to each other with the output 421 of P type amplifier 321 with the drain electrode of the 8th NMOS pipe 411.

This P type amplifier 321 is for having the differential right of source load (current mirror that the 7th PMOS pipe the 412 and the 8th PMOS pipe 413 constitutes), it with the differential input signal of in-phase input end 420 and inverting input 421 via the 7th NMOS pipe the 410 and the 8th NMOS pipe 411 transform pass to the active electric current mirror after, differential input is converted to the single-ended output of P type amplifier 321 outputs 443 by this current mirror.

Wherein N type amplifier 311 as shown in Figure 3: be the load by the 9th PMOS pipe the 430 and the tenth PMOS pipe 431 differential configurations that constitute by the 9th NMOS pipe the 432 and the tenth NMOS pipe 433 current mirrors that constitute, the source electrode of the 9th NMOS pipe the 432 and the tenth NMOS pipe 433 is connected in common 100, the source electrode and second bias current sources 404 of the 9th PMOS pipe the 430 and the tenth PMOS pipe 431 are connected in node 442, the other end of second bias current sources 404 links to each other with voltage source 103, the drain electrode of the grid of the grid of the 9th NMOS pipe 432 and the tenth NMOS pipe 433 and the 9th PMOS pipe 430 is connected in node 446, the grid of the 9th PMOS pipe 430 links to each other with the in-phase input end 440 of N type amplifier 311, the grid of the tenth PMOS pipe 431 links to each other with the inverting input 441 of N type amplifier 311, and the drain electrode of the tenth NMOS pipe 433 links to each other with the output 443 of N type amplifier 311 with the drain electrode of the tenth PMOS pipe 431.

This N type amplifier 311 is for having the differential right of source load (current mirror that the 9th NMOS pipe the 432 and the tenth NMOS pipe 433 constitutes), it with the differential input signal of in-phase input end 440 and inverting input 411 via the 9th PMOS pipe the 430 and the tenth PMOS pipe 431 transform pass to the active electric current mirror after, differential input is converted to the single-ended output of N type amplifier 311 outputs 443 by this current mirror.

By the structure of amplifier as can be known, the signal input range of N type amplifier 311 and P type amplifier 321 is limited but complementary, when input voltage during relatively near power supply (being voltage source 103) voltage, the voltage follower that P type amplifier 312 and P type driving tube 327 are formed works independently, when input voltage more closely the time, the voltage follower that N type amplifier 311 and N type driving tube 317 are formed works independently, and input voltage is during near intermediate level, then two voltage followers can be worked, and so just can guarantee that total is applicable to bigger voltage input.

Because the electric current that flows through P type driving tube 327 and N type driving tube 317 is relevant with the size (breadth length ratio) of the output voltage of

amplifier

321 and 311 and they self respectively, by increasing the size of

driving tube

327 and 317, this output-stage circuit just can provide very big output driving current.

When circuit is in static state, just circuit powers on, and when still load not being driven, differential configuration pipe the 7th NMOS pipe the 410 and the 8th NMOS pipe 411 in the amplifier 321 is in saturated, since the symmetry of entire circuit, the voltage V at node 423 places ₄₂₃Equal the voltage V at node 426 places ₄₂₆So there is the grid voltage of the 8th PMOS pipe 413 to equate with the grid voltage of P type driving tube 327, and the source voltage of the 8th PMOS pipe 413 and P type driving tube 327 is the voltage of voltage source 103, so their the gate source voltage voltage difference of source electrode (grid with) equates, by the current formula of the metal-oxide-semiconductor that is operated in the saturation region as can be known, flow through their ratio of electric current is the ratio of their breadth length ratio.

Half of the electric current that the same because symmetry of circuit, the electric current of the 8th PMOS that flows through pipe 413 provide for first bias current sources 403, the electric current that establishing first bias current sources 403 provides is I ₀, the electric current of the 8th PMOS that then flows through pipe 413 is

The electric current I of P type driving tube 327 so flow through _P327For:

I_{P 327} = \frac{{(W / L)}_{327}}{{(W / L)}_{413}} * \frac{I_{0}}{2},

Wherein, (W/L) ₃₂₇Be the breadth length ratio of P type driving tube 327, (W/L) ₄₁₃It is the breadth length ratio of the 8th PMOS pipe 413.

Symmetry requirement by circuit, first bias current sources 403 in the P type amplifier 321 equates with the size of current that second bias current sources 404 in the N type amplifier 311 is provided, so, based on top described same reason, the electric current I of the N type of flowing through driving tube 317 _N317For:

I_{N 317} = \frac{{(W / L)}_{317}}{{(W / L)}_{433}} * \frac{I_{0}}{2},

Wherein (W/L) ₃₁₇Be the breadth length ratio of N type driving tube 317, (W/L) ₄₃₃It is the breadth length ratio of the tenth NMOS pipe 433.

Should select the size of each metal-oxide-semiconductor during design, make:

\frac{{(W / L)}_{327}}{{(W / L)}_{413}} = \frac{{(W / L)}_{317}}{{(W / L)}_{433}},

Thereby the quiescent current of output stage is

That is

So when increasing the driving tube size when the requirement that will satisfy big drive current, the static working current of circuit can be bigger, thereby cause quiescent dissipation big.

If only just satisfying, the operating voltage range of circuit shown in Figure 1 drives requirement in the input voltage range of P type amplifier 321, so, following half of circuit, promptly the voltage follow structure of being made up of N type amplifier 311 and N type driving tube 327 can be substituted by a bias current sources, as shown in Figure 4, this bias current sources provides a direct current biasing when static to circuit, and this moment, circuit was equivalent to a category-A output-stage circuit.

In this case, the bias current sources one end ground connection among Fig. 4, the output of other end connection circuit, the size of current when its size of current is the first half circuit static state, for

Certainly, drive requirement if the operating voltage range of circuit shown in Figure 1 only just satisfies in the input voltage range of N type amplifier 311, the first half circuit also can be substituted by a bias current sources so, and principle is identical.

Equally, when this circuit that has adopted bias current sources increased the driving tube size when the requirement that will satisfy big drive current, the static working current of circuit also can be bigger, thereby cause quiescent dissipation big.

This problem is mainly reflected in two aspects:

1, the static working current absolute value is bigger.This mainly is because for enough output driving currents can be provided, output driving tube size all designs very big usually, even cause the bias current I in the amplifier ₀Very little, still have bigger static working current in the driving tube.

2, static working current is to the input offset voltage sensitivity.Because the open-loop gain of voltage follower circuit is very big usually, therefore it is very responsive to the variation of input voltage to export the driving tube electric current, because the driving tube electric current directly is controlled by the output voltage of amplifier circuit, and this voltage equals the gain of amplifier circuit and the product of input difference voltage.Like this, when voltage follower (or amplifier) when there is input offset voltage in circuit, the static working current of output driving tube then may have bigger variation, even quiescent dissipation is multiplied.

Summary of the invention

Embodiments of the invention provide a kind of output-stage circuit, reduce quiescent dissipation when satisfying the driving force requirement.

Embodiments of the invention disclose a kind of output-stage circuit, comprising:

First operational amplifier is used to receive first input signal and second input signal, and described first input signal and second input signal are carried out the difference processing and amplifying and export the difference processing result;

First node;

First output circuit, be connected between the output of described first node and described first operational amplifier, be used to receive the difference processing result of described first operational amplifier, and produce first electric current of the described first node of flowing through according to the difference processing result of described first operational amplifier;

Biasing circuit, be connected in first node, be used for based on described first electric current, form first voltage at first node, and the circuit that described first electric current during based on static state is formed described first operational amplifier and described first output circuit carries out quiescent biasing, and wherein said first voltage is second input signal of described first operational amplifier;

Described first output circuit comprises:

Section Point;

First change-over circuit, be connected between the output and described Section Point of described first operational amplifier, be used to receive the difference processing result of described first operational amplifier, and adjust second electric current between described first change-over circuit and the described Section Point according to the difference processing result of described first operational amplifier;

The first feedthrough shunt circuit links to each other with described Section Point, is used for forming when described output-stage circuit is in static state the 3rd electric current between described first feedthrough shunt circuit and the described Section Point;

First output processing circuit, be connected between described first node and the described Section Point, be used for the 4th electric current between described first output processing circuit and the described Section Point is converted into described first electric current of the described first node of flowing through, described first electric current is greater than described the 4th electric current;

Described second electric current is described the 3rd electric current and described the 4th electric current sum.

Embodiments of the invention also disclose a kind of electric signal processing method, comprise the steps:

First operational amplifier carries out first input voltage signal and second input signal to produce the difference processing result after difference is amplified;

First conversion circuit produces second electric current of the Section Point of flowing through according to described difference processing result;

The first feedthrough shunt circuit produces the 3rd electric current of the described Section Point of flowing through when static state, and produce the 4th electric current of the described Section Point of flowing through according to described second electric current and described the 3rd electric current, make described second electric current equal described the 3rd electric current and described the 4th electric current sum;

First output processing circuit is converted into described the 4th electric current in first electric current of the first node of flowing through, and produce first voltage at described first node, described first electric current is greater than described the 4th electric current, described first voltage is described second input signal, wherein, the point that links to each other with the output of output-stage circuit of described first output processing circuit is a first node.

The disclosed technical scheme of the embodiment of the invention, for entire circuit, input signal is converted to an intermediate current, the electric current that is used to drive is to be amplified by described intermediate current to produce, because also being amplified by described intermediate current, the electric current when static produces, and when static state, circuit can be shunted described intermediate current, described intermediate current is shunted the back and is produced a static reference current, described static reference current is amplified the quiescent current that becomes the output of flowing through by circuit again, and described static reference current is less than described intermediate current, thus can reduce the quiescent current of circuit, thus reduce quiescent dissipation.

Description of drawings

Fig. 1 is a prior art AB power-like amplifier output stage circuit;

Fig. 2 is the internal circuit of P type amplifier among Fig. 1;

Fig. 3 is the internal circuit of N type amplifier among Fig. 1;

Fig. 4 replaces with the circuit of bias current sources for the latter half circuit among Fig. 1;

Fig. 5 is the circuit structure diagram of the embodiment of the invention;

Fig. 6 is the circuit diagram of the embodiment of the invention 1;

Fig. 7 is the internal circuit of first amplifier in the embodiment of the invention 1;

Fig. 8 is the internal circuit of second amplifier in the embodiment of the invention 1;

Fig. 9 is the circuit diagram of the embodiment of the invention 2;

Figure 10 is the circuit diagram of the embodiment of the invention 3;

Figure 11 is the circuit diagram of the embodiment of the invention 4;

Figure 12 is the circuit diagram of the embodiment of the invention 5;

Figure 13 is the circuit diagram of the embodiment of the invention 6;

Figure 14 is the flow chart of the embodiment of the invention 7.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, utilize specific embodiment below, the present invention is further detailed explanation.

As shown in Figure 5, first operational amplifier 1 receives the input signal of input, and first output circuit 2 receives the output signal of described first operational amplifier, and produces the electric current of the output of flowing through according to this output signal.

Particularly, first output circuit 2 comprises first change-over circuit 21, first output processing circuit 22 and the first feedthrough shunt circuit 23, first change-over circuit 22 is converted to electric current with the output signal of first operational amplifier 1, first output processing circuit 22 receives the electric current of first change-over circuit 21 and the electric current that receives is converted into the electric current of the output of flowing through, the first feedthrough shunt circuit 23 is controlled by output end signal, when being in static state, circuit shown in Figure 5 produces shunt current, this shunt current is used for the electric current that first change-over circuit 21 produces is shunted, to reduce the flow through when static electric current of output of circuit.

Biasing circuit 3 provides the quiescent biasing to circuit, and certainly, this biasing circuit can have various ways, except simple biasing when static state is provided, also can have driving action.

Embodiment 1:

In the output-stage circuit as shown in Figure 6, first operational amplifier 1 is specially first amplifier 121, first change-over circuit 21 is specially NMOS pipe 123, first output processing circuit 22 is specially first current mirror output that PMOS pipe the 126 and the 2nd PMOS pipe 127 is formed, the first feedthrough shunt circuit 23 comprises specifically that then the first shunting generation circuit and 128, the first shuntings of PMOS switching tube produce circuit and specifically comprise the 2nd NMOS pipe 122 again and manage the 124 first shunt current mirrors of forming by the 3rd PMOS pipe the 125 and the 4th PMOS.

Biasing circuit 3 makes entire circuit have symmetry, except providing the quiescent biasing to circuit, also has driving force.Biasing circuit comprises second operational amplifier (being specially second amplifier 111 in this circuit), second change-over circuit (in this circuit, being specially the 5th PMOS pipe 113), second output processing circuit (in this circuit, being specially) and the second feedthrough shunt circuit (comprising specifically that in this circuit the second shunting generation circuit and 118, the second shuntings of nmos switch pipe produce circuit and comprise the 6th PMOS pipe 112 again and manage the 114 second shunt current mirrors of forming by the 5th NMOS pipe the 115 and the 6th NMOS) by the 3rd NMOS pipe the 116 and the 4th NMOS pipe 117 second current mirror outputs of forming.

The other parts of biasing circuit and entire circuit constitute symmetrical structure, and the structure of the first half of symmetric circuit is:

The in-phase input end of first amplifier 121 links to each other with the input of this output-stage circuit 101, reversed-phase output links to each other with the output 102 of this output-stage circuit, output links to each other with the grid of NMOS pipe 123, the source electrode of the one NMOS pipe 123 links to each other with common 100, drain electrode is connected in end points 107 with the input (i.e. the drain electrode of PMOS pipe 126) of being managed 127 first current mirror outputs of forming by PMOS pipe the 126 and the 2nd PMOS, the output of this first current mirror output (i.e. the drain electrode of the 2nd PMOS pipe 127) links to each other with the output 102 of described AB class output-stage circuit, and the source electrode of PMOS pipe 126 is connected with voltage source 103 respectively with the source electrode of the 2nd PMOS pipe 127.

Output-stage circuit as shown in Figure 6, the working method of symmetric circuit the first half is:

When 121 work of first amplifier, first amplifier 121 receives the input voltage of this AB class output-stage circuit, the one NMOS pipe 123 receives the output voltage of first amplifier 121 and according to the flow through electric current of NMOS pipe 123 of this voltage adjustment, I-E characteristic when also i.e. electric current between first change-over circuit and the Section Point (end points 107), concrete adjustment mode are can be by metal-oxide-semiconductor saturated obtains:

I = k * \frac{W}{L} {(V_{GS} - V_{TH})}^{2},

Wherein I is the electric current of metal-oxide-semiconductor of flowing through, and k is the physical parameter of metal-oxide-semiconductor, Be the breadth length ratio of metal-oxide-semiconductor, V _THBe the threshold voltage of metal-oxide-semiconductor, V _GSBe the voltage between the metal-oxide-semiconductor grid source.

From top formula as can be seen, when metal-oxide-semiconductor is in saturation condition, the electric current of metal-oxide-semiconductor of flowing through is to be adjusted by the gate source voltage of metal-oxide-semiconductor, and in circuit shown in Figure 6, the output signal of first amplifier 121 is added on the grid of NMOS pipe 123 just, determine the gate source voltage of NMOS pipe 123, thereby adjust the electric current of the NMOS pipe 123 of flowing through, also promptly adjust the electric current between first change-over circuit and the Section Point (end points 107).

This electric current is by the input pipe of described first current mirror output, promptly PMOS pipe 126 receives, after carrying out mirror image by this first current mirror output, by the efferent duct of this first current mirror output, promptly the 2nd PMOS pipe 127 outputs to image current the output 102 of this AB class output-stage circuit.

The first above-mentioned amplifier 121, the one NMOS pipe 123 and first current mirror output is constituting voltage follower between the input 101 of this AB class output-stage circuit and the output 102: when the input voltage of input 101 increases and during working range at first amplifier 121, the voltage that the one NMOS manages 123 grids increases, thereby the electric current of the NMOS that flows through pipe 123 increases, cause the mirror image output current of described first current mirror output to increase, thereby the voltage of the output 102 of this AB class output-stage circuit increases, promptly the inverting input voltage of first amplifier 121 increases, the grid voltage of the one NMOS pipe 123 reduces, thereby formation negative feedback, and because the open-loop gain of first amplifier 121 is very big, so this negative feedback is degree of depth negative feedback, make the voltage of voltage follow in-phase input end of the inverting input of the amplifier 121 of winning, i.e. the voltage of the voltage follow input 101 of the output 102 of this AB class output-stage circuit.

On this basis, this output-stage circuit also has one first feedthrough shunt circuit 23, introduces the syndeton of this first feedthrough shunt circuit below.

This first feedthrough shunt circuit is connected in the drain electrode of NMOS pipe 123, comprise first shunting generation circuit and the PMOS switching tube 128, this first shunting produces circuit and comprises the 2nd NMOS pipe 122 and manage the 124 first shunt current mirrors of forming by the 3rd PMOS pipe the 125 and the 4th PMOS.The grid of the 2nd NMOS pipe 122 links to each other with the output of first amplifier 121, and source electrode connects common 100, and drain electrode is connected in end points 106 with the input (i.e. the drain electrode of the 3rd PMOS pipe 125) of the first shunt current mirror; The grid of PMOS switching tube 128 is connected with the output 102 of this AB class output-stage circuit, drain electrode is connected in end points 107 (i.e. the drain electrode of NMOS pipe 123), source electrode links to each other with the output (i.e. the drain electrode of the 4th PMOS pipe 124) of the first shunt current mirror, and the source electrode of the 3rd PMOS pipe 125 links to each other with voltage source 103 with the source electrode of the 4th PMOS pipe 124.

The operation principle that the first feedthrough shunt circuit reduces quiescent current is as follows:

When AB class output-stage circuit shown in Figure 6 is in static state, the voltage of output 102 is in the intermediate level of circuit voltage scope, 128 conductings of PMOS switching tube, the 2nd NMOS pipe 122 is converted to current signal with the voltage signal of the output stage of first amplifier 121, this electric current is by the input pipe of the first shunt current mirror, promptly the 3rd PMOS pipe 125 receives, after carrying out mirror image by this first shunt current mirror, efferent duct by this first shunt current mirror, promptly the 4th PMOS pipe 124 outputs to image current the source electrode of PMOS switching tube 128, the PMOS switching tube 128 of conducting makes this image current flow into NMOS pipe 123, realization is to the shunting of the electric current of the NMOS pipe 123 of flowing through, so only some is mirrored onto the 2nd PMOS pipe 127 to electric current in the NMOS pipe 123, forms quiescent current; And when the voltage of output 102 to voltage source voltage near and make PMOS switching tube 128 by the time, circuit is in the foreign work state, all electric currents in the NMOS pipe all are mirrored onto the 2nd PMOS pipe 127, externally export big electric current, guarantee big driving force.

Output-stage circuit as shown in Figure 6, symmetric circuit the latter half also is that the structure of biasing circuit is:

The in-phase input end of second amplifier 111 links to each other with the input 101 of this AB class output-stage circuit, reversed-phase output links to each other with the output 102 of this AB class output-stage circuit, output links to each other with the grid of the 5th PMOS pipe 113, the source electrode of the 5th PMOS pipe 113 links to each other with voltage source 103, drain electrode is connected in end points 105 with the input (i.e. the drain electrode of the 3rd NMOS pipe 116) of being managed 117 second current mirror outputs of forming by the 3rd NMOS pipe the 116 and the 4th NMOS, the output of this second current mirror output (i.e. the drain electrode of the 4th NMOS pipe 117) links to each other with the output 102 of described AB class output-stage circuit, and the source electrode of the 3rd NMOS pipe 116 is connected with common 100 respectively with the source electrode of the 4th NMOS pipe 117.

AB class output-stage circuit as shown in Figure 6, the working method of symmetric circuit the latter half is:

When 111 work of second amplifier, second amplifier 111 receives the input voltage of this AB class output-stage circuit, the 5th PMOS pipe 113 receives the output voltage of second amplifier 111 and produces the electric current of the 5th PMOS pipe 113 of flowing through, this electric current is by the input pipe of described second current mirror output, promptly the 3rd NMOS pipe 116 receives, after carrying out mirror image by this second current mirror, by the efferent duct of this second current mirror output, promptly the 4th NMOS pipe 117 outputs to image current the output 102 of this AB class output-stage circuit.

The second above-mentioned amplifier 111, the 5th PMOS pipe 113 and second current mirror output is constituting voltage follower between the input 101 of this AB class output-stage circuit and the output 102: when the input voltage of input 101 increases and during working range at second amplifier 111, the voltage that the 5th PMOS manages 113 grids increases, thereby the electric current of the 5th PMOS that flows through pipe 113 increases, cause the mirror image output current of described second current mirror output to increase, thereby the voltage of the output 102 of this AB class output-stage circuit increases, promptly the inverting input voltage of second amplifier 111 increases, the grid voltage of the 5th PMOS pipe 113 reduces, thereby formation negative feedback, and because the open-loop gain of second amplifier 111 is very big, so this negative feedback is degree of depth negative feedback, make the voltage of voltage follow in-phase input end of the inverting input of the amplifier 111 of winning, i.e. the voltage of the voltage follow input 101 of the output 102 of this AB class output-stage circuit.

The voltage follow structure that the voltage follow structure that the first half of this symmetric circuit constitutes and the latter half constitute is formed AB class export structure, and they are setovered mutually, and produce driving force jointly.

On this basis, the biasing circuit of this output-stage circuit also has one second feedthrough shunt circuit, introduces the syndeton of this second feedthrough shunt circuit below.

This second feedthrough shunt circuit is connected in the drain electrode of the 5th PMOS pipe 113, comprise second fen current source circuit and nmos switch pipe 118, this second fen current source circuit comprises the 6th PMOS pipe 112 and manages the 114 second shunt current mirrors of forming by the 5th NMOS pipe the 115 and the 6th NMOS.The grid of the 6th PMOS pipe 112 links to each other with the output of second amplifier 111, and source electrode links to each other with voltage source 103, and drain electrode is connected in end points 104 with the input (i.e. the drain electrode of the 5th NMOS pipe 115) of the second shunt current mirror; The grid of nmos switch pipe 118 is connected with the output 102 of this AB class output-stage circuit, drain electrode is connected in end points 105 (i.e. the drain electrode of the 5th PMOS pipe 113), source electrode links to each other with the output (i.e. the drain electrode of the 6th NMOS pipe 114) of the second shunt current mirror, and the source electrode of the 5th NMOS pipe 115 links to each other with common 100 respectively with the source electrode of the 6th NMOS pipe 114.

The operation principle that the second feedthrough shunt circuit reduces quiescent current is as follows:

When AB class output-stage circuit shown in Figure 6 is in static state, the voltage of output 102 is in the intermediate level of circuit voltage scope, 118 conductings of nmos switch pipe, the 6th PMOS pipe 112 is converted to current signal with the voltage signal of the output stage of second amplifier 111, this electric current is by the input pipe of the second shunt current mirror, promptly the 5th NMOS pipe 115 receives, after carrying out mirror image by this second shunt current mirror, efferent duct by this second shunt current mirror, promptly the 6th NMOS pipe 114 outputs to image current the source electrode of nmos switch pipe 118, the nmos switch pipe 118 of conducting extracts this image current from the 5th PMOS pipe 113, realization is to the shunting of the electric current of the 5th PMOS pipe 113 of flowing through, so only some is mirrored onto the 4th NMOS pipe 117 to the electric current in the 5th PMOS pipe 113, forms static working current; And when the voltage of output 102 to ground voltage near and make nmos switch pipe 118 by the time, circuit is in the foreign work state, all electric currents in the 5th PMOS pipe 113 all are mirrored onto the 4th NMOS pipe 117, externally export big electric current, guarantee big driving force.

Reduce the principle of quiescent dissipation for clearer and more definite present embodiment, present embodiment has proposed a kind of concrete implementation of first amplifier 121 and second amplifier 111, it may be noted that, first amplifier 121 here and second amplifier 111 are also used N type amplifier 311 among Fig. 3 and the P type amplifier 321 among Fig. 2 respectively, both differences are the input voltage range difference of work just, certain also amplifier of available other form, here the concrete structure of enumerating can not be considered as limitation of the present invention just for convenience of description.

Introduce first amplifier 121 used in the present embodiment and the composition structure of second amplifier 111 below.

Fig. 7 is the circuit structure diagram of first amplifier 121 in the AB class output-stage circuit shown in Figure 6, the 11 NMOS pipe the 214 and the 3rd bias current sources 200 is formed first source follower, the output of this first source follower is the source electrode 225 of the 11 NMOS pipe 214, one end of the 3rd bias current sources 200 is connected in the source electrode of the 11 NMOS pipe 214, another termination common 100; The 12 NMOS pipe the 215 and the 4th bias current sources 201 constitutes second source follower, the output of this second source follower is the source electrode 224 of the 12 NMOS pipe 215, one end of the 4th bias current sources 201 is connected in the source electrode of the 12 NMOS pipe 215, the drain electrode of another termination common 100, the 11 NMOS pipes 214 and the drain electrode of the 12 NMOS pipe 215 connect voltage source 103 respectively.The grid of the 11 NMOS pipe 214 links to each other with inverting input 221 with the in-phase input end 220 of first amplifier 121 respectively with the grid of the 12 NMOS pipe 215, receive the differential wave of input, this differential wave exports an input that has first differential amplifier circuit of source current mirror load to after first source follower and second source follower are handled, the input pipe of this first differential amplifier circuit is the 13 PMOS pipe the 212 and the 14 a PMOS pipe 213, their grid is as the input of first differential amplifier circuit, link to each other with the source electrode of the 11 NMOS pipe 214 respectively, receive the output signal of first source follower and second source follower with the 12 NMOS pipe 215.The source electrode and the 5th bias current sources 203 of the source electrode of the 13 PMOS pipe 212 and the 14 PMOS pipe 213 are connected in end points 222, and the other end of this 5th bias current sources 203 is connected in voltage source 103.The load of this first differential amplifier circuit is the active electric current mirror that the 15 NMOS pipe the 210 and the 16 NMOS pipe 211 is formed, the input signal that this active electric current mirror receives the 13 PMOS pipe 212 and the 14 PMOS pipe 213 is handled the output that is converted into this first differential amplifier circuit that links to each other with the drain electrode of the 14 PMOS pipe 213 and the output of this active electric current mirror (i.e. the drain electrode of the 16 NMOS pipe 211), the also i.e. single-ended output of the output 223 of first amplifier 121.The drain and gate of the 15 NMOS pipe 210 is connected in end points 226, and link to each other with the grid of the 16 NMOS pipe 211 and the drain electrode of the 13 PMOS pipe 212, the 15 NMOS manages 210 source electrode and the source electrode of the 16 NMOS pipe links to each other with common 100 respectively.

Because what first source follower and second source follower were handled is differential signal, the circuit requirement symmetry is so the electric current that the electric current that the 3rd bias current sources 200 is provided needs with the 4th bias current sources 201 provides equates that we establish this electric current is I ₁

Fig. 8 is the circuit structure diagram of second amplifier 111 in the AB class output-stage circuit shown in Figure 6, the 11 PMOS pipe the 234 and the 6th bias current sources 205 is formed the 3rd source follower, the output of the 3rd source follower is the source electrode 245 of the 11 PMOS pipe 234, one end of the 6th bias current sources 205 is connected in the source electrode of the 11 PMOS pipe 234, another termination voltage source 103; The 12 PMOS pipe the 235 and the 7th bias current sources 206 constitutes the 4th source follower, the output of the 4th source follower is the source electrode 244 of the 12 PMOS pipe 235, one end of the 7th bias current sources 206 is connected in the source electrode of the 12 PMOS pipe 235, the drain electrode of another termination voltage source 103, the 11 PMOS pipes 234 and the drain electrode of the 12 PMOS pipe 235 connect common 100 respectively.The grid of the 11 PMOS pipe 234 links to each other with inverting input 241 with the in-phase input end 240 of second amplifier 111 respectively with the grid of the 12 PMOS pipe 235, receive the differential wave of input, this differential wave exports an input that has second differential amplifier circuit of source current mirror load to after the 3rd source follower and the 4th source follower are handled, the input pipe of this second differential amplifier circuit is the 13 NMOS pipe the 232 and the 14 a NMOS pipe 233, their grid is as the input of second differential amplifier circuit, link to each other with the source electrode of the 11 PMOS pipe 234 respectively, receive the output signal of the 3rd source follower and the 4th source follower with the 12 PMOS pipe 235.The source electrode and the 8th bias current sources 204 of the source electrode of the 13 NMOS pipe 232 and the 14 NMOS pipe 233 are connected in end points 242, and the other end of this 8th bias current sources 204 is connected in common 100.The load of this second differential amplifier circuit is the active electric current mirror that the 15 PMOS pipe the 230 and the 16 PMOS pipe 231 is formed, the input signal that this active electric current mirror receives the 13 NMOS pipe 232 and the 14 NMOS pipe 233 is handled the output that is converted into this second differential amplifier circuit that links to each other with the drain electrode of the 14 NMOS pipe 233 and the output of this active electric current mirror (i.e. the drain electrode of the 16 PMOS pipe 231), the also i.e. single-ended output of the output 243 of second amplifier 111.The drain and gate of the 15 PMOS pipe 230 is connected in end points 246, and link to each other with the grid of the 16 PMOS pipe 231 and the drain electrode of the 13 NMOS pipe 232, the source electrode of the 15 PMOS pipe 230 and the 16 PMOS manage 231 source electrode and link to each other with voltage source 103 respectively.

Because what the 3rd source follower and the 4th source follower were handled is differential signal, the circuit requirement symmetry is so the electric current that the electric current that the 6th bias current sources 205 is provided needs with the 7th bias current sources 206 provides equates that the size that we establish this electric current is I ₂

For the design of the AB class output-stage circuit in the present embodiment, a kind of scheme is designed to the size of current of the 5th bias current sources 203 and the size of current of the 8th bias current sources 204 to equate that still establishing its size of current is I ₀The size of current of the 3rd bias current sources 200, the 4th bias current sources 201, the 5th bias current sources 203 and the 6th bias current sources 205 is designed to equate that establishing its size of current is I ₁

Need to prove, the design of the size of current relation of above-mentioned current source is the convenience in order to illustrate just, the person of ordinary skill in the field knows that in the actual design, the electric current of the 4th NMOS pipe 117 equates with the electric current of the 2nd PMOS pipe 127 of flowing through as long as assurance is flowed through when static.

Circuit in the following surface analysis present embodiment reduces the principle of quiescent current:

For the first half circuit, make drive current bigger, then the breadth length ratio of the 2nd PMOS pipe 127 should be bigger, and the breadth length ratio that we can establish the 2nd PMOS pipe 127 is n times of breadth length ratio of PMOS pipe 126.When circuit was in static state, the electric current in first amplifier in two of first differential amplifier circuit input pipe the 13 PMOS pipe 212 equated with electric current in the 14 PMOS pipe 213, half of the electric current that provides for the 5th bias current sources 203, promptly

The electric current of the 16 NMOS that flows through pipe 211 also is

And the symmetry of first differential amplifier circuit during owing to static state, the voltage of the output 223 of first amplifier 121 (i.e. the drain voltage of the 16 NMOS pipe 211) equals the drain voltage of the 15 NMOS pipe 210, also just equals the grid voltage of the 16 NMOS pipe 211.Because the output 223 of first amplifier 121 links to each other with the grid of NMOS pipe 123, and the source electrode of a NMOS pipe all links to each other with common 100 with the source electrode of the 16 NMOS pipe, so NMOS pipe 123 has identical gate source voltage with the 16 NMOS pipe 211, the current formula that is operated in the saturation region according to metal-oxide-semiconductor as can be known, the ratio of the electric current of the electric current of the NMOS that flows through pipe 123 and the 16 NMOS pipe 211 of flowing through equals the ratio of their breadth length ratio, the electric current I of the NMOS that flows through pipe 123 _N123For:

I_{N 123} = \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

Wherein, (W/L) ₁₂₃Be the breadth length ratio of NMOS pipe 123, (W/L) ₂₁₁It is the breadth length ratio of the 16 NMOS pipe 211.

For effect of the present invention is described intuitively, can analyze the situation that does not have the first feedthrough shunt circuit, the quiescent current of the 2nd PMOS pipe 127 of flowing through this moment

For:

{\overset{\cdot \cdot \cdot}{I}}_{P 127} = n * I_{N 123} = \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2} .

Analyzing now has the first feedthrough shunt circuit, for convenience of description, the breadth length ratio that can establish NMOS pipe 123 be the 2nd NMOS pipe 122 breadth length ratio m doubly, the breadth length ratio of the 4th PMOS pipe 124 be the 3rd PMOS pipe 125 breadth length ratio k doubly.Output voltage made 128 conductings of PMOS switching tube when circuit was static, and the first feedthrough shunt circuit can produce shunt current.The same with NMOS pipe 123, the gate source voltage of the 2nd NMOS pipe 122 equates with the gate source voltage of the 16 NMOS pipe 211, so the electric current I of the 2nd NMOS pipe 122 of flowing through _N122For:

I_{N 122} = \frac{1}{m} I_{N 123} = \frac{1}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

I _N122Behind the current mirror mirror image that the 3rd PMOS pipe the 125 and the 4th PMOS pipe 124 is formed, the electric current I of output in efferent duct the 4th PMOS of this current mirror pipe 124 _P124For:

I_{P 124} = {kI}_{N 122} = \frac{k}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

By the KCL law,, have end points 107

I _N123＝I _P124+I _P126，

Wherein, I _P126Electric current for the PMOS pipe 126 of flowing through.

So, the quiescent current I of the 2nd PMOS pipe 127 of flowing through this moment _P127For:

I_{P 127} = {nI}_{P 126} = n (I_{N 123} - I_{P 124}) = n [\frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2} - \frac{k}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2}]

= \frac{n * (m - k)}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

Relatively

And I _P127Can one find out that under the same terms, the quiescent current when the first feedthrough shunt circuit is arranged is only for traditional scheme (not having the first feedthrough shunt circuit) quiescent current

If m: k=5: 4, then quiescent current can reduce

Stricter comparison is compared with background technology traditional scheme partly, considers all quiescent currents of circuit, still considers the first half circuit, and the electric current in first amplifier is I ₀+ 2I ₁, the electric current in the 2nd PMOS pipe 127 still is

I_{P 127} = \frac{n * (m - k)}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

Its aftercurrent is electric current in the NMOS pipe 123 and the electric current in the 2nd NMOS pipe 122, is respectively

With

So the quiescent current of the first half circuit is:

And the quiescent current of traditional scheme the first half circuit is:

For relatively convenient, but reasonable assumption (this hypothesis can be achieved by technological parameter and the current source parameter that disposes corresponding metal-oxide-semiconductor)

I_{1} = \frac{I_{0}}{2},

m∶k∶n＝5∶4∶20、

\frac{{(W / L)}_{123}}{{(W / L)}_{211}} = 1,

Then can obtain:

Compare I _AlwaysWith The static working current that can find out entire circuit still has significantly and reduces.

The principle of the latter half circuit minimizing quiescent current is the same with the first half circuit, repeats no more here.

In this embodiment, should suitably select the size and the current source current value of metal-oxide-semiconductor, the electric current of the electric current of the 2nd PMOS that flows through when making static state pipe 127 and the 4th NMOS pipe 117 of flowing through equates.

To need to prove, the just convenience in order illustrating of the current value of proportionate relationship, current source of breadth length ratio of value, metal-oxide-semiconductor of m, n, k and the quantitative relation between the current value to be set above, can not be considered as limitation of the present invention.

Embodiment 2:

As shown in Figure 9, present embodiment is compared with embodiment 1, changed biasing circuit 3 into first bias current sources 31, other parts are identical, and this circuit is applicable to that the input voltage range of input 101 only is the promptly satisfied situation about requiring that drives of working range of first amplifier 121.

Analysis according to embodiment 1, the breadth length ratio that can establish the 2nd PMOS pipe 127 equally be PMOS pipe 126 breadth length ratio n doubly, the breadth length ratio of the one NMOS pipe 123 be the 2nd NMOS pipe 122 breadth length ratio m doubly, the breadth length ratio of the 4th PMOS pipe 124 be the 3rd PMOS pipe 125 breadth length ratio k doubly, when so static, the quiescent current I of the 2nd PMOS that flows through pipe 127 _P127For:

I_{P 127} = \frac{n * (m - k)}{m} * \frac{{(W / L)}_{123}}{{(W / L)}_{211}} * \frac{I_{0}}{2},

This moment, the effect of first bias current sources 31 just provided the DC channel of this quiescent current to ground, and the size of its electric current is I _P127Size.

With the situation contrast that does not have the first feedthrough shunt circuit, the circuit in the present embodiment can reduce quiescent dissipation, and this has detailed explanation in embodiment 1, repeat no more here.

Here need that the circuit among embodiment 1 and the embodiment 2 is done a circuit among explanation: the embodiment 1 and have symmetry fully, we when describing with the latter half of symmetric circuit as biasing circuit, certainly also can be with the first half of symmetric circuit as biasing circuit, and the latter half is as first operational amplifier 1 and first output circuit 2, correspond to the situation of embodiment 2 so, the latter half circuit that also can keep the symmetric circuit among the embodiment 1, and the biasing circuit 3 of the first half is replaced with bias current sources, its operation principle is similar to the description among the embodiment 2.

Embodiment 3:

As shown in figure 10, present embodiment is compared with embodiment 1, first switching circuit PNP switching transistor T1 and first resistance R 1 have been replaced to by PMOS switching tube 128, one end of first resistance R 1 links to each other with output 102, the other end links to each other with the base stage of PNP switching tube transistor T 1, the emitter of PNP switching transistor T1 links to each other with the drain electrode of the 4th PMOS pipe 124, and collector electrode links to each other with end points 107 (Section Point); The second switch circuit npn switching transistor T2 and second resistance R 2 have been replaced to by nmos switch pipe 118, one end of second resistance R 2 links to each other with output 102, the other end links to each other with the base stage of NPN switching tube transistor T 2, the emitter of npn switching transistor T2 links to each other with the drain electrode of the 6th NMOS pipe 114, and collector electrode links to each other with end points 105 (the 3rd node).

For convenience of explanation, " switching circuit " that occurs below is the general designation of first switching circuit and second switch circuit, " switching transistor " is the general designation of npn switching transistor T2 and PNP switching transistor T1, " shunting produces circuit " is the general designation that the first shunting generation circuit and second shunting produce circuit, " the feedthrough shunting produces circuit " is that first feedthrough shunting produces circuit and the general designation that produces circuit is shunted in second feedthrough, and explanation herein is applicable to whole specification part.

When circuit is in static state, the voltage of output 102 level that mediates, can make the equal conducting of emitter junction of emitter junction and the npn switching transistor T2 of PNP switching transistor T1, thereby make conducting between the emitter and collector of switching transistor T1 and T2, make static time-division miscarriage give birth to the electric current that circuit produces and can pass through switching circuit, produce the 3rd electric current between circuit and the Section Point (end points 107) and second feedthrough and shunt the 7th electric current between generation circuit and the 3rd node (end points 105) thereby form first feedthrough shunting.

Certainly, in this embodiment, also first switching circuit can be replaced with the PNP switching transistor T1 and first resistance R 1, and the second switch circuit is still used original nmos switch pipe 118; Also the second switch circuit can be replaced with the npn switching transistor T2 and second resistance R 2, and first switching circuit is still used original PMOS switching tube 128.

Illustrated that more than the operation principle of remainder is identical with the description among the embodiment with the operation principle of the switching circuit after the contactor circuit replaces it among the embodiment 1, the principle that reduces quiescent dissipation is also described identical with a kind of embodiment, does not repeat them here.

Equally, in the present embodiment, because the symmetry of circuit, the first half circuit and the latter half circuit are setovered mutually, and all can produce driving force, the first half circuit and the latter half circuit all can be substituted by a bias current sources, and this kind made biasing circuit of current source scheme is identical with the circuit theory described in the embodiment 2, does not repeat them here.

Embodiment 4:

As shown in figure 11, present embodiment is compared with embodiment 1, the concrete composition that shunting is produced circuit changes: it is the current mirror that the 4th PMOS pipe the 124 and the one PMOS pipe 126 is formed that first shunting of the first half circuit produces circuit, the 4th PMOS pipe the 124 and the one PMOS pipe 126 is formed current mirror, produce shunt current.The grid of the 4th PMOS pipe 124 links to each other with the grid of PMOS pipe 126, and source electrode connects voltage source 103, and drain electrode connects first switching circuit; It is the current mirror that the 6th NMOS pipe the 114 and the 3rd NMOS pipe 116 is formed that second shunting of the latter half circuit produces circuit, and the 6th NMOS pipe the 114 and the 3rd NMOS pipe 116 is formed current mirror, produces shunt current.The grid of the 6th NMOS pipe 114 links to each other with the grid of the 3rd NMOS pipe 116, and source electrode connects common 100, and drain electrode connects the second switch circuit.

If the breadth length ratio of the 4th PMOS pipe 124 be PMOS pipe 126 breadth length ratio α doubly, α: n=1 then: 5 with embodiment 1 in m: k: n=5: the effect of 4: 20 minimizing quiescent dissipation is identical, and principle is similar, does not repeat them here.

The operation principle of the latter half circuit is identical with the operation principle of the first half circuit.Certainly, compare, the shunting of the first half can be produced in this embodiment that circuit is done to replace and the latter half keeps the structure among the embodiment 1, the shunting of the latter half can be produced also that circuit is done to replace and the first half keeps the structure of a kind of embodiment with embodiment 1.

Further, the situation described in the also replaceable one-tenth embodiment 3 of the switching circuit in the present embodiment is about to first switching circuit and replaces with the PNP switching transistor T1 and first resistance R 1, and the second switch circuit is still used original nmos switch pipe 118; Also the second switch circuit can be replaced with the npn switching transistor T2 and second resistance R 2, and first switching circuit is still used original PMOS switching tube 128, also first switching circuit and second switch circuit all can be done replacement, the operation principle of the switching circuit after the replacement has a detailed description in embodiment 3, no longer repeats herein.

Have again, in the present embodiment, because the symmetry of circuit, the first half circuit and the latter half circuit are setovered mutually, and all can produce driving force, the first half circuit and the latter half circuit all can be substituted by a bias current sources, and this kind made biasing circuit of current source scheme is identical with the circuit theory described in the embodiment 2, does not repeat them here.

Embodiment 5:

As shown in figure 12, present embodiment is compared with embodiment 1, to shunt the generation circuit and do change: it is the 4th PMOS pipe 124 that first shunting of top circuit produces circuit, the grid of the 4th PMOS pipe 124 links to each other with the output of second amplifier 111, controls the 4th PMOS pipe 124 by the output voltage of second amplifier 111 and produces shunt current.The drain electrode of the 4th PMOS pipe 124 links to each other with first switching circuit, and source electrode connects voltage source 103; The second shunting generation circuit of the latter half circuit is that the grid of the 6th NMOS pipe 114, the six NMOS pipe 114 links to each other with first amplifier 121, controls the 6th NMOS pipe 114 by the output voltage of first amplifier 121 and produces shunt current.The drain electrode of the 6th NMOS pipe 114 links to each other with the second switch circuit, and source electrode connects common 100.

For the first half circuit, illustrate that mainly first shunting produces circuit and how to produce shunt current, the operation principle of other parts is identical with previous embodiment.Be as shown in Figure 7 circuit still with first amplifier 121, second amplifier 111 is an example for circuit as shown in Figure 8, and design is identical among the relation of the bias current sources size of current in first amplifier 121 and second amplifier 111 and the embodiment 1, and the related description that concerns about the size of current of each bias current sources among the embodiment 1 still is applicable to present embodiment.

The operation principle of describing with embodiment 1 is similar, when circuit is in static state, the electric current of the 13 NMOS that flows through in second amplifier 111 as shown in Figure 8 pipe 232 and the 14 NMOS that flows through manage 233 electric current and equate, are half of electric current of the 8th bias current sources 204, promptly

The electric current of the 16 PMOS pipe 231 also is so flow through

Because the symmetry of circuit when static, the voltage of the output 243 of second amplifier 111 (i.e. the drain voltage of the 16 PMOS pipe 231) equals the drain voltage of the 15 PMOS pipe 230, and the drain voltage of the 15 PMOS pipe 230 equals the grid voltage of the 16 PMOS pipe 231, so the voltage of the output 243 of second amplifier 111 equals the grid voltage of the 16 PMOS pipe 231, according to shown in Figure 12, because the grid of the 4th PMOS pipe 124 links to each other with the output 243 of second amplifier 111, so the grid voltage of the 4th PMOS pipe 124 equates with the grid voltage of the 16 PMOS pipe 231, again because the source electrode of the source electrode of the 4th PMOS pipe 124 and the 16 PMOS pipe 231 all connects voltage source 103, so the gate source voltage of the 4th PMOS pipe 124 equates with the gate source voltage of the 16 PMOS pipe 231, according to the current formula of metal-oxide-semiconductor as can be known, the electric current of the 4th PMOS that flows through pipe 124 and the ratio of the electric current of the 16 PMOS pipe 231 of flowing through equal the ratio of breadth length ratio with the breadth length ratio of the 16 PMOS pipe 231 of the 4th PMOS pipe 124.

If the breadth length ratio of the 4th PMOS pipe 124 is k ' with the ratio of the breadth length ratio of the 16 PMOS pipe 231,123 breadth length ratio is m ' with the ratio of 211 breadth length ratio, 127 breadth length ratio and 126 breadth length ratio are n ', m ': k ': n '=m: k: n=5 then: the principle and the effect of 4: 20 minimizing static working current are the same, this point had been described in detail in embodiment 1, did not repeat them here.In addition, the principle of this circuit other parts minimizing static working current is similar to the above, and those skilled in the art can learn that the other parts of this circuit reduce the principle of static working current, do not repeat them here according to foregoing description.

Need to prove, above m ', n ', the setting of the ratio of k ' is the convenience in order to describe just, should be appreciated that when circuit is in static state, shunting produces circuit and has produced shunt current, and the electric current that change-over circuit (the change-over circuit here is the general designation of first change-over circuit and second change-over circuit, and first change-over circuit is a NMOS pipe 123) produces shunted the effect of minimizing quiescent dissipation in the time of just can being created in static state.

In addition, in the present embodiment, the situation among the also replaceable one-tenth embodiment 3 of switching circuit can all be done replacement by two switching circuits, also can only replace one of them, and another remains unchanged, and that describes among its principle and the embodiment 3 is identical.

Embodiment 6:

As shown in figure 13, present embodiment is compared with embodiment 1, to shunt the generation circuit replaces: first shunting of the first half circuit produces circuit and replaces with the first shunt current source 207, and an end in this first shunt current source 207 links to each other with voltage source 103, and the other end links to each other with first switching circuit; Second shunting of the latter half circuit produces circuit and replaces with the second shunt current source 208, and an end in this second shunt current source 208 links to each other with earth terminal, and the other end links to each other with the second switch circuit.

Be as shown in Figure 7 circuit still with first amplifier 121, second amplifier 111 is an example for circuit as shown in Figure 8, and design is identical among the relation of the bias current sources size of current in first amplifier 121 and second amplifier 111 and the embodiment 1, and the related description that concerns about the size of current of each bias current sources among the embodiment 1 still is applicable to present embodiment.Electric current when the first shunt current source is

The time, it is similar that its shunting action and principle and embodiment 1 describe, in this no longer repeat specification.

The operation principle of the latter half circuit is identical with the operation principle of the first half, no longer is repeated in this description.

Need to prove that in this enforcement was fallen, the shunting of first in the first half circuit generation circuit also can adopt the structure among the embodiment 1, and the second shunting generation circuit of the latter half circuit still adopts the second shunt current source 208; Perhaps first of the first half circuit shunting source generating circuit still adopts the first shunt current source 207, and second shunting of the latter half circuit produces the structure among the circuit employing embodiment 1.More than the operation principle of two kinds of form circuit among the embodiment description is arranged all in front, do not repeat them here.

In addition, in this embodiment, when the input voltage range of circuit input end 101 only is that the working range of first amplifier 121 promptly satisfies and drives when requiring, replaceable one-tenth one bias current sources of the latter half circuit of this embodiment, the first half circuit is constant, its operation principle is similar to the description among the embodiment 2, does not repeat them here.By the symmetry of circuit as can be known, also the first half circuit among this embodiment can be replaced to a bias current sources, the latter half circuit is constant.

Have again, in this embodiment, first switching circuit can be replaced with the PNP switching transistor T1 and first resistance R 1, and the second switch circuit is still used original nmos switch pipe 118; Also the second switch circuit can be replaced with the npn switching transistor T2 and second resistance R 2, and first switching circuit is still used original PMOS switching tube 128, also first switching circuit and second switch circuit all can be done replacement, the operation principle of the switching circuit after the replacement has a detailed description in embodiment 3, no longer repeats herein.

Also have, in this embodiment, the first shunting generation circuit also can adopt the mode among the embodiment 4, other remains unchanged, perhaps second shunting produces the mode among the circuit employing embodiment 4, and other parts remain unchanged, and its operation principle that changes part has a detailed description in embodiment 4, no longer repeats at this.

Embodiment 7:

The embodiment of the invention also provides a kind of electric signal processing method, as shown in figure 14.This method comprises the steps:

S1: first input voltage signal and second input signal are carried out producing the difference processing result after difference is amplified;

S2: second electric current that produces the Section Point of flowing through according to described difference processing result;

S3: when static state, produce the 3rd electric current of the described Section Point of flowing through, and produce the 4th electric current of the described Section Point of flowing through, make described second electric current equal described the 3rd electric current and described the 4th electric current sum according to described second electric current and described the 3rd electric current;

The S3 step specifically comprises:

S31: by first voltage control, the described first voltage cut-out circuit turn-on when static state, the electric current that makes introducing produces described the 3rd electric current by the switching circuit of the conducting described Section Point of flowing through;

S32: produce the 4th electric current of the described Section Point of flowing through according to described second electric current and described the 3rd electric current, the size of described second electric current is the size of described the 3rd electric current and the big or small sum of described the 4th electric current;

S4: described the 4th electric current is converted into first electric current of the first node of flowing through, and produces described first voltage at described first node, described first electric current is greater than described the 4th electric current, and described first voltage is described second input signal.

In the present embodiment, produced the 3rd electric current during owing to static state, in order to second electric current is shunted, so when static, only carry out mirror image processing, and directly second electric current carried out mirror image processing and compare to shunting the 4th electric current that the back produces, reduce quiescent current, thereby reduced quiescent dissipation.

More than be some embodiment for the explanation technical solution of the present invention; understanding under the prerequisite of technical solution of the present invention; the those of ordinary skill in described field can obtain the execution mode that other is equal to according to the foregoing description, and these execution modes that are equal to also are encompassed in protection scope of the present invention.

Claims

1. An output stage circuit, characterized in that it comprises:

A first operational amplifier, configured to receive a first input signal and a second input signal, perform differential amplification processing on the first input signal and the second input signal, and output a differential processing result;

first node;

The first output circuit, connected between the first node and the output terminal of the first operational amplifier, is used to receive the differential processing result of the first operational amplifier, and perform the differential processing according to the differential processing of the first operational amplifier resulting in a first current flowing through the first node;

a bias circuit, connected to the first node, for forming a first voltage at the first node based on the first current, and based on the first current at a static state for the first operational amplifier and the first A circuit composed of an output circuit is statically biased, wherein the first voltage is a second input signal of the first operational amplifier;

The first output circuit includes:

second node;

The first conversion circuit, connected between the output terminal of the first operational amplifier and the second node, is used to receive the differential processing result of the first operational amplifier, and perform the differential processing according to the differential processing of the first operational amplifier. As a result, adjusting a second current between the first switching circuit and the second node;

a first feedthrough shunt circuit, connected to the second node, and configured to form a third current between the first feedthrough shunt circuit and the second node when the output stage circuit is in a static state;

A first output processing circuit, connected between the first node and the second node, for converting the fourth current between the first output processing circuit and the second node to flow through the the first current at a first node, the first current being greater than the fourth current;

The second current is the sum of the third current and the fourth current.

2. The output stage circuit according to claim 1, characterized in that, the output stage circuit further comprises a first common terminal, the first conversion circuit is a first MOS transistor, and the gate of the first MOS transistor It is connected to the output terminal of the first operational amplifier, the source is connected to the first common terminal, and the drain is connected to the second node.

3. The output stage circuit according to claim 1, characterized in that, the output stage circuit further comprises a first common terminal, the first switching circuit is a first MOS transistor and a cascode MOS transistor, the The gate of the first MOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the first common terminal, and the drain is connected to the source of the cascode MOS transistor; The gate of the gate MOS transistor is connected to a bias voltage, and the drain is connected to the second node.

4. The output stage circuit according to claim 2 or 3, wherein the first operational amplifier includes a first differential pair with an active current mirror load, and the output terminal of the first operational amplifier is connected to The active current mirror load of the first differential pair is connected, and the channel type of the first MOS transistor is the same as the channel type of the MOS transistor constituting the active current mirror load of the first differential pair.

5. The output stage circuit according to claim 1, wherein the first output processing circuit is a first active current mirror, and the current input terminal of the first active current mirror is connected to the second node The current output end of the first active current mirror is connected to the first node, the first active current mirror receives the fourth current, and the fourth current flows through the the first current at the first node.

6. The output stage circuit according to claim 1, wherein the first feedthrough shunt circuit comprises:

A first switch circuit, the first switch circuit includes a first control terminal, a second terminal and a third terminal, the first control terminal is connected to the first node, and the second terminal is connected to the second node connected;

A first shunt generation circuit, the first shunt generation circuit is connected to the third terminal; the signal of the first node controls the first switch circuit, so that the first switch circuit is in the state of the output stage circuit In static state, the connection between the second terminal and the third terminal is conducted, and the current generated by the first shunt generating circuit passes through the first switch circuit to form the third current.

7. The output stage circuit according to claim 6, wherein the first switch circuit is a first MOS switch, the gate of the first MOS switch is the first control terminal, and the gate of the first MOS switch is connected to the The first node is connected, and the source and drain of the first MOS switch tube are respectively the third terminal and the second terminal, which are respectively connected to the first shunt generation circuit and the second node.

8. The output stage circuit according to claim 6, wherein the first switch circuit comprises a first resistor and a first transistor, one end of the first resistor is the first control end, and the The first node is connected, the other end of the first resistor is connected to the base of the first transistor, the emitter and the collector of the first transistor are respectively the third end and the second end, respectively It is connected with the first shunt generation circuit and the second node.

9. The output stage circuit according to claim 6, wherein the first shunt generating circuit comprises:

The second MOS transistor is used to adjust the current flowing through the second MOS transistor according to the differential processing result of the first operational amplifier, and the gate of the second MOS transistor is connected to the output terminal of the first operational amplifier. , the source is connected to the first common terminal;

The second active current mirror, the current input terminal of the second active current mirror is connected to the drain of the second MOS transistor, and receives the current of the second MOS transistor, and the current input terminal of the second active current mirror is The output terminal is connected with the third terminal.

10. The output stage circuit according to claim 6, wherein the first output processing circuit is a first active current mirror, and the first active current mirror includes a first input MOS transistor and a first output MOS transistor, the gate and drain of the first input MOS transistor are connected to the current input end of the first active current mirror with the gate of the first output MOS transistor, the first input MOS transistor The source and the source of the first output MOS transistor are connected to the second common terminal, the drain of the first output MOS transistor is the current output terminal of the first active current mirror, and the first active current The current input terminal of the mirror is connected to the second node, the current output terminal of the first active current mirror is connected to the first node, the first active current mirror receives the fourth current, and the The fourth current is mirrored to obtain the first current flowing through the first node.

11. The output stage circuit as claimed in claim 10, characterized in that,

The first shunt generation circuit is a second active current mirror, the second active current mirror includes the first input MOS transistor and the second output MOS transistor, the gate of the second output MOS transistor is connected to the The gate of the first input MOS transistor is connected, the source of the second output MOS transistor is connected to the second common terminal, and the drain of the second output MOS transistor is connected to the third terminal.

12. The output stage circuit according to claim 6, characterized in that, the output stage circuit further comprises a second common terminal,

The first shunt generating circuit is a first shunt current source, one end of the first shunt current source is connected to the second common end, and the other end is connected to the third end, and the current generated by the first shunt current source The third current is formed by passing through the first switch circuit when the second terminal and the third terminal of the first switch circuit are turned on.

13. The output stage circuit according to claim 1, characterized in that, the output stage circuit further comprises a first common terminal, the bias circuit is a bias current source, and one end of the bias current source is connected to the The first node, the other terminal is connected to the first common terminal, and the magnitude of the bias current source is the first current when the output stage circuit is in a static state.

14. The output stage circuit according to claim 1, wherein the bias circuit comprises:

A second operational amplifier, where the second operational amplifier receives the first input signal and the second input signal, performs differential amplification processing on the first input signal and the second input signal, and outputs a differential processing structure;

a second output circuit, configured to receive a differential processing result of the second operational amplifier, and generate a fifth current flowing through the first node according to the differential processing result of the second operational amplifier;

When the output stage circuit is in a static state, the fifth current is equal to the first current.

15. The output stage circuit according to claim 14, wherein the second output circuit comprises:

third node;

The second conversion circuit is connected between the second operational amplifier and the third node, and is used for receiving the differential processing result of the second operational amplifier, and adjusting the differential processing result of the second operational amplifier according to the differential processing result of the second operational amplifier. a sixth current between the second conversion circuit and the third node;

The second output processing circuit, connected between the first node and the third node, is used to convert the seventh current between the second output processing circuit and the third node to flow through the said fifth current at the first node;

16. The output stage circuit according to claim 15, wherein the second output circuit further comprises a second feedthrough shunt circuit, the second feedthrough shunt circuit is connected to the third node for An eighth current between the second feed-through shunt circuit and the third node is formed in a static state, and the sixth current is a sum of the seventh current and the eighth current.

17. The output stage circuit according to claim 6, wherein said bias circuit comprises:

A second operational amplifier, configured to receive the first input signal and the second input signal, perform differential amplification processing on the first input signal and the second input signal, and output a differential processing result; a second output circuit , connected between the first node and the output terminal of the second operational amplifier, used to receive the differential processing result of the second operational amplifier, and generate the fifth current of the first node;

The second output circuit includes:

third node;

The second conversion circuit, connected between the output terminal of the second operational amplifier and the third node, is used to receive the differential processing result of the second operational amplifier, and perform the differential processing according to the differential processing of the second operational amplifier. adjusting a sixth current between the second conversion circuit and the third node as a result;

a second feedthrough shunt circuit, connected to the third node, and used to form an eighth current between the second feedthrough shunt circuit and the third node in static state;

The sixth current is the sum of the seventh current and the eighth current. .

18. The output stage circuit according to claim 17, wherein the second feedthrough shunt circuit comprises:

A second switch circuit, the second switch circuit includes a fourth control terminal, a fifth terminal and a sixth terminal, the fourth control terminal is connected to the first node, and the fifth terminal is connected to the third node connected;

The second shunt generation circuit, the second shunt generation circuit is connected to the sixth end; the first power-saving signal controls the second switch circuit, so that the second switch circuit is in the output stage circuit In static state, the fifth terminal and the sixth terminal are conducted, and the current generated by the second shunt generating circuit passes through the second switch circuit to form the eighth current.

19. The output stage circuit according to claim 18, wherein the first shunt generating circuit is a first shunt MOS transistor, the gate of the first shunt MOS transistor is connected to the output of the second operational amplifier terminal, the drain is connected to the third terminal of the first switch circuit, the source is connected to the second common terminal, and the first shunt MOS transistor is used to connect between the second terminal and the third terminal of the first switch circuit Receive the differential processing result of the second operational amplifier when the interval is turned on, and adjust the current flowing through the first shunt MOS tube according to the differential processing result of the second operational amplifier, and the current passes through the first switch circuit , forming the third current.

20. The output stage circuit according to claim 18 or 19, wherein the second shunt generation circuit is a second shunt MOS transistor, the gate of the second shunt MOS transistor is connected to the first operational amplifier connected to the output terminal of the second switch circuit, the drain is connected to the sixth terminal of the second switch circuit, and the source is connected to the first common terminal, and the second shunt MOS transistor is used to connect the fifth terminal and the sixth terminal of the second switch circuit Receive the differential processing result of the first operational amplifier when the terminals are turned on, and adjust the current flowing through the second shunt MOS tube according to the differential processing result of the first operational amplifier, which flows through the second The current of the shunt MOS transistor passes through the second switch circuit to form the seventh current.

21. A power amplifier circuit, including an output stage circuit, characterized in that the output stage circuit includes:

first node;

The first output circuit includes:

second node;

The second current is the sum of the third current and the fourth current.

22. The power amplifying circuit according to claim 21, wherein the first output processing circuit is a first active current mirror, and the current input terminal of the first active current mirror is connected to the second node The current output end of the first active current mirror is connected to the first node, the first active current mirror receives the fourth current, and the fourth current flows through the the first current at the first node.

23. The power amplifying circuit according to claim 21, wherein the first feedthrough shunt circuit comprises:

24. The power amplifying circuit according to claim 21, wherein the output stage circuit further comprises a first common terminal, the bias circuit is a bias current source, and one end of the bias current source is connected to the The first node, the other terminal is connected to the first common terminal, and the magnitude of the bias current source is the first current when the output stage circuit is in a static state.

25. The power amplifying circuit according to claim 21, said biasing circuit comprising:

26. The power amplifying circuit according to claim 25, wherein the second output circuit comprises:

third node;

27. The power amplifying circuit according to claim 26, wherein the second output circuit further comprises a second feedthrough shunt circuit, and the second feedthrough shunt circuit is connected to the third node for An eighth current between the second feed-through shunt circuit and the third node is formed in a static state, and the sixth current is a sum of the seventh current and the eighth current.

28. A method for processing electrical signals, comprising the following steps:

The first operational amplifier differentially amplifies the first input voltage signal and the second input signal to generate a differential processing result;

the first conversion circuit generates a second current flowing through the second node according to the differential processing result;

The first feed-through shunt circuit generates a third current flowing through the second node in static state, and the first feed-through shunt circuit generates a third current flowing through the second node according to the second current and the third current. four currents such that said second current is equal to the sum of said third current and said fourth current;

The first output processing circuit converts the fourth current into a first current flowing through the first node, and generates a first voltage at the first node, the first current is greater than the fourth current, and the first current is greater than the fourth current. A voltage is the second input signal, wherein the point where the first output processing circuit is connected to the output end of the output stage circuit is the first node.

29. The method for processing electrical signals according to claim 28, wherein the step of converting the fourth current into the first current flowing through the first node is specifically:

The fourth current is mirrored by a current mirror to obtain the first current.

30. The method for processing electrical signals according to claim 28, wherein the step of generating a third current flowing through the second node in static state is specifically:

Controlled by the first voltage, the first voltage controls the conduction of the switch circuit in static state, so that the introduced current flows through the second node through the conduction switch circuit to generate the third current.