CN109802641B - Amplifier with wider input voltage range - Google Patents
Amplifier with wider input voltage range Download PDFInfo
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- CN109802641B CN109802641B CN201910069111.0A CN201910069111A CN109802641B CN 109802641 B CN109802641 B CN 109802641B CN 201910069111 A CN201910069111 A CN 201910069111A CN 109802641 B CN109802641 B CN 109802641B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses an amplifier with wider input voltage range, comprising: a control module for converting the amplifier on permission signal comp_en into a complementary amplifier enable signal en_n and an amplifier enable signal EN; a bias voltage module for converting the reference voltage VREFPGM into a bias voltage VBIAS required for the operation of the amplifier under the control of a complementary amplifier enable signal en_n; the differential amplifying module is used for amplifying the difference value of the input differential signals VN and VP under the control of the bias voltage VBIAS; the invention solves the problems of input range and gain simultaneously by using a high-voltage tube and a high-voltage Native tube which are connected in parallel as an input pair tube of an amplifier.
Description
Technical Field
The present invention relates to an amplifier, and more particularly, to an amplifier having a wide input voltage range.
Background
The existing differential voltage amplifier for an embedded flash (eFlash) includes a control module 40, a bias voltage module 10, a differential amplification module 20, and an output amplification module 30. Wherein the control module 40 is composed of direction switches I61 and I62 for converting the amplifier on enable signal comp_en into the complementary amplifier enable signal en_n and the amplifier enable signal EN; the bias voltage module 10 consists of a PMOS tube M14, a PMOS tube PM0, an NMOS tube M16 and an NMOS tube NM0, and is used for converting a reference voltage VREFPGM into a bias voltage VBIAS required by the operation of the amplifier with wider input voltage under the control of a complementary amplifier enabling signal EN_N; the differential amplification module 20 is composed of a PMOS tube M19, a PMOS tube PM1, an NMOS amplification tube NM3, an NMOS tube M0 and a first lower bias tube NM1, and is configured to amplify the difference value of the input differential signals VN and VP under the control of the bias voltage VBIAS; the output amplifying module 30 is composed of a PMOS transistor M20, a PMOS transistor M18, and a second lower bias NMOS transistor NM2, and is configured to further amplify the amplified differential signal under the control of the amplifier enable signal EN to obtain an output signal fb_n.
The amplifier on permission signal comp_en is connected to the input end of the inverter I61, the output end of the inverter I61, that is, the complementary amplifier enable signal en_n is connected to the input end of the inverter I62, the gate of the PMOS transistor M14 and the gate of the NMOS transistor NM0, and the output end of the inverter I62, that is, the amplifier enable signal EN is connected to the gate of the PMOS transistor M18; the drain electrode of the PMOS tube M14 is connected to the source electrode of the PMOS tube PM0, the substrate of the PMOS tube PM0 is connected with a power supply Vdd, the grid electrode of the PMOS tube PM0 is connected with a reference voltage VREFPGM, the drain electrode of the PMOS tube PM0 is connected with the drain electrode and the grid electrode of the NMOS tube M16, the drain electrode of the NMOS tube NM0, the grid electrode of the first lower bias NMOS tube NM1 and the grid electrode of the second lower bias NMOS tube NM2 to form a bias voltage VBIAS node, and the source electrodes of the NMOS tubes M16 and NM0 and the substrate are grounded gnd; the sources and the substrates of the PMOS tubes M14, M19, PM1, M20 and M18 are connected with a power supply Vdd, the PMOS tube M19 and the PMOS tube PM1 form a mirror constant current source, the drain electrode and the grid electrode of the PMOS tube M19 are connected with the grid electrode of the PMOS tube PM1 and the drain electrode of the NMOS tube NM3 to form a node B, the inverted differential voltage VN is connected to the grid electrode of the NMOS tube NM3, the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube M0 and the grid electrode of the PMOS tube M20 to form a node C, the drain electrode of the first lower bias NMOS tube NM1 is connected with the source electrode of the NMOS tube NM3 and the source electrode of the NMOS tube M0 to form a node A, the same-phase differential voltage VP is connected to the grid electrode of the NMOS tube M0, and the substrates of the NMOS tube NM3 and the NMOS tube M0 are grounded to gnd; the drain electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18 and the drain electrode of the second lower bias NMOS tube to form an output signal FB_N node; the source electrodes of the first lower bias NMOS transistor NM1 and the second lower bias NMOS transistor and the substrate are grounded gnd.
Table 1 AC results under different PVT for conventional amplifier
Table 1 above is the AC results under different PVT for a conventional amplifier. It can be seen that the prior art amplifier has large gain fluctuations at different PVT (Precess Voltage Temperature) process angles, and that the prior art has a gain fluctuation of e.g. ss/vdd=1.7V/vn=0.5-0.6V/-40 at some process angles O C and ss/vdd=1.3V/vn=0.5-0.6V/-40 O C、sf/Vdd＝1.7V/Vn＝0.5-0.6V/-40 O C、sf/Vdd＝1.3V/Vn＝0.5-0.6V/-40 O And C, the working is not carried out.
Typically, a large number of charge pumps and high voltages are used within an eFlash circuit. In order to detect these high voltages, a comparator and a reference voltage are required. Since a reference voltage VREF of 0.8v or less is more easily generated by the bandgap under a power supply voltage of 1.5 v.
The input of the comparator is at one end the reference voltage VREF, and the other end is the output HV of the charge pump. Considering BV, the input pair of comparators must choose a high voltage tolerant tube, such as hv_nmos or hv_native.
However, if the high voltage tube hv_nmos is selected, the threshold voltage under extreme conditions is relatively high. Under such conditions, an input voltage around 0.8v has entered the subthreshold region, resulting in low gain and even no operation; if a high-voltage Native tube is selected as the input pair tube, the high-voltage Native tube has the characteristic of high-voltage resistance and can be used as the high-voltage input pair tube, but because the VT of the high-voltage Native tube is low, the input voltage near 0.8v already makes the high-voltage Native tube enter a linear region, and the Vt of the Native tube is inaccurate, so that the mismatch is poor, and the high-voltage Native tube is not suitable for being used as the input pair tube of the comparator.
Therefore, the invention aims to select the high-voltage tube and the high-voltage Native tube which are connected in parallel to be used as the input pair tubes of the amplifier so as to solve the problems of input range and gain.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an amplifier with a wider input voltage range, which is used as an input pair tube of the amplifier by utilizing a high-voltage tube and a high-voltage Native tube which are connected in parallel, and simultaneously solves the problems of the input range and the gain.
To achieve the above and other objects, the present invention provides an amplifier having a wide input voltage range, comprising:
a control module for converting the amplifier on permission signal comp_en into a complementary amplifier enable signal en_n and an amplifier enable signal EN;
a bias voltage module for converting the reference voltage VREFPGM into a bias voltage VBIAS required for the operation of the amplifier under the control of a complementary amplifier enable signal en_n;
the differential amplifying module is used for amplifying the difference value of the input differential signals VN and VP under the control of the bias voltage VBIAS;
and the output amplifying module is used for further amplifying the amplified differential signal under the control of the amplifier enabling signal EN to obtain an output signal FB_N.
Preferably, the control module includes an inverter I61 and an inverter I62.
Preferably, the amplifier on permission signal comp_en is connected to the input terminal of the inverter I61, the output terminal of the inverter I61, that is, the complementary amplifier enable signal en_n is connected to the input terminal of the inverter I62 and the bias voltage module, and the output terminal of the inverter I62, that is, the amplifier enable signal EN is connected to the output amplifying module.
Preferably, the bias voltage module comprises a PMOS tube M14, a PMOS tube PM0, an NMOS tube M16 and an NMOS tube NM0.
Preferably, the gate of the PMOS transistor M14 is connected to the enable signal en_n of the complementary amplifier, the drain is connected to the source of the PMOS transistor PM0, the source and the substrate are connected to the power supply, the substrate of the PMOS transistor PM0 is connected to the power supply Vdd, the gate is connected to the reference voltage VREFPGM, the drain forms a bias voltage VBIAS node with the drain and the gate of the NMOS transistor M16, the drain of the NMOS transistor NM0, and the differential amplifying module, the source and the substrate of the NMOS transistors M16 and NM0 are grounded gnd, and the gate of the NMOS transistor NM0 is connected to the enable signal en_n of the complementary amplifier.
Preferably, the differential amplification module uses a high voltage tube and a high voltage primary tube in parallel as input pair tubes of the amplifier.
Preferably, the differential amplification module includes a PMOS transistor M19, a PMOS transistor PM1, an NMOS amplifier transistor NM3, an NMOS transistor M0, an NMOS transistor M1, an NMOS transistor N2, and a first lower bias transistor NM1.
Preferably, the PMOS transistor M19 and the PMOS transistor PM1 form a mirror constant current source, the source and the substrate of the PMOS transistor M19 are connected to the power supply Vdd, the drain and the gate of the PMOS transistor M19 are connected to the gate of the PMOS transistor PM1, the drain of the NMOS transistor NM3, and the drain of the NMOS transistor M1 to form a node B, the inverted differential voltage VN is connected to the gate of the NMOS transistor NM3, the gate of the NMOS transistor M1, the drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor M0, the drain of the NMOS transistor N2, and the output amplification module to form a node C, the drain of the first lower bias NMOS transistor NM1 is connected to the source of the NMOS transistor NM3, the source of the NMOS transistor M1, the source of the NMOS transistor M0, and the source of the NMOS transistor N2 to form a node a, the in-phase differential voltage VP is connected to the gate of the NMOS transistor M0, the substrate of the NMOS transistor M3, the substrate of the NMOS transistor M0, and the substrate of the NMOS transistor N2 to ground gnd, and the first lower bias transistor NM1 gate is connected to the node ias.
Preferably, the output amplification module includes a PMOS transistor M20, a PMOS transistor M18, and a second lower bias NMOS transistor NM2.
Preferably, the gate of the PMOS transistor M20 is connected to the node C, the drain of the PMOS transistor M20 is connected to the drain of the PMOS transistor M18 and the drain of the second lower bias NMOS transistor to form an output signal fb_n node, the source and the substrate of the second lower bias NMOS transistor NM2 are grounded gnd, the gate of the PMOS transistor M18 is connected to the amplifier enable signal EN, and the source and the substrate are connected to a power supply.
Compared with the prior art, the amplifier with wider input voltage range is characterized in that the high-voltage tube and the high-voltage Native tube are connected in parallel to serve as input pair tubes of the amplifier, and meanwhile, the problems of input range and gain are solved.
Drawings
FIG. 1 is a schematic diagram of a prior art differential voltage amplifier for an embedded flash (eFlash);
fig. 2 is a system configuration diagram of an amplifier with a wide input voltage range according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
Fig. 2 is a system configuration diagram of an amplifier with a wide input voltage range according to the present invention. As shown in fig. 2, an amplifier with a wide input voltage range according to the present invention includes: a control module 10, a bias voltage module 20, a differential amplification module 30, and an output amplification module 40.
Wherein the control module 10 is composed of an inverter I61 and an inverter I62 for converting the amplifier on permission signal comp_en into a complementary amplifier enable signal en_n and an amplifier enable signal EN; the bias voltage module 20 is composed of a PMOS tube M14, a PMOS tube PM0, an NMOS tube M16 and an NMOS tube NM0, and is used for converting the reference voltage VREFPGM into the bias voltage VBIAS required by the operation of the amplifier with wider input voltage under the control of the enable signal EN_N of the complementary amplifier; the differential amplification module 30 is composed of a PMOS tube M19, a PMOS tube PM1, an NMOS amplification tube NM3, an NMOS tube M0, an NMOS Native tube (Native tube) M1, an NMOS Native tube (Native tube) N2, and a first lower bias tube NM1, and is configured to amplify a difference value between the input differential signals VN and VP under the control of the bias voltage VBIAS; the output amplifying module 40 is composed of a PMOS transistor M20, a PMOS transistor M18, and a second lower bias NMOS transistor NM2, and is configured to further amplify the amplified differential signal under the control of the amplifier enable signal EN to obtain an output signal fb_n.
The amplifier on permission signal comp_en is connected to the input end of the inverter I61, the output end of the inverter I61, that is, the complementary amplifier enable signal en_n is connected to the input end of the inverter I62, the gate of the PMOS transistor M14 and the gate of the NMOS transistor NM0, and the output end of the inverter I62, that is, the amplifier enable signal EN is connected to the gate of the PMOS transistor M18; the drain electrode of the PMOS tube M14 is connected to the source electrode of the PMOS tube PM0, the substrate of the PMOS tube PM0 is connected with a power supply Vdd, the grid electrode of the PMOS tube PM0 is connected with a reference voltage VREFPGM, the drain electrode of the PMOS tube PM0 is connected with the drain electrode and the grid electrode of the NMOS tube M16, the drain electrode of the NMOS tube NM0, the grid electrode of the first lower bias NMOS tube NM1 and the grid electrode of the second lower bias NMOS tube NM2 to form a bias voltage VBIAS node, and the source electrodes of the NMOS tubes M16 and NM0 and the substrate are grounded gnd; the sources and the substrates of the PMOS pipes M14, M19, PM1, M20 and M18 are connected with a power supply Vdd, the PMOS pipe M19 and the PMOS pipe PM1 form a mirror constant current source, the drain and the grid of the PMOS pipe M19 are connected with the grid of the PMOS pipe PM1, the drain of the NMOS pipe NM3 and the drain of the NMOS pipe (Native pipe) M1 to form a node B, the inverted differential voltage VN is connected to the grid of the NMOS pipe NM3 and the grid of the NMOS pipe (Native pipe) M1, the drain of the PMOS pipe PM1 is connected with the drain of the NMOS pipe M0, the drain of the NMOS pipe (Native pipe) N2 and the grid of the PMOS pipe M20 to form a node C, and the drain of the first lower bias NMOS pipe NM1 is connected with the source of the NMOS pipe NM3, the source of the NMOS pipe (Native pipe) M1, the source of the NMOS pipe M0 and the source of the NMOS pipe (Native pipe) N2 to form a node A, the gate of the NMOS pipe M0, the gate of the NMOS pipe (Native pipe) N2, the differential voltage VP is connected to the grid of the NMOS pipe N2, the drain of the NMOS pipe (Native pipe) N2, and the Native pipe (Native pipe) M2; the drain electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18 and the drain electrode of the second lower bias NMOS tube to form an output signal FB_N node; the source electrodes of the first lower bias NMOS transistor NM1 and the second lower bias NMOS transistor and the substrate are grounded gnd.
From Table 1, the prior art has large gain fluctuation at different PVT (Precess Voltage Temperature) process angles, the average value is 49.88dB, and the deviation is only-24.3/+16.7 dB; table 2 shows the AC simulation results for different PVT of the improved amplifier according to the invention:
table 2 AC simulation results under different PVT of the post-amplifier improvement
From the simulation data list of Table 2, after improvement, the invention has stable gain under different PVT (Precess Voltage Temperature) process angles, the average value is 60.83dB, and the deviation is only-6.5/+2.9 dB, which is obviously superior to the prior art. While transient simulation works at different PVT (Precess Voltage Temperature) process corners, the prior art works at some process corners such as ss/vdd=1.7V/vn=0.5-0.6V/-40 O C and ss/vdd=1.3V/vn=0.5-0.6V/-40 O C、sf/Vdd＝1.7V/Vn＝0.5-0.6V/-40 O C、sf/Vdd＝1.3V/Vn＝0.5-0.6V/-40 O C will not work, the invention is also obviously superior to the prior art.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.
Claims (5)
1. An amplifier having a wide input voltage range, comprising:
a control module for converting the amplifier on permission signal comp_en into a complementary amplifier enable signal en_n and an amplifier enable signal EN;
a bias voltage module for converting the reference voltage VREFPGM into a bias voltage VBIAS required for the operation of the amplifier under the control of a complementary amplifier enable signal en_n;
the differential amplifying module is used for amplifying the difference value of the input differential signals VN and VP under the control of the bias voltage VBIAS;
the output amplifying module is used for further amplifying the amplified differential signal under the control of the amplifier enabling signal EN to obtain an output signal FB_N;
the bias voltage module comprises a PMOS tube M14, a PMOS tube PM0, an NMOS tube M16 and an NMOS tube NM0, wherein the grid electrode of the PMOS tube M14 is connected with the enable signal EN_N of the complementary amplifier, the drain electrode of the PMOS tube M14 is connected to the source electrode of the PMOS tube PM0, the source electrode and the substrate of the PMOS tube PM0 are connected with a power supply Vdd, the grid electrode of the PMOS tube PM0 is connected with a reference voltage VREFPGM, the drain electrode and the grid electrode of the NMOS tube M16, the drain electrode of the NMOS tube NM0 and the differential amplification module form a bias voltage VBIAS node, the source electrodes of the NMOS tubes M16 and NM0 are grounded gnd, and the grid electrode of the NMOS tube NM0 is connected with the enable signal EN_N of the complementary amplifier;
the differential amplification module comprises a PMOS tube M19, a PMOS tube PM1, an NMOS amplification tube NM3, an NMOS tube M0, an NMOS primary tube M1, an NMOS primary tube N2 and a first lower bias tube NM1, wherein the PMOS tube M19 and the PMOS tube PM1 form mirror constant current sources, the sources and the substrates of the PMOS tube M19 are connected with a power supply Vdd, the drains and the gates of the PMOS tube M19 are connected with the grid electrode of the PMOS tube PM1, the drain electrode of the NMOS tube NM3 and the drain electrode of the NMOS primary tube M1 to form a node B, the reverse phase differential voltage VN is connected to the grid electrode of the NMOS tube NM3, the grid electrode of the NMOS primary tube M1, the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube M0, the drain electrode of the NMOS primary tube N2 and the output amplification module to form a node C, the drain electrode of the first lower bias NMOS tube NM1 is connected with the source electrode of the NMOS tube NM3, the source electrode of the NMOS primary tube M0, the source electrode of the NMOS tube M0 is connected with the same phase as the source of the NMOS tube N2, the drain electrode of the NMOS tube N2 is connected with the drain electrode of the NMOS tube M2 to form a node A, the differential voltage VN 0 is connected with the drain electrode of the primary tube NM2, the drain electrode of the NMOS tube N2 is connected with the drain electrode of the primary tube N2, and the drain is connected with the drain electrode of the primary tube N2.
2. An amplifier having a wide input voltage range as claimed in claim 1, characterized in that: the control module includes an inverter I61 and an inverter I62.
3. An amplifier having a wide input voltage range as claimed in claim 2, characterized in that: the amplifier on enable signal comp_en is connected to the input terminal of the inverter I61, the output terminal of the inverter I61, i.e., the complementary amplifier enable signal en_n is connected to the input terminal of the inverter I62 and the bias voltage module, and the output terminal of the inverter I62, i.e., the amplifier enable signal EN is connected to the output amplification module.
4. An amplifier having a wide input voltage range as claimed in claim 1, characterized in that: the output amplification module comprises a PMOS tube M20, a PMOS tube M18 and a second lower bias NMOS tube NM2.
5. An amplifier having a wide input voltage range as claimed in claim 4, characterized in that: the grid electrode of the PMOS tube M20 is connected with the node C, the drain electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18 and the drain electrode of the second lower bias NMOS tube to form an output signal FB_N node, the source electrode and the substrate of the second lower bias NMOS tube NM2 are grounded gnd, the grid electrode of the PMOS tube M18 is connected with the amplifier enabling signal EN, and the source electrode and the substrate are connected with a power supply.
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| CN201910069111.0A CN109802641B (en) | 2019-01-24 | 2019-01-24 | Amplifier with wider input voltage range |
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| CN201910069111.0A CN109802641B (en) | 2019-01-24 | 2019-01-24 | Amplifier with wider input voltage range |
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| CN109802641B true CN109802641B (en) | 2023-06-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112965567B (en) * | 2021-02-08 | 2022-02-11 | 苏州领慧立芯科技有限公司 | Low-noise voltage driving buffer |
| CN113341212B (en) * | 2021-06-05 | 2022-08-02 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040084722A (en) * | 2003-03-27 | 2004-10-06 | 엔이씨 일렉트로닉스 가부시키가이샤 | Differential amplifier 0perable in wide range |
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108710400A (en) * | 2018-06-04 | 2018-10-26 | 电子科技大学 | A kind of enabled circuit can be used for negative voltage output |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040084722A (en) * | 2003-03-27 | 2004-10-06 | 엔이씨 일렉트로닉스 가부시키가이샤 | Differential amplifier 0perable in wide range |
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108710400A (en) * | 2018-06-04 | 2018-10-26 | 电子科技大学 | A kind of enabled circuit can be used for negative voltage output |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
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