CN109802641A - A kind of wider amplifier of input voltage range - Google Patents
A kind of wider amplifier of input voltage range Download PDFInfo
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- CN109802641A CN109802641A CN201910069111.0A CN201910069111A CN109802641A CN 109802641 A CN109802641 A CN 109802641A CN 201910069111 A CN201910069111 A CN 201910069111A CN 109802641 A CN109802641 A CN 109802641A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a kind of wider amplifiers of input voltage range, comprising: control module, for amplifier Access Authorized signal COMP_EN to be converted to complementary amplifier enable signal EN_N and amplifier enable signal EN；Bias voltage module, for bias voltage VBIAS needed for reference voltage VREFPGM is converted to the amplifier operation under the control of complementary amplifier enable signal EN_N；Differential amplification module, for amplifying the difference of input differential signal VN and VP under the control of bias voltage VBIAS；Export amplification module, for amplified differential signal to be further amplified under the control of amplifier enable signal EN to obtain output signal FB_N, the present invention by using high-voltage tube and high pressure Native pipe parallel connection as the input of amplifier to pipe, to solve the problems, such as input range and gain simultaneously.
Description
Technical field
The present invention relates to a kind of amplifiers, more particularly to a kind of wider amplifier of input voltage range.
Background technique
The amplifier for being currently used for the differential voltage of embedded flash memory (eFlash) includes control module 10, biased electrical pressing mold
Block 20, differential amplification module 30 and output amplification module 40.Wherein, control module 10 plays I61 and I62 by direction and forms, and is used for
Amplifier Access Authorized signal COMP_EN is converted into complementary amplifier enable signal EN_N and amplifier enable signal EN；Partially
It sets voltage module 20 to be made of PMOS tube M14, PMOS tube PM0, NMOS tube M16 and NMOS tube NM0, for making in complementary amplifier
Reference voltage VREFPGM is converted into a kind of wider amplifier operation institute of input voltage of the present invention under the control of energy signal EN_N
The bias voltage VBIAS needed；Differential amplification module 30 is by PMOS tube M19, PMOS tube PM1, NMOS amplifier tube NM3, NMOS tube M0
With the first below-center offset pipe NM1 form, under the control of bias voltage VBIAS by the difference of input differential signal VN and VP into
Row amplification；Output amplification module 40 is made of PMOS tube M20, PMOS tube M18 and the second below-center offset NMOS tube NM2, for putting
Amplified differential signal is further amplified to obtain output signal FB_N under the control of big device enable signal EN.
Amplifier Access Authorized signal COMP_EN is connected to the input terminal of phase inverter I61, and the output end of phase inverter I61 is
Complementary amplifier enable signal EN_N is connected to the grid of the input terminal of phase inverter I62, the grid of PMOS tube M14 and NMOS tube NM0
Pole, output end, that is, amplifier enable signal EN of phase inverter I62 are connected to the grid of PMOS tube M18；The drain electrode of PMOS tube M14 connects
It is connected to the source electrode of PMOS tube PM0, the substrate of PMOS tube PM0 meets power supply Vdd, and the grid of PMOS tube PM0 connects reference voltage
The drain electrode of the drain and gate, NMOS tube NM0 of the drain electrode and NMOS tube M16 of VREFPGM, PMOS tube PM0, the first below-center offset NMOS
The grid of the grid of pipe NM1 and the second below-center offset NMOS tube NM2 are connected to form bias voltage VBIAS node, NMOS tube M16, NM0
Source electrode and Substrate ground gnd；The source electrode of PMOS tube M14, M19, PM1, M20, M18 connect power supply Vdd, PMOS tube with substrate
M19 and PMOS tube PM1 forms mirror-image constant flow source, the drain and gate of PMOS tube M19 and grid, the NMOS tube NM3 of PMOS tube PM1
Drain electrode be connected to form node B, inverting difference voltage VN is connected to the grid of NMOS tube NM3, the drain electrode of PMOS tube PM1 and NMOS
The drain electrode of pipe M0 and the grid of PMOS tube M20 are connected to form node C, the drain electrode and NMOS tube of the first below-center offset NMOS tube NM1
The source electrode of NM3, the source electrode of NMOS tube M0 are connected to form node A, and the grid of NMOS tube M0, NMOS are connected to phase differential voltage VP
The Substrate ground gnd of the substrate of pipe NM3, NMOS tube M0；Under the drain electrode of PMOS tube M20 and the drain electrode and second of PMOS tube M18
The drain electrode of biasing NMOS tube is connected to form output signal FB_N node；First below-center offset NMOS tube NM1, the second below-center offset NMOS tube
Source electrode and Substrate ground gnd.
AC result below 1 Conventional amplifiers difference PVT of table
Above-mentioned table 1 is the AC result below Conventional amplifiers difference PVT.As it can be seen that the amplifier of the prior art, different
Under PVT (Precess Voltage Temperature) process corner, gain fluctuation is big, and the prior art is in some process corners
Lower such as ss/Vdd=1.7V/Vn=0.5-0.6V/-40 DEG C and ss/Vdd=1.3V/Vn=0.5-0.6V/-40 DEG C, sf/Vdd=
It will not work at 1.7V/Vn=0.5-0.6V/-40 DEG C, sf/Vdd=1.3V/Vn=0.5-0.6V/-40 DEG C.
Generally, a large amount of charge pump and high pressure are used inside eFlash circuit.In order to detect these high pressures, need to compare
Device and reference voltage.Due to being easier to generate 0.8v or lower than the ginseng of 0.8v below by bandgap in 1.5v supply voltage
Examine voltage VREF.
Input one end of comparator is reference voltage VREF, another section be charge pump output HV.In view of BV, comparator
Input high voltage bearing pipe, such as HV_NMOS or HV_Native must be selected to pipe.
However, if the threshold voltage in the face under extreme conditions selection high-voltage tube HV_NMOS is relatively high.Such as SS
Corner/-40c. face in such a situa-tion, the input voltage near 0.8v have entered subthreshold region, have caused gain low very
To not working；If selecting high pressure Native pipe as input to pipe, high pressure native pipe has the characteristics that high voltage bearing, Ke Yizuo
For high pressure input to pipe, but since the VT of high pressure Native pipe is low, the input voltage near 0.8v has made it into line
Property area, in addition the Vt of Native pipe is inaccurate, mismatch is poor, and the input for being also not suitable for being used as comparator uses pipe.
Therefore, the present invention is quasi- selects to use the input of high-voltage tube and high pressure Native pipe parallel connection as amplifier to pipe, with solution
Certainly input range and the problem of gain.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of input voltage range is wider
Amplifier, using by using high-voltage tube and high pressure Native pipe parallel connection as the input of amplifier to pipe, while solving to input
The problem of range and gain.
In view of the above and other objects, the present invention proposes a kind of wider amplifier of input voltage range, comprising:
Control module, for amplifier Access Authorized signal COMP_EN to be converted to complementary amplifier enable signal EN_N
With amplifier enable signal EN；
Bias voltage module, for turning reference voltage VREFPGM under the control of complementary amplifier enable signal EN_N
Bias voltage VBIAS needed for being changed to the amplifier operation；
Differential amplification module, under the control of bias voltage VBIAS by the difference of input differential signal VN and VP into
Row amplification；
Amplification module is exported, for further putting amplified differential signal under the control of amplifier enable signal EN
Output signal FB_N is obtained greatly.
Preferably, the control module includes phase inverter I61 and phase inverter I62.
Preferably, the amplifier Access Authorized signal COMP_EN is connected to the input terminal of the phase inverter I61, described
The output end of phase inverter I61, that is, complementary amplifier enable signal EN_N is connected to the input terminal of the phase inverter I62 and described
Output end, that is, amplifier enable signal EN of bias voltage module, the phase inverter I62 is connected to the output amplification module.
Preferably, the bias voltage module includes PMOS tube M14, PMOS tube PM0, NMOS tube M16 and NMOS tube NM0.
Preferably, the PMOS tube M14 grid meets the complementary amplifier enable signal EN_N, and drain electrode is connected to PMOS tube
The source electrode of PM0, source electrode and substrate connect power supply, and the substrate of the PMOS tube PM0 meets power supply Vdd, and grid connects reference voltage
VREFPGM, the drain electrode and and the differential amplification module shape of drain electrode and the drain and gate, NMOS tube NM0 of NMOS tube M16
At bias voltage VBIAS node, the source electrode and Substrate ground gnd, the NMOS tube NM0 grid of NMOS tube M16, NM0 are connect
The complementary amplifier enable signal EN_N.
Preferably, the differential amplification module is using high-voltage tube and the primary pipe parallel connection of high pressure as the input pair of amplifier
Pipe.
Preferably, the differential amplification module includes PMOS tube M19, PMOS tube PM1, NMOS amplifier tube NM3, NMOS tube
The primary pipe N2 of M0, NMOS primary pipe M1, NMOS and the first below-center offset pipe NM1.
Preferably, the PMOS tube M19 and PMOS tube PM1 forms mirror-image constant flow source, and source electrode connects power supply with substrate
Vdd, the drain and gate and the grid of PMOS tube PM1, the drain electrode of NMOS tube NM3, the primary pipe M1 of NMOS of the PMOS tube M19
Drain electrode be connected to form node B, inverting difference voltage VN is connected to the grid of the primary pipe M1 of the grid of NMOS tube NM3, NMOS,
The drain electrode of PMOS tube PM1 is connected group with the drain electrode of NMOS tube M0, the drain electrode of the primary pipe N2 of NMOS and the output amplification module
At node C, the source electrode of the primary pipe M1 of source electrode, NMOS of the drain electrode and NMOS tube NM3 of the first below-center offset NMOS tube NM1, NMOS tube
The source electrode of the primary pipe N2 of source electrode, the NMOS of M0 is connected to form node A, with phase differential voltage VP be connected to NMOS tube M0 grid,
The grid of the primary pipe N2 of NMOS, substrate, substrate, the NMOS of NMOS tube M0 of the primary pipe M1 of substrate, the NMOS of NMOS tube NM3 are primary
The Substrate ground gnd of pipe N2, the first below-center offset pipe NM1 grid connect the bias voltage VBIAS node.
Preferably, the output amplification module includes PMOS tube M20, PMOS tube M18 and the second below-center offset NMOS tube NM2.
Preferably, the PMOS tube M20 grid meets the node C, and the drain electrode of the PMOS tube M20 is with PMOS tube M18's
Drain electrode and the drain electrode of the second below-center offset NMOS tube are connected to form output signal FB_N node, the second below-center offset NMOS tube NM2's
Source electrode and Substrate ground gnd, the PMOS tube M18 grid meet the amplifier enable signal EN, and source electrode connects power supply with substrate.
Compared with prior art, a kind of amplifier that input voltage range is wider of the present invention, by utilizing high-voltage tube
With high pressure Native pipe parallel connection as amplifier input to pipe, while solving the problems, such as input range and gain.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for being used for the amplifier of differential voltage of embedded flash memory (eFlash) in the prior art；
Fig. 2 is a kind of system construction drawing of the wider amplifier of input voltage range of the present invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 2 is a kind of system construction drawing of the wider amplifier of input voltage range of the present invention.As shown in Fig. 2, of the invention
A kind of wider amplifier of input voltage range, comprising: control module 10, bias voltage module 20,30 and of differential amplification module
Export amplification module 40.
Wherein, control module 10 is made of phase inverter I61 and phase inverter I62, is used for amplifier Access Authorized signal
COMP_EN is converted to complementary amplifier enable signal EN_N and amplifier enable signal EN；Bias voltage module 20 is by PMOS tube
M14, PMOS tube PM0, NMOS tube M16 and NMOS tube NM0 composition, for being incited somebody to action under the control of complementary amplifier enable signal EN_N
Bias voltage VBIAS needed for reference voltage VREFPGM is converted to a kind of wider amplifier operation of input voltage of the present invention；Difference
Divide amplification module 30 by PMOS tube M19, PMOS tube PM1, NMOS amplifier tube NM3, the primary pipe of NMOS tube M0, NMOS (Native pipe)
The primary pipe of M1, NMOS (Native pipe) N2 and the first below-center offset pipe NM1 composition, for being incited somebody to action under the control of bias voltage VBIAS
The difference of input differential signal VN and VP amplify；Amplification module 40 is exported by under PMOS tube M20, PMOS tube M18 and second
NMOS tube NM2 composition is biased, for amplified differential signal to be further amplified under the control of amplifier enable signal EN
Obtain output signal FB_N.
Amplifier Access Authorized signal COMP_EN is connected to the input terminal of phase inverter I61, and the output end of phase inverter I61 is
Complementary amplifier enable signal EN_N is connected to the grid of the input terminal of phase inverter I62, the grid of PMOS tube M14 and NMOS tube NM0
Pole, output end, that is, amplifier enable signal EN of phase inverter I62 are connected to the grid of PMOS tube M18；The drain electrode of PMOS tube M14 connects
It is connected to the source electrode of PMOS tube PM0, the substrate of PMOS tube PM0 meets power supply Vdd, and the grid of PMOS tube PM0 connects reference voltage
The drain electrode of the drain and gate, NMOS tube NM0 of the drain electrode and NMOS tube M16 of VREFPGM, PMOS tube PM0, the first below-center offset NMOS
The grid of the grid of pipe NM1 and the second below-center offset NMOS tube NM2 are connected to form bias voltage VBIAS node, NMOS tube M16, NM0
Source electrode and Substrate ground gnd；The source electrode of PMOS tube M14, M19, PM1, M20, M18 connect power supply Vdd, PMOS tube with substrate
M19 and PMOS tube PM1 forms mirror-image constant flow source, the drain and gate of PMOS tube M19 and grid, the NMOS tube NM3 of PMOS tube PM1
Drain electrode, the primary pipe of NMOS (Native pipe) M1 drain electrode be connected to form node B, inverting difference voltage VN is connected to NMOS tube
The grid of the primary pipe of grid, NMOS (Native pipe) M1 of NM3, the drain electrode and the drain electrode of NMOS tube M0 of PMOS tube PM1, NMOS are former
Raw pipe (Native pipe) drain electrode of N2 and the grid of PMOS tube M20 are connected to form node C, the first below-center offset NMOS tube NM1's
The primary pipe of source electrode, NMOS (Native pipe) source electrode of M1, the source electrode of NMOS tube M0, the primary pipe of NMOS of drain electrode and NMOS tube NM3
The source electrode of (Native pipe) N2 is connected to form node A, is connected to the primary pipe of the grid of NMOS tube M0, NMOS with phase differential voltage VP
The grid of (Native pipe) N2, the lining of the substrate of the primary pipe of substrate, NMOS (Native pipe) M1 of NMOS tube NM3, NMOS tube M0
Bottom, the primary pipe of NMOS (Native pipe) N2 Substrate ground gnd；The drain electrode of PMOS tube M20 and the drain electrode of PMOS tube M18 and the
The drain electrode of two below-center offset NMOS tubes is connected to form output signal FB_N node；First below-center offset NMOS tube NM1, the second below-center offset
The source electrode and Substrate ground gnd of NMOS tube.
From table 1, the prior art increases under different PVT (Precess Voltage Temperature) process corners
Benefit fluctuation is big, average value 49.88dB, deviation only -24.3/+16.7dB；After table 3 improves for the present invention under amplifier difference PVT
The AC simulation result in face:
AC simulation result after table 3 improves below amplifier difference PVT
It is emulated in terms of data list from table 3, after improvement, the present invention is in different PVT (Precess Voltage
Temperature) under process corner, gain stabilization, average value 60.83dB, deviation only -6.5/+2.9dB, hence it is evident that better than existing
Technology.And when instantaneously emulating, it can work under different PVT (Precess Voltage Temperature) process corners, and
The prior art is under some process corners such as ss/Vdd=1.7V/Vn=0.5-0.6V/-40 DEG C and ss/Vdd=1.3V/Vn=
0.5-0.6V/-40 DEG C, sf/Vdd=1.7V/Vn=0.5-0.6V/-40 DEG C, sf/Vdd=1.3V/Vn=0.5-0.6V/-40
DEG C when will not work, the present invention is also significantly better than the prior art.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of wider amplifier of input voltage range, comprising:
Control module, for amplifier Access Authorized signal COMP_EN to be converted to complementary amplifier enable signal EN_N and is put
Big device enable signal EN；
Bias voltage module, for being converted to reference voltage VREFPGM under the control of complementary amplifier enable signal EN_N
Bias voltage VBIAS needed for the amplifier operation；
Differential amplification module, for putting the difference of input differential signal VN and VP under the control of bias voltage VBIAS
Greatly；
Amplification module is exported, for amplified differential signal to be further amplified under the control of amplifier enable signal EN
To output signal FB_N.
2. a kind of wider amplifier of input voltage range as described in claim 1, it is characterised in that: the control module packet
Include phase inverter I61 and phase inverter I62.
3. a kind of wider amplifier of input voltage range as claimed in claim 2, it is characterised in that: the amplifier is opened
Enabling signal COMP_EN is connected to the input terminal of the phase inverter I61, output end, that is, complementary amplifier of the phase inverter I61
Enable signal EN_N is connected to the input terminal and the bias voltage module of the phase inverter I62, and the phase inverter I62's is defeated
Outlet, that is, amplifier enable signal EN is connected to the output amplification module.
4. a kind of wider amplifier of input voltage range as claimed in claim 3, it is characterised in that: the biased electrical pressing mold
Block includes PMOS tube M14, PMOS tube PM0, NMOS tube M16 and NMOS tube NM0.
5. a kind of wider amplifier of input voltage range as claimed in claim 4, it is characterised in that: the PMOS tube M14
Grid meets the complementary amplifier enable signal EN_N, and drain electrode is connected to the source electrode of PMOS tube PM0, and source electrode and substrate connect power supply,
The substrate of the PMOS tube PM0 meets power supply Vdd, and grid connects reference voltage VREFPGM, drain electrode and grid of the drain electrode with NMOS tube M16
Pole, NMOS tube NM0 drain electrode and and the differential amplification module formed bias voltage VBIAS node, the NMOS tube
The source electrode and Substrate ground gnd of M16, NM0, the NMOS tube NM0 grid meet the complementary amplifier enable signal EN_N.
6. a kind of wider amplifier of input voltage range as claimed in claim 5, it is characterised in that: the differential amplification mould
Block using high-voltage tube and the primary pipe parallel connection of high pressure as the input of amplifier to pipe.
7. a kind of wider amplifier of input voltage range as claimed in claim 6, it is characterised in that: the differential amplification mould
Block include PMOS tube M19, PMOS tube PM1, NMOS amplifier tube NM3, the primary pipe N2 of NMOS tube M0, NMOS primary pipe M1, NMOS and
First below-center offset pipe NM1.
8. a kind of wider amplifier of input voltage range as claimed in claim 7, it is characterised in that: the PMOS tube M19
Mirror-image constant flow source is formed with PMOS tube PM1, source electrode connects power supply Vdd with substrate, the drain and gate of the PMOS tube M19
Node B, inverting difference electricity are connected to form with the grid of PMOS tube PM1, the drain electrode of NMOS tube NM3, the drain electrode of the primary pipe M1 of NMOS
Pressure VN is connected to the grid of the primary pipe M1 of the grid of NMOS tube NM3, NMOS, the drain electrode of PMOS tube PM1 and the drain electrode of NMOS tube M0,
The drain electrode of the primary pipe N2 of NMOS and the output amplification module are connected to form node C, the drain electrode of the first below-center offset NMOS tube NM1
It is connected group with the source electrode of the primary pipe N2 of source electrode, NMOS of the source electrode of NMOS tube NM3, the source electrode of the primary pipe M1 of NMOS, NMOS tube M0
At node A, the grid of the primary pipe N2 of the grid of NMOS tube M0, NMOS, the lining of NMOS tube NM3 are connected to phase differential voltage VP
Bottom, the substrate of the primary pipe M1 of NMOS, NMOS tube M0 the primary pipe N2 of substrate, NMOS Substrate ground gnd, first below-center offset
Pipe NM1 grid connects the bias voltage VBIAS node.
9. a kind of wider amplifier of input voltage range as claimed in claim 8, it is characterised in that: mould is amplified in the output
Block includes PMOS tube M20, PMOS tube M18 and the second below-center offset NMOS tube NM2.
10. a kind of wider amplifier of input voltage range as claimed in claim 9, it is characterised in that: the PMOS tube M20
Grid connects the node C, the drain electrode of the PMOS tube M20 and the drain electrode of PMOS tube M18 and the leakage of the second below-center offset NMOS tube
Pole is connected to form output signal FB_N node, the source electrode and Substrate ground gnd of the second below-center offset NMOS tube NM2, the PMOS tube
M18 grid meets the amplifier enable signal EN, and source electrode connects power supply with substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910069111.0A CN109802641B (en) | 2019-01-24 | 2019-01-24 | Amplifier with wider input voltage range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910069111.0A CN109802641B (en) | 2019-01-24 | 2019-01-24 | Amplifier with wider input voltage range |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109802641A true CN109802641A (en) | 2019-05-24 |
| CN109802641B CN109802641B (en) | 2023-06-16 |
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ID=66560317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910069111.0A Active CN109802641B (en) | 2019-01-24 | 2019-01-24 | Amplifier with wider input voltage range |
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| CN (1) | CN109802641B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112965567A (en) * | 2021-02-08 | 2021-06-15 | 苏州领慧立芯科技有限公司 | Low-noise voltage driving buffer |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
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| KR20040084722A (en) * | 2003-03-27 | 2004-10-06 | 엔이씨 일렉트로닉스 가부시키가이샤 | Differential amplifier 0perable in wide range |
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108710400A (en) * | 2018-06-04 | 2018-10-26 | 电子科技大学 | A kind of enabled circuit can be used for negative voltage output |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
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2019
- 2019-01-24 CN CN201910069111.0A patent/CN109802641B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040084722A (en) * | 2003-03-27 | 2004-10-06 | 엔이씨 일렉트로닉스 가부시키가이샤 | Differential amplifier 0perable in wide range |
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108710400A (en) * | 2018-06-04 | 2018-10-26 | 电子科技大学 | A kind of enabled circuit can be used for negative voltage output |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112965567A (en) * | 2021-02-08 | 2021-06-15 | 苏州领慧立芯科技有限公司 | Low-noise voltage driving buffer |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
| CN113341212B (en) * | 2021-06-05 | 2022-08-02 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
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| Publication number | Publication date |
|---|---|
| CN109802641B (en) | 2023-06-16 |
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