CN210518233U

CN210518233U - Rail-to-rail input stage circuit with constant transconductance

Info

Publication number: CN210518233U
Application number: CN201921890875.8U
Authority: CN
Inventors: 曹毅; 陈弈星; 于钦杭
Original assignee: Nanjing Xinshiyuan Electronics Co ltd
Current assignee: Nanjing Xinshiyuan Electronics Co ltd
Priority date: 2019-11-05
Filing date: 2019-11-05
Publication date: 2020-05-12
Anticipated expiration: 2029-11-05

Abstract

The utility model provides a rail-to-rail input stage circuit of invariable transconductance mainly contains PMOS input geminate transistor branch road and NMOS input geminate transistor branch road, adopts the comparator to correspond selection PMOS geminate transistor or NMOS geminate transistor work in two input common mode voltage ranges, realizes rail-to-rail input and invariable transconductance. The utility model discloses compare the rail-to-rail input circuit of traditional invariable transconductance, simple structure, consumption reach lower, stride to the input range of power and lead and keep invariable ground.

Description

Rail-to-rail input stage circuit with constant transconductance

Technical Field

The utility model belongs to the technical field of analog circuit and specifically relates to a rail-to-rail input stage circuit of invariable transconductance is related to.

Background

With the continuous development of chip technology, the performance requirements for analog circuits are higher and higher. In analog circuit modules, the design of operational amplifier circuits is the most extensive, and some circuit modules need to adopt a rail-to-rail input stage design to meet the input requirement of full swing.

SUMMERY OF THE UTILITY MODEL

The utility model provides a rail-to-rail input stage circuit of invariable transconductance can realize the input of rail-to-rail and keep invariable transconductance.

The main contents of the utility model include:

a rail-to-rail input stage circuit with constant transconductance comprises a PMOS input geminate transistor branch and an NMOS input geminate transistor branch, and a comparator is adopted to correspondingly select a PMOS geminate transistor or an NMOS geminate transistor to work in a range of two input common-mode voltages, so that rail-to-rail input and constant transconductance are realized.

Further, the transconductance values of the PMOS pair transistor and the NMOS pair transistor are equal in a saturation region by adjusting the channel width-length ratio of the PMOS pair transistor and the NMOS pair transistor in the PMOS input pair transistor branch and the NMOS input pair transistor branch.

Further, the comparator compares the input common mode voltage with half of the power supply voltage, when the common mode voltage is less than or equal to half of the power supply voltage, the output of the comparator is low voltage, and when the common mode voltage is greater than half of the power supply voltage, the output of the comparator is high voltage.

Further, the output signal of the comparator controls the closing or conducting of the PMOS pair transistor and the NMOS pair transistor.

Furthermore, the output signal of the comparator controls the closing or the conduction of the PMOS geminate transistor after passing through the inverter; meanwhile, the output signal of the comparator directly controls the closing or conducting of the NMOS geminate transistor.

Further, when the output signal of the comparator is low voltage, the branch where the PMOS pair transistor is located is controlled to work, and the NMOS pair transistor is turned off.

Further, the output of the comparator is high voltage, the branch where the NMOS pair transistor is located is controlled to work, and the PMOS pair transistor is switched off.

The beneficial effects of the utility model reside in that:

the utility model provides a rail-to-rail input stage circuit of invariable transconductance contains PMOS input geminate transistor branch road and NMOS input geminate transistor branch road, adopts the comparator to correspond in two input common mode voltage ranges and selects PMOS geminate transistor and NMOS geminate transistor work, can realize the design requirement of rail-to-rail input and invariable transconductance, compare the rail-to-rail input simple structure of traditional invariable transconductance, the consumption reaches lowly, ground also can keep invariable to the input range internal transconductance of power.

Drawings

Fig. 1 is a schematic circuit diagram of a rail-to-rail input stage of constant transconductance according to the present invention;

fig. 2 is a schematic diagram of the input stage transconductance of the present invention.

Detailed Description

The technical solution protected by the present invention will be specifically described below with reference to the accompanying drawings.

Please refer to fig. 1 to 2. The utility model provides a rail-to-rail input stage circuit with constant transconductance, which comprises a PMOS input geminate transistor branch, an NMOS input geminate transistor branch and a comparator, wherein,

the PMOS input pair transistor branch and the NMOS input pair transistor branch, as shown in fig. 1, select corresponding branches to operate according to the high and low voltages output by the comparator, so that the PMOS pair transistor and the NMOS pair transistor operate in the saturation region, and simultaneously adjust the bias current and the width-to-length ratio of the MOS transistor to make the transconductance values of the saturation region equal.

The PMOS input pair transistor branch comprises two PMOS transistors M1 and M2 of common source, a common source contact is connected with a power voltage VDD through a switch SW _ P, and grids of the PMOS transistors M1 and M2 are respectively connected with positive and negative input voltage electrodes VIN + and VIN-.

The NMOS transistor pair branch comprises two NMOS transistors M3 and M4 with common sources, a common source node is grounded GND through a switch SW _ N, and grids of the NMOS transistors M3 and M4 are respectively connected with positive and negative input voltage electrodes VIN + and VIN-.

The drain outputs of the PMOS tubes M1 and M2 and the NMOS tubes M3 and M4 are used as a post-stage circuit.

The switch SW _ P is triggered to be turned on or off by a signal obtained by inverting the output signal of the comparator through the inverter U1. The switch SW _ N is triggered to be switched on or off by the output signal of the comparator.

The comparator compares the input common-mode voltage VCM with a half VDD/2 of the power supply voltage VDD, when the VCM is less than or equal to VDD/2, the output of the comparator is at a low level, the switch SW _ P is switched on after passing through the inverter U1, the current bias corresponding to the PMOS input pair transistors M1 and M2 is switched on, meanwhile, the low level output by the comparator switches off the switch SW _ N, and the current bias corresponding to the NMOS input pair transistors M3 and M4 is switched off; when VCM is larger than VDD/2, the output of the comparator is in high level, the switch SW _ N is conducted, the current bias corresponding to the NMOS input pair transistors M3 and M4 is gated, meanwhile, the high level output by the comparator enables the switch SW _ P to be disconnected after passing through the inverter U1, and the current bias corresponding to the PMOS input pair transistors M1 and M2 is closed.

As shown in fig. 2, the input common-mode voltage is in the range from ground to VDD/2 input, and the equivalent transconductance is the transconductance gmp of the PMOS pair transistor in the saturation region; when the input common mode voltage is larger than VDD/2, the input common mode voltage is equivalent to transconductance gmn of NMOS paired transistors in a saturation region, and after bias current and channel width-length ratio are adjusted, gm is enabled to be larger_{Saturation of}= gmp = gmn, so that a constant transconductance is maintained between ground and supply, while rail-to-rail input is possible.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all the equivalent structures or equivalent processes that are used in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A rail-to-rail input stage circuit with constant transconductance is characterized by comprising a PMOS input pair transistor branch and an NMOS input pair transistor branch, and a comparator is adopted to correspondingly select a PMOS pair transistor or an NMOS pair transistor to work within a range of two input common-mode voltages so as to realize rail-to-rail input and constant transconductance.

2. A constant transconductance rail-to-rail input stage circuit according to claim 1, wherein transconductance values of the PMOS pair transistor and the NMOS pair transistor in the saturation region are equalized by adjusting channel width-to-length ratios of the PMOS pair transistor and the NMOS pair transistor in the PMOS input pair transistor branch and the NMOS input pair transistor branch.

3. The constant transconductance rail-to-rail input stage circuit of claim 1, wherein the comparator compares an input common mode voltage with half of a supply voltage, the comparator output being a low voltage when the common mode voltage is less than or equal to half of the supply voltage, and the comparator output being a high voltage when the common mode voltage is greater than half of the supply voltage.

4. The constant transconductance rail-to-rail input stage circuit of claim 1, wherein the output signal of the comparator controls the PMOS pair transistor and the NMOS pair transistor to be turned off or on.

5. The constant transconductance rail-to-rail input stage circuit of claim 4, wherein an output signal of the comparator controls the closing or conduction of the PMOS pair transistor after passing through the inverter; meanwhile, the output signal of the comparator directly controls the closing or conducting of the NMOS geminate transistor.

6. A constant transconductance rail-to-rail input stage circuit according to claim 5, wherein when the output signal of the comparator is a low voltage, the branch of the PMOS pair transistor is controlled to operate, and the NMOS pair transistor is controlled to be turned off.

7. A constant transconductance rail-to-rail input stage circuit according to claim 5, wherein the comparator output is a high voltage, controlling the NMOS pair transistor branch to operate and the PMOS pair transistor to be off.