CN1961621A - 用于在印刷电路板构造上制造通孔的方法 - Google Patents
用于在印刷电路板构造上制造通孔的方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/092—Particle beam, e.g. using an electron beam or an ion beam
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Electric Cable Installation (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
建议一种用于制造印刷电路板构造的方法,所述印刷电路板构造此外还能够以无胶粘剂、柔性、且具有最小通孔的方式加以实现,其中所述通孔具有1至3μm数量级的直径。本方法以印刷电路板构造用的还不具有任何铜涂覆的基体介质为出发点。尤其是针对最小的通孔借助于重离子使穿孔射入如此准备的材料中。接着才给基体介质的表面涂覆铜。在此,同时制造电通孔。如果基体介质例如是柔性的聚酰亚胺并且还未针对铜涂覆被预先处理,则尤其是所述重离子方法除了射击出孔之外还可以同时被用于使表面粗糙。接着,按照常规的方法完成所期望的印刷电路板构造。
Description
本发明涉及一种按照权利要求1的前序部分的用于制造通孔的方法。
在用于制造两层或多层印刷电路板构造的方法中,通孔(Durchkontaktierung)通常是一个问题,尤其是在焊盘直径小于200μm的最小空间上的微通孔是一个问题。根据目前的技术状况,例如可以制造孔径为75至100μm且焊盘直径为250至300μm的微导通孔。
相应的说明例如源自于公司P.C.M.GmbH(Hattsteiner Allee 17,61250 Usingen,URL:http://www.p-m-c.de/Produkte/Standardleiterplatten/tech-rdllp_d.htm)的资料。
此外,根据文献WO 2004/015161 A1已公知用于通过重离子照射和随后的蚀刻工艺来处理基材的方法和装置,所述重离子照射和随后的蚀刻工艺被用于使印刷电路板构造的基体介质(Trgermittel)的表面或印刷电路板构造的基材的表面粗糙,以便随后要涂覆的铜层在那里可靠地保持在基体介质或基材的相应被处理的表面上。
如果以无胶粘剂的方式将铜层涂覆到基体介质或者基材上,并且如果基体介质或基材是诸如聚酰亚胺的塑料,则使表面粗糙是特别重要的。
聚酰亚胺(PI)被用于高值的印刷电路板构造,其是可弯曲的、即柔性的。这种基体介质的另一实例是聚萘二甲酸乙二醇酯(PEN)和聚脂(PET)。对于刚性印刷电路板构造,例如可以采用CEM1、FR2或FR4作为基体介质。
在迄今的用于制造印刷电路板构造(Leiterplattengebilden)的制造工艺中,在实现通孔时使用已经涂覆有铜层的基体介质。其结果是,在制造电通孔时,至少在一些位置处涂覆另一铜层,通过该另一铜层增加了最后所得到的印刷电路板构造的厚度。此外,用于涂覆第一铜层的耗费在一定程度上是冗余的。另一缺点是,相比于较薄的总铜层,总共所得到的较厚的铜层仅仅允许较粗糙的印制电路结构。另外,应当试图进一步减小通孔用的占地面积,以便例如在印刷电路板构造的预定面积上能够安置得比迄今更多。
因此,本发明的任务是,说明一种用于制造前述类型的印刷电路板构造的方法,所述方法具有简化的制造工艺,能够制造最小的通孔,并且也可以应用于以无胶粘剂的方式所制造的柔性印刷电路板构造。
根据本发明,该任务通过一种具有在权利要求1的特征部分中所说明的方法步骤的方法来解决。
据此,在制造通孔时采用在表面上还不具有铜层的基体介质。由此取消直至该时刻为止已有的对于将所述层装配到基体介质上所必需的这样的制造步骤。由此最终简化了用于制造印刷电路板构造的总方法。
在装配某一层之前,在稍后的印刷电路板构造的为通孔所预先规定的位置处利用一种用于在分别相关的位置上分别制造至少一个唯一的孔的造孔方法来分别产生至少一个唯一的孔。
作为造孔方法,例如可以采用钻孔、激光、或者重离子射穿的方法。后者尤其具有以下优点:能够实现最小的通孔。
借助于接着的蚀刻工艺,在所期望的程度上对所制造的孔进行蚀刻。在此,如果所采用的造孔方法导致在一个位置处同时相邻地产生多于一个唯一的孔,正如在射击重离子时可能的那样,则紧靠在一起的孔被熔合成所期望大小的唯一的孔。于是,这种最终孔的孔例如具有1至3μm的直径,这在目前是用于通孔的可能的最小孔。
在随后的方法步骤中才实现对印刷电路板构造的基体介质或基材的表面的铜涂覆。在此,同时在通过先前方法步骤中所制造的孔的铜涂覆之间实现电通孔。
因为迄今还不存在铜层,所以铜涂覆的厚度是最小的。因此,可以利用所述铜涂覆制造最细致的印制电路结构。
此外,通孔的小的直径具有以下优点,即在制造电通孔时完全用铜来填充所述通孔。这对于能够流过所述通孔的可能的最大电流密度而言是有利的,并且在基体介质的平坦表面方面是有利的。因此,不必为了获得平坦的表面而在另一方法步骤中额外地填充所述通孔。
最后,可以实施另外的熟知的方法步骤,以便最终获得完整的期望的印刷电路板构造。
因为所述通孔非常小,所以可以在基体介质或印刷电路板构造的预定的面上设置相应增多的通孔。这在以下情况中是特别有利的,即所述印刷电路板构造例如将被用于显示器,在所述显示器中需要能够控制数量不断增加的多个控制点。
本发明的有利的扩展方案是从属权利要求的主题。
据此,正如上面已经提到的那样,重离子射击可以被用作造孔方法。由此如上述可以实现最小的通孔。如果不需要如此小的通孔,则也可以借助于激光方法来产生孔。如果通孔还可以更粗,则也可以借助于常规的钻孔方法来实现孔。
此外有利的是,能够将柔性材料(诸如聚酰亚胺)用作基体介质,原因在于由此能够制造柔性印刷电路板构造。这甚至具有最小的通孔和最细致的印制电路结构。
另一优点是,如果选择利用重离子的射击方法来为所述通孔形成孔,则不必事先完成使基体介质的表面粗糙的方法步骤,以便鉴于铜涂覆确保附着强度。除了制造用于通孔的孔之外,在相应地控制重离子照射的情况下,射击方法还可以同时被用于使基体介质的表面粗糙。在只期望使基体介质的表面粗糙的位置处,相应更小强度地调整重离子照射。在期望穿孔的位置处,进行相应加强的射击,使得重离子在这些位置处穿过基体介质的整个厚度。由此节省成本和制造时间。
使基体介质的表面粗糙的可能性与以下优点相关联,即可以以无胶粘剂的方式实现印刷电路板构造。
Claims (5)
1.用于在印刷电路板构造中制造通孔的方法,所述印刷电路板构造具有基体介质,在所述基体介质上最后布置所有其他介质,利用所述其他介质与基体介质一起实现所述印刷电路板构造,
其特征在于,
在涂覆所述其他介质之前,在稍后的印刷电路板构造的为通孔所预先规定的位置处仅仅对所述基体介质本身施加用于在分别相关的位置处分别制造至少一个唯一的孔的造孔方法,
随后实施蚀刻工艺,利用所述蚀刻工艺总是分别将在被施加造孔方法的相应位置处所产生的一个或多个孔蚀刻成具有所期望的总大小的一个唯一的共同的孔,
实施铜涂覆工艺,在所述铜涂覆工艺中对基体介质的已有的上侧和下侧进行铜涂覆,在所述上侧和下侧上进一步布置其他介质,用于在随后的步骤中形成印刷电路板构造,并且同时通过在先前方法步骤中所产生的孔来制造导电的通孔,以及
随后实现用于实现完整的印刷电路板构造的所有其他步骤。
2.按照权利要求1的方法,其特征在于,
在所述造孔方法中实施重离子射击。
3.按照权利要求1或2的方法,其特征在于,
将聚酰亚胺薄膜用作基体介质。
4.按照权利要求2或3的方法,其特征在于,
在重离子射击时,同时利用分别相应匹配的重离子射击来使所述基体介质表面的朝向射击的侧粗糙。
5.按照上述权利要求之一的方法,其特征在于,
将所述印刷电路板构造实现为无胶粘剂的印刷电路板构造。
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DE102004021063 | 2004-04-29 | ||
DE102004021063.2 | 2004-04-29 |
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CN1961621A true CN1961621A (zh) | 2007-05-09 |
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US (1) | US20070220745A1 (zh) |
EP (1) | EP1754399B1 (zh) |
JP (1) | JP2007535154A (zh) |
KR (1) | KR20070004929A (zh) |
CN (1) | CN1961621A (zh) |
AT (1) | ATE385399T1 (zh) |
BR (1) | BRPI0510332A (zh) |
DE (1) | DE502005002731D1 (zh) |
WO (1) | WO2005107348A1 (zh) |
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US7918018B2 (en) * | 2007-06-12 | 2011-04-05 | Texas Instruments Incorporated | Method of fabricating a semiconductor device |
FR2927218B1 (fr) * | 2008-02-06 | 2010-03-05 | Hydromecanique & Frottement | Procede de fabrication d'un element chauffant par depot de couches minces sur un substrat isolant et l'element obtenu |
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US3562009A (en) * | 1967-02-14 | 1971-02-09 | Western Electric Co | Method of providing electrically conductive substrate through-holes |
US6153060A (en) * | 1999-08-04 | 2000-11-28 | Honeywell International Inc. | Sputtering process |
US20020000370A1 (en) * | 1999-08-04 | 2002-01-03 | Richard J. Pommer | Ion processing of a substrate |
JP3879816B2 (ja) * | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器 |
US6629348B2 (en) * | 2001-05-01 | 2003-10-07 | Oak-Mitsui, Inc. | Substrate adhesion enhancement to film |
DE10234614B3 (de) * | 2002-07-24 | 2004-03-04 | Fractal Ag | Verfahren zur Bearbeitung von Trägermaterial durch Schwerionenbestrahlung und nachfolgenden Ätzprozess |
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- 2005-03-02 BR BRPI0510332-0A patent/BRPI0510332A/pt not_active IP Right Cessation
- 2005-03-02 DE DE502005002731T patent/DE502005002731D1/de active Active
- 2005-03-02 EP EP05729754A patent/EP1754399B1/de active Active
- 2005-03-02 CN CNA2005800135671A patent/CN1961621A/zh active Pending
- 2005-03-02 AT AT05729754T patent/ATE385399T1/de not_active IP Right Cessation
- 2005-03-02 JP JP2007510003A patent/JP2007535154A/ja active Pending
- 2005-03-02 KR KR1020067022684A patent/KR20070004929A/ko not_active Application Discontinuation
- 2005-03-02 US US11/568,495 patent/US20070220745A1/en not_active Abandoned
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US20070220745A1 (en) | 2007-09-27 |
WO2005107348A1 (de) | 2005-11-10 |
EP1754399A1 (de) | 2007-02-21 |
JP2007535154A (ja) | 2007-11-29 |
ATE385399T1 (de) | 2008-02-15 |
KR20070004929A (ko) | 2007-01-09 |
DE502005002731D1 (de) | 2008-03-20 |
BRPI0510332A (pt) | 2007-10-23 |
EP1754399B1 (de) | 2008-01-30 |
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