CN1941410A - 生产高密度半导体功率器件的钴－硅接触绝缘金属工艺 - Google Patents

生产高密度半导体功率器件的钴－硅接触绝缘金属工艺 Download PDF

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CN1941410A
CN1941410A CNA2005101198627A CN200510119862A CN1941410A CN 1941410 A CN1941410 A CN 1941410A CN A2005101198627 A CNA2005101198627 A CN A2005101198627A CN 200510119862 A CN200510119862 A CN 200510119862A CN 1941410 A CN1941410 A CN 1941410A
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cobalt
field effect
effect transistor
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mos field
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常虹
李铁生
戴嵩山
伍明谦
安荷叭剌
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Nations Semiconductor (Cayman) Ltd.
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Abstract

本发明介绍了一种改进的槽沟金属氧化物半导体场效应晶体管(MOSFET)单元，它包含一个由源区包围的槽沟门，源区被漏极区上方的本体区围绕，漏极区位于衬底的底部表面。该MOSFET单元还包含通过保护绝缘层延伸到所述本体区和源区的区域顶部开出的源接触开口。其中，该区域还拥有一层排列在衬底顶部表面附近的钴－硅层。该MOSFET单元还进一步包含一层Ti/TiN导电层，该导电层覆盖源接触开口上方的、与钴－硅层交界的区域。另外，该MOSFET单元还包含一层在Ti/TiN导电层顶部生成的源接触金属层，该导电层可在此随时生成源结合导线。

Description

生产高密度半导体功率器件的钴-硅接触绝缘金属工艺
技术领域
本发明一般涉及半导体功率器件，尤其涉及一种改进的、新的接触绝缘金属工艺，通过改进源接触界面层结构而生产具有改进的源接触电阻的高密度半导体功率器件。
背景技术
自手提电子设备高效金属氧化物半导体(MOS)门器件问世以来，电源转换的应用要求更严格地进一步降低金属氧化物半导体场效应晶体管(MOSFET)器件的开机电阻。为了满足这一要求，人们将较大直径的导线结合在一起来改进半导体晶片与外部引线的连接。采用结合的较大直径导线时，传统工艺生产无论是不用金属绝缘还是与金属接触时使用钛/氮化钛(Ti/TiN)绝缘的槽沟MOSFET便面临技术困难和局限性，特别是不用金属绝缘的高密度槽沟半导体功率器件不能承受这些具有较大直径的结合导线，常常引起损耗和可靠性的问题。这些问题可通过使用Ti/TiN金属绝缘层来改进结合的可靠性和提高生产率而得到一定程度解决。在半导体工业中，Ti/TiN构成的绝缘层被视为一种绝缘金属，用来改进半导体的接触可靠性和防止使源区或本体区到栅电极短路的金属“尖脉冲”或使栅氧化层质量下降的晶体缺陷。图1A显示Ti/TiN绝缘层在一个槽沟MOSFET装置中的实际应用。
Yeh等人在美国专利5,783,493中介绍了利用Ti/TiN绝缘层来改进金属的接触。其中，在接触开口生成一层由Ti/TiN构成的附着层，其上再是一层金属沉积，构成与源/漏极和其它部分的接触。Lin等人在专利6,177,336中公开了一种在半导体衬底上生产MOS晶体管的方法，它包括初始的导电层，再进一步包括一层Ti/TiN绝缘层，该Ti/TiN绝缘层和位于衬底顶部的表面共形。Williams等人在专利6,413,822a中介绍了由一层厚的高压金属堆积层与绝缘层同时形成的Ti和TiN的三明治结构构形。专利5,693,562和5,950,090也介绍了利用Ti/TiN构成的绝缘层改进金属接触可靠性生产半导体器件的方法和装置。
然而，在槽沟MOSFET中使用Ti/TiN金属绝缘层是以降低器件性能为代价的。位于接触界面的Ti/TiN金属绝缘层会在硅-Ti/TiN界面，特别是对于引起较大开机电阻Rdson和临界电压Vt激增以及造成槽沟DMOS器件运行不佳的p-沟道槽沟DMOS器件而言，会产生界面掺杂损失。图1B比较了采用类似工艺但其中一个器件不用金属绝缘而另一个器件在与金属接触时使用钛/氮化钛(Ti/TiN)绝缘的两个p-沟道器件的开机电阻和临界电压，该示意图清楚地显示了它们在开机电阻和临界电压方面的某些变化。开始时，应用Ti/TiN绝缘层试图改进导线结合的可靠性而对器件性能产生的这种负面影响还并未清楚地认识，且常常被忽略，直到最近由于单元尺寸缩小和每个器件单元数量增加而使电阻急剧减小时才得以充分表现出来。
为了克服因使用Ti/TiN金属绝缘层导致半导体功率器件性能下降，生产工艺必须进行改变。为了在相同的临界电压下获得相同的诸如同样的Rds的槽沟DMOS的主要性能，源接触植入剂量不得不增加。然而，这样的工艺改变开销极大，且由于生产成本的上升和随之导致的生产工艺复杂性，这种改变几乎没有多大的实际意义。
因此，在半导体功率器件设计和生产的现有技术领域，仍然存在着探索新的生产方法和新的器件构形的要求，从而生产出能解决上述所讨论的问题和局限性的功率器件。
发明内容
因此，本发明的目的在于提供一种新的、改进的使用钴-硅金属绝缘接触的半导体功率器件，以便解决接触界面掺杂剂丢失的问题，从而克服传统方法的局限性。
具体地说，本发明的目的是提供改进的MOSFET器件，它们通过使用槽沟DMOS的一种新的、独特的CoSi/Ti/TiN金属绝缘结构生产具有槽沟门的MOSFET器件。这种器件的结构构形还有一个独特的工艺，拥有一个较高激励温度的窗，用来克服与导线结合有关的可靠性较差问题和传统半导体功率器件中遇到的因DMOS性能下降而带来的局限性。
本发明的一个较佳实施例简要地介绍了一个槽沟MOSFET单元，它包括一个由源区包围的槽沟门，源区被漏极区上方的本体区围绕，漏极区位于衬底的底部表面。该MOSFET单元还包括通过一个保护绝缘层延伸到本体区和源区的区域顶部开出一个源接触开口，该区域还有一层排列在衬底顶部表面附近的钴-硅层。该MOSFET单元还进一步包括一层在Ti/TiN导电层顶部生成的源接触金属层，该导电层可在此随时生成源结合导线。这个MOSFET还进一步包括一个通过保护绝缘层在槽沟门顶部开口的门接触开口和在电接触槽沟门时覆盖该门开口的Ti/TiN导电层。此外，这个MOSFET还包括一层在Ti/TiN导电层顶部生成的门接触金属层，Ti/TiN导电层可在此随时生成门结合导线。
本领域的普通技术人员在阅读以下多个以图解举例说明的具体实施方式后，他们便会对本发明的这些和另一些目标和优点一目了然。
附图说明
图1A是一个应用Ti/TiN金属绝缘层的传统槽沟DMOS器件的横断面图。
图1B显示因Si-Ti/TiN界面掺杂轮廓变化而引起的Vt和开机电阻的改变。
图2是根据本发明工艺应用CoSi接触绝缘金属工艺生产的一个槽沟DMOS器件的横断面图。
图3显示CoSi和Si-Ti/TiN两个界面上Vt和开机电阻的改变与其因掺杂轮廓变化引起的开机电阻和Vt的变化的比较。
具体实施方式
现在来看图2中关于槽沟DMOS器件100的横断面图。该槽沟DMOS器件100被支撑在含有外延层110的衬底105上，它包括一个位于槽沟118中、含有槽沟壁上方生成的门绝缘层115的槽沟门120。用第二导电率型，如P型掺杂剂掺杂的本体区125延伸到槽沟门120之间，这个环绕源区130的P-本体区125采用第一导电率型，如N+掺杂剂掺杂。环绕槽沟门120的外延层顶部表面附近生成有源区130，延伸到槽沟门顶部、P-本体区125和源区130的半导体衬底顶部表面覆盖着电介质保护层140。槽沟DMOS器件100还包括一个排列于门流槽槽沟118’中的绝缘门流槽120’，该门流槽120’与门120连接，其连接在此未特别地显示出来。
为了实现电接触门120’和源区130，在保护绝缘层140上开有多个接触开口。为了克服源开口中掺杂剂丢失的问题，与Ti/TiN金属绝缘层160交界的表面附近生成有一层钴-硅界面层150，然后在Ti/TiN绝缘层160的顶部生成一层接触金属层170以便生成门和源接触金属。用来接触Ti/TiN金属绝缘层160的CoSi界面层150可消除掺杂剂丢失的问题，从而形成良好的源接触，因源接触电阻增大而引起的掺杂剂丢失和性能下降的问题也可得到解决。图3显示与拥有Si-Ti/TiN界面的器件相比CoSi界面层150显著地改进了器件的开机电阻。
许多标准生产工艺均可用来生成槽沟门、本体区125、源区130、保护绝缘层140和在绝缘层140上开出接触开口。在绝缘层140上开出接触开口后，将100-300埃钴同时喷射到暴露于开口的门流槽120’、源区130和本体区125上，接下来将温度升高到400-800℃左右进行几秒钟快速温度退火(RTA)。本发明公开的首个使用的RTA温度要比对应的CMOS工艺中钴-硅通常生成的温度475℃高得多，这是因为槽沟DMOS不像CMOS那样具有垂直的限制，允许钴合金有较大的深度，实现较好的电阻性接触。湿法蚀刻工艺可用来选择性地从非接触区清除钴。钴湿法蚀刻后使用的第二个RTA温度约为450-800℃，如果第一个RTA温度足够高，可将全部钴转换成硅化钴，则该过程可以忽略跳过。这样，一种独特的、对DMOS器件十分有利的钴-硅界面层150便可生成，能防止导致源接触电阻增大的掺杂剂丢失。第三个RTA使用的温度依据器件性能要求决定，随后喷射Ti/TiN层160。第三个RTA是用来增强金属-金属的界面和释放这两个金属层之间的潜在张力。然后，将AlSiCu或AlCu构成的金属层170喷射到Ti/TiN层160的顶部、成型，生成门和源金属接触层。
根据以上说明，本发明还进一步公开了一种生产槽沟MOSFET单元的方法，它包括一个由源区包围的槽沟门，源区被漏极区上方的本体区围绕，漏极区位于衬底的底部表面。该方法还包括一个步骤，在通过一个保护绝缘层延伸到本体区和源区的区域顶部开出一个源接触开口，该区域还有一层排列在衬底顶部表面附近的钴-硅层。该方法还包括一个生成Ti/TiN导电层的步骤，用来覆盖钴-硅层和源接触开口，并与其结合。该方法还进一步包括在Ti/TiN导电层顶部生成一层接触金属层并使其成型为源金属接触层的步骤，可随时在此生成源结合导线。该方法还进一步包括通过保护绝缘层的槽沟门流槽的顶部开出一个门接触开口的步骤。该方法还进一步包括生成一层Ti/TiN导电层，用来在电接触槽沟门流槽时覆盖门开口的步骤。该方法还包括在Ti/TiN导电层顶部生成一层接触金属层，并使其成型为门金属接触层的步骤，可随时在此生成门结合导线。
在一个较佳的实施例中，在衬底顶部表面附近区域生成钴-硅层的步骤包括在该区域喷射钴离子的过程。在另一个较佳的实施例中，在该区域喷射钴离子的过程还进一步包括喷射约100-300埃厚度钴离子的步骤。在又一个较佳的实施例中，在衬底顶部表面附近的区域生成钴-硅层的步骤还包括继在该区域喷射钴离子后实施钴-硅RTA步骤。在另外一个较佳的实施例中，在衬底顶部表面附近的区域生成钴-硅层的步骤还进一步包括继在该区域喷射钴离子后使用远高于475℃的温度实施首个钴-硅RTA的步骤。在又一个较佳的实施例中，在衬底顶部表面附近的区域生成钴-硅层的步骤还进一步包括继首个钴-硅RTA后实施钴湿法蚀刻的步骤。在另外一个较佳的实施例中，在衬底顶部表面附近的区域生成钴-硅层的步骤还进一步包括继进行钴湿法蚀刻后使用大约450-800℃的温度实施第二次钴-硅RTA的步骤。在另外一个较佳的实施例中，在衬底顶部表面附近的区域生成钴-硅层的步骤还进一步包括继第二次钴-硅RTA后实施第三次钴-硅RTA的步骤。在又一个较佳的实施例中，该方法还包括向覆盖钴-硅区域和源接触开口的MOSFET器件顶部喷射Ti/TiN导电层的步骤。在另外一个较佳的实施例中，该方法还包括向Ti/TiN层顶部喷射AlSiCu或AlCu构成的金属层并使其成型为源接触金属层的步骤。
虽然用当前较佳的实施例对本发明进行了介绍，但必须认识到这种公开绝不能理解为仅仅局限于此。毫无疑问，本领域技术人员阅读以上介绍后便会十分清楚，一定还存在各式各样的修改和变动。因此，期望本发明的真正精神和范围所包括的全部修改和变动能理解为包含在随附的权利要求之中。

Claims (21)

1.一种槽沟金属氧化物半导体场效应晶体管单元，特征在于，其包含一个由源区包围的槽沟门，源区被漏极区上方的本体区围绕，漏极区位于衬底的底部表面；其中，所述的金属氧化物半导体场效应晶体管单元进一步包含：
在通过保护绝缘层延伸到所述本体区和源区的区域顶部开有源接触开口；其中，所述区域还包含排列于所述衬底顶部表面附近的钴-硅层。
2.根据权利要求1所述的槽沟金属氧化物半导体场效应晶体管单元，其特征在于，还进一步包含：
用所述源接触开口上方的钴-硅层覆盖所述区域的一层钛/氮化钛导电层。
3.根据权利要求2所述的槽沟金属氧化物半导体场效应晶体管单元，其特征在于，还进一步包含：
在所述的钛/氮化钛导电层顶部生成的一层源接触金属层，该导电层可在此随时生成源结合导线。
4.根据权利要求1所述的槽沟金属氧化物半导体场效应晶体管单元，其特征在于，还进一步包含：
通过所述保护绝缘层在所述槽沟门顶部开出的一个门接触开口。
5.根据权利要求4所述的槽沟金属氧化物半导体场效应晶体管单元，其特征在于，还进一步包含：
在电接触所述槽沟门时覆盖所述门开口的一层钛/氮化钛导电层。
6.根据权利要求5所述的槽沟金属氧化物半导体场效应晶体管单元，其特征在于，还进一步包含：
在所述的钛/氮化钛导电层顶部生成的一层门接触金属层，该导电层可在此随时生成门结合导线。
7.一种生产槽沟金属氧化物半导体场效应晶体管单元的方法，特征在于，其包括生成一个由源区包围的槽沟门，源区被漏极区上方的本体区围绕，漏极区位于衬底的底部表面的加工步骤；其中，该方法还进一步包括：
在通过保护绝缘层延伸到所述本体区和源区的区域顶部开出源接触开口和在所述衬底顶部表面附近的所述区域生成一层钴-硅层。
8.根据权利要求7所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
生成一层钛/氮化钛导电层，用来覆盖所述的钴-硅层和源接触开口。
9.根据权利要求8所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
在所述钛/氮化钛导电层顶部生成接触金属层并使其成型为源金属接触层，可随时在此生成源结合导线。
10.根据权利要求7所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
通过所述保护绝缘层在所述槽沟门顶部开出门接触开口。
11.根据权利要求10所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
生成一层钛/氮化钛导电层，以便在电接触所述槽沟门时覆盖所述门开口。
12.根据权利要求11所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包含：
在所述钛/氮化钛导电层顶部生成一层接触金属层并使其成型为门金属接触层，可随时在此生成门结合导线。
13.根据权利要求7所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤包括向所述区域喷射钴离子的过程。
14.根据权利要求13所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
向所述区域喷射钴离子的所述过程还包括向所述衬底喷射约100-300埃厚度的所述钴离子。
15.根据权利要求13所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤还包括继向所述区域喷射钴离子过程后进行钴-硅快速温度退火的步骤。
16.根据权利要求13所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤还包括继向所述区域喷射钴离子过程后使用远高于475℃的温度进行首个钴-硅快速温度退火的步骤。
17.根据权利要求16所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤还包括继所述首个钴-硅快速温度退火后进行钴湿法蚀刻的步骤。
18.根据权利要求17所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤还包括继所述钴湿法蚀刻后使用约450-800℃的温度进行第二次钴-硅快速温度退火的步骤。
19.根据权利要求18所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于：
在所述衬底顶部表面附近的所述区域生成一层钴-硅层的所述步骤，还包括继所述第二次钴-硅快速温度退火后进行第三次钴-硅快速温度退火的步骤。
20.根据权利要求13所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
向覆盖所述钴-硅区域和源接触开口的所述金属氧化物半导体场效应晶体管器件顶部喷射一层钛/氮化钛导电层。
21.根据权利要求20所述的生产槽沟金属氧化物半导体场效应晶体管单元的方法，其特征在于，还进一步包括：
向所述钛/氮化钛层喷射一层由AlSiCu或AlCu构成的金属层，并使其成型为源接触金属层。
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