CN1917170A - Semiconductor component of preventing breakdown, and manufacturing method - Google Patents
Semiconductor component of preventing breakdown, and manufacturing method Download PDFInfo
- Publication number
- CN1917170A CN1917170A CN 200510089499 CN200510089499A CN1917170A CN 1917170 A CN1917170 A CN 1917170A CN 200510089499 CN200510089499 CN 200510089499 CN 200510089499 A CN200510089499 A CN 200510089499A CN 1917170 A CN1917170 A CN 1917170A
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- CN
- China
- Prior art keywords
- groove type
- semiconductor element
- plough groove
- punctures
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 230000015556 catabolic process Effects 0.000 title 1
- 238000002955 isolation Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 230000015654 memory Effects 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 150000003376 silicon Chemical class 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Element Separation (AREA)
Abstract
The semiconductor component includes a substrate, multiple groove type components, and at least an isolation region. Being located in the substrate, groove type component includes a region of source electrode/drain electrode. The region of source electrode/drain electrode is collocated on base of the groove type component. Being collocated on the substrate, the isolation region is positioned between regions of source electrodes/drain electrodes of groove type components.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of semiconductor element and manufacture method thereof of puncturing of preventing.
Background technology
Along with the fast development of IC industry, requiring under the more and more higher situation of circuit integration, the design of entire circuit element size also is forced to advance toward the direction that size does not stop to dwindle.When the size of semiconductor element was dwindled gradually, what the distance between the element also can be relative dwindled, and after its distance shortened to certain certain degree, various problems of being derived because of the raising of technology integrated level just can take place.Therefore, how to produce that size is dwindled, high integration, the semiconductor element that can take into account its quality again is the consistent target of industry.
Fig. 1 is the generalized section of existing a kind of plough groove type element.Please refer to Figure 1A, substrate 100 has a plurality of grooves 102, and the plough groove type arrangements of components is in groove 102.The plough groove type element is the plough groove type memory, and this plough groove type memory is made of floating grid 104, dielectric layer 106 and control grid 108.In addition, the plough groove type element also has the source/drain regions 110 that is arranged in floating grid 104, dielectric layer 106 and the 108 below substrates of control grid.
Yet, along with the increase of integrated level, when formation was the grid of material with the doped polycrystalline silicon, alloy wherein can diffuse in the source/drain regions 110, its zone is enlarged, make easily with adjacent source/drain regions 110 and cause abnormal electrical puncture (punch through).Electrically the problem that punctures can cause and produce abnormal electrically conducting between the adjacent grooves formula element, and make element operation speed and element efficiency not good, or even cause element short circuit (short) or open circuit (open), and then influence the rate of finished products and the reliability of whole technology widely.
Summary of the invention
Purpose of the present invention is exactly a kind of manufacture method that prevents the semiconductor element that punctures to be provided, can to form area of isolation between adjacent source/drain regions, avoiding influencing element efficiency because of the problem of the electrical puncture between the element.
Another object of the present invention provides a kind of semiconductor element of puncturing of preventing, the area of isolation between source/drain regions wherein can be avoided producing electrically between the element and punctures.
The present invention proposes a kind of manufacture method that prevents the semiconductor element that punctures, at first, provides a substrate.Then, in substrate, form a layer insulating.Then, with insulating layer patternization, to form a plurality of area of isolation.Next, in substrate, form one deck silicon layer, and cover area of isolation.Then, form groove in the silicon layer between each adjacent area of isolation.Afterwards, in each groove, form the plough groove type element.In addition, the plough groove type element also comprises source, and this source/drain regions is formed in the silicon layer of beneath trenches and between adjacent two area of isolation.
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, the material of above-mentioned insulating barrier for example is a silica.
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, the thickness of above-mentioned insulating barrier for example is between 100 ～1000 .
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, the shape of above-mentioned area of isolation comprises block or strip parallel to each other.
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, the formation method of above-mentioned source/drain regions for example is an ion implantation.
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, above-mentioned plough groove type element for example is the plough groove type memory.
According to the described manufacture method that prevents the semiconductor element that punctures of the embodiment of the invention, can also after forming the plough groove type memory, on silicon layer, form one dielectric layer and covering groove formula memory, and on dielectric layer, form one deck conductor layer.
The present invention also proposes a kind of semiconductor element of puncturing of preventing, this prevents that the semiconductor element that punctures from comprising a substrate, a plurality of plough groove type element and at least one insulating regions.The plough groove type element is arranged in substrate, and wherein the plough groove type element comprises source, and this source/drain regions is disposed at the bottom of plough groove type element.Insulating regions is disposed in the substrate, and between the source/drain regions of each plough groove type element.
According to the described semiconductor element that punctures of preventing of the embodiment of the invention, the thickness of above-mentioned area of isolation is for example between 100 ～1000 .
According to the described semiconductor element that punctures of preventing of the embodiment of the invention, the material of above-mentioned area of isolation for example is a silica.
According to the described semiconductor element that punctures of preventing of the embodiment of the invention, the shape of above-mentioned area of isolation for example is block or strip parallel to each other.
According to the described semiconductor element that punctures of preventing of the embodiment of the invention, above-mentioned plough groove type element for example is the plough groove type memory.
The present invention is because of between two adjacent plough groove type elements, form area of isolation, therefore can prevent that adjacent source/drain regions from carrying out ion implantation technology with when producing the doped polycrystalline silicon grid, because of alloy diffuses to source/drain regions its zone is enlarged, produce the problem of electrical puncture, and further avoid making element efficiency not good, and then have influence on the rate of finished products and the reliability of technology because of electrically puncturing.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing a kind of plough groove type element.
Fig. 2 A to Fig. 2 G is the manufacturing process profile of the semiconductor element that prevented from according to the embodiment of the invention illustrated to puncture.
The simple symbol explanation
100,200: substrate
102,210: groove
104,218: floating grid
106,222,226: dielectric layer
108,224: the control grid
110,220: source/drain regions
202: insulating barrier
204: area of isolation
206: silicon layer
208: patterned mask layer
212: tunneling oxide layer
214,228: conductor layer
216: clearance wall
225: the plough groove type element
Embodiment
Fig. 2 A to Fig. 2 G is the manufacturing process profile of the semiconductor element that prevented from according to the embodiment of the invention illustrated to puncture.Below be that example describes with the plough groove type memory.
At first, please refer to Fig. 2 A, substrate 200 is provided, substrate 200 for example is a silicon base.Then, in substrate 200, form a layer insulating 202.Wherein, the material of insulating barrier 202 for example is a silica, and thickness for example is between 100 ～1000 , and the method for formation for example is a chemical vapour deposition technique.
Then, please refer to Fig. 2 B, utilize photoetching process and etch process, with insulating barrier 202 patternings, in substrate 200, to form area of isolation 204.It should be noted that, area of isolation among the present invention is different with the fleet plough groove isolation structure that is used for being formed with the source region (shallow trench isolation structure), and the degree of depth that area of isolation of the present invention is formed in the substrate is dark than fleet plough groove isolation structure.In addition, the shape of area of isolation 204 can be block or strip parallel to each other.
Then, please continue B, in substrate 200, form one deck silicon layer 206, and cover area of isolation 204 with reference to Fig. 2.Wherein, the formation method of silicon layer 206 for example is a chemical vapour deposition technique.Next, silicon layer 206 is carried out planarization, the method for planarization for example is to use chemical mechanical milling method.Then, on silicon layer 206, form patterned mask layer 208.Wherein, the material of patterned mask layer 208 for example is a silicon nitride.Afterwards, be mask with patterned mask layer 208, etch silicon layer 206 is to form groove 210 in the silicon layer 206 between adjacent two area of isolation 204.
Then, please refer to Fig. 2 C, form tunnel oxide 212 in the surface of groove 210.Wherein, the material of tunnel oxide 212 for example is a silica, and its formation method for example is a thermal oxidation method.Then, on silicon layer 206, form one deck conductor layer 214, and fill up groove 210.Wherein, the material of conductor layer 214 for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step again.
Next, please refer to Fig. 2 D, remove the conductor layer 214 on the patterned mask layer 208.Wherein, the mode that removes for example is a chemical mechanical milling method.Then, carry out the etch-back step, the conductor layer 214 of etching part, the preferable top of conductor layer 214 that makes is higher than the surface of silicon layer 206, and is lower than the surface of patterned mask layer 208.Then, form clearance wall 216, with the surface of cover part conductor layer 214.Wherein, the formation method of clearance wall 216 for example is to form one deck insulation material layer (not illustrating) earlier, utilizes anisotropic etching to remove the SI semi-insulation material layer then.
Then, please refer to Fig. 2 E, is mask with patterned mask layer 208 with clearance wall 216, carries out etch process, to form floating grid 218 on the sidewall of groove 210.Then, in the substrate 200 of groove 210 bottoms, form source/drain regions 220, make source/drain regions 220 between adjacent two area of isolation 204.Wherein, the formation method of source/drain regions 220 for example is an ion implantation technology.Next, in substrate 200, form dielectric layer 222.Wherein, dielectric layer 222 can be a composite bed, from bottom to top is silicon oxide layer, silicon nitride layer and silicon oxide layer in regular turn.Certainly, dielectric layer 222 also may be to include only silicon oxide layer/silicon nitride layer, perhaps only is one deck silicon oxide layer.The formation method of dielectric layer 222 for example is a chemical vapour deposition technique.
Afterwards, please refer to Fig. 2 F, remove the tunnel oxide 212 and dielectric layer 222 of groove 210 base sections, to expose substrate 200.Wherein, the method that removes for example is an anisotropic etching process.Then, in substrate 200, form one deck doped polysilicon layer (not illustrating), remove the doped polysilicon layer of part again with chemical mechanical milling method, to form control grid 224.What deserves to be mentioned is that in the present embodiment, tunnel oxide 212, floating grid 218, dielectric layer 222, control grid 224 and source/drain regions 220 are referred to as plough groove type element 225.
Then, please refer to Fig. 2 G, remove patterned mask layer 208.Then, on plough groove type element 225 and silicon layer 206, form dielectric layer 226.Wherein, the material of dielectric layer 226 for example is a silica.Afterwards, on dielectric layer 226, form conductor layer 228.Wherein, the material of conductor layer 228 for example is a doped polycrystalline silicon.In the present embodiment, conductor layer 228 is intended for the usefulness of word line (word line).
In addition, with plough groove type memory proposed by the invention (shown in Fig. 2 G), because between the source/drain regions in adjacent two plough groove type elements, dispose an area of isolation, can therefore avoid producing undesired electrical puncture between two source/drain regions by this area of isolation, influence element efficiency.
In sum, the present invention is between the source/drain of adjacent two plough groove type memories below, form area of isolation, can avoid increase along with integrated level, forming with the doped polycrystalline silicon is in the step of grid of material, the alloy that is injected can diffuse to source/drain regions, and source/drain regions is enlarged, and causes and produces abnormal electrical puncture between the adjacent element.Simultaneously, also and then avoided because of electrically puncturing the short circuit of the element that causes or open circuit, and influence the rate of finished products and the reliability of whole technology.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (12)
1, a kind of manufacture method that prevents the semiconductor element that punctures comprises:
One substrate is provided;
In this substrate, form an insulating barrier;
This insulating barrier of patterning is to form a plurality of area of isolation;
In substrate, form a silicon layer, and cover those area of isolation;
Form a plurality of grooves in this silicon layer between adjacent two area of isolation; And
Form a plough groove type element in each those groove, wherein this plough groove type element comprises source, is formed in this silicon layer of this beneath trenches and between adjacent two area of isolation.
2, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the material of this insulating barrier comprises silica.
3, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the thickness of this insulating barrier is between 100 ～1000 .
4, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the shape of those area of isolation comprises block or strip parallel to each other.
5, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the formation method of those source/drain regions comprises ion implantation.
6, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein those plough groove type elements comprise the plough groove type memory.
7, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 6 also comprises:
After forming those plough groove type memories, on this silicon layer, form a dielectric layer, and cover those plough groove type memories; And
On this dielectric layer, form a conductor layer.
8, a kind of semiconductor element of puncturing of preventing comprises:
One substrate;
A plurality of plough groove type elements are arranged in this substrate, and wherein this plough groove type element comprises source, and this source/drain regions is disposed at the bottom of this plough groove type element; And
At least one area of isolation is disposed in this substrate, and between this source/drain regions of those plough groove type elements.
9, the semiconductor element that punctures of preventing as claimed in claim 8, wherein the thickness of this area of isolation is between 100 ～1000 .
10, the semiconductor element that punctures of preventing as claimed in claim 8, wherein the material of this area of isolation comprises silica.
11, the semiconductor element that punctures of preventing as claimed in claim 8, wherein the shape of this area of isolation comprises bulk or strip.
12, the semiconductor element that punctures of preventing as claimed in claim 8, wherein this plough groove type element comprises the plough groove type memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100894999A CN100385646C (en) | 2005-08-19 | 2005-08-19 | Semiconductor component of preventing breakdown, and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100894999A CN100385646C (en) | 2005-08-19 | 2005-08-19 | Semiconductor component of preventing breakdown, and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1917170A true CN1917170A (en) | 2007-02-21 |
| CN100385646C CN100385646C (en) | 2008-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100894999A Expired - Fee Related CN100385646C (en) | 2005-08-19 | 2005-08-19 | Semiconductor component of preventing breakdown, and manufacturing method |
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Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2735193B2 (en) * | 1987-08-25 | 1998-04-02 | 株式会社東芝 | Nonvolatile semiconductor device and method of manufacturing the same |
| CN1280891C (en) * | 2001-12-31 | 2006-10-18 | 台湾茂矽电子股份有限公司 | Non-volatile storage structure and its manufacturing method |
| CN1271717C (en) * | 2002-08-02 | 2006-08-23 | 上海宏力半导体制造有限公司 | Structure of channel shielded Rom memory unit and producing method thereof |
| JP2005116592A (en) * | 2003-10-03 | 2005-04-28 | Takehide Shirato | Field effect transistor |
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| CN100385646C (en) | 2008-04-30 |
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Granted publication date: 20080430 |