CN1949519A - Dynamic random access memory and mfg. method thereof - Google Patents
Dynamic random access memory and mfg. method thereof Download PDFInfo
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- CN1949519A CN1949519A CN200510106792.1A CN200510106792A CN1949519A CN 1949519 A CN1949519 A CN 1949519A CN 200510106792 A CN200510106792 A CN 200510106792A CN 1949519 A CN1949519 A CN 1949519A
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- 238000000034 method Methods 0.000 title claims description 91
- 239000000758 substrate Substances 0.000 claims abstract description 132
- 239000003990 capacitor Substances 0.000 claims abstract description 61
- 239000004020 conductor Substances 0.000 claims description 143
- 238000003973 irrigation Methods 0.000 claims description 82
- 230000002262 irrigation Effects 0.000 claims description 82
- 239000000463 material Substances 0.000 claims description 66
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 238000002955 isolation Methods 0.000 claims description 37
- 238000004519 manufacturing process Methods 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 239000004575 stone Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000001459 lithography Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
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- 239000003989 dielectric material Substances 0.000 description 2
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- 238000005468 ion implantation Methods 0.000 description 1
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- 229910000464 lead oxide Inorganic materials 0.000 description 1
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention is a dynamic random access memory (DRAM), comprising substrate, active component and deep tunnel capacitor, where the substrate has tunnel and deep tunnel; the active component is arranged on the substrate and comprises grid structure and doping region, the grid structure is arranged on the substrate and filled in the tunnels and the doping region is arranged in the substrate on the first side of the grid; the deep tunnel capacitor is arranged in the deep tunnel in the substrate on the second side of the grid; the first and second sides are opposite to each other; and electrodes on the deep tunnel capacitor are adjacent to the tunnel bottom.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relevant for a kind of dynamic random access memory and manufacture method thereof.
Background technology
Along with the function of computer microprocessor (Microprocessor) now is more and more strong, program that software carried out and computing are also more and more huge.Therefore, the manufacturing technology of memory has become one of semiconductor industry important techniques.
In general, memory can be divided into volatile storage and non-volatility memorizer according to the kenel of its storage data.And dynamic random access memory (Dynamic Random Access Memory DRAM) promptly belongs to a kind of volatile storage, and it is made of a plurality of memory cell.And each memory cell is made of an active element and a capacitor, and each memory cell (Word Line, WL) (Bit Line BL) is electrically connected to each other with bit line by word line.
On the other hand, dynamic random access memory mainly can be divided into two kinds of forms according to the structure of its capacitor, one is for having the dynamic random access memory of stacked capacitor (Stack Capacitor), and another is then for having the dynamic random access memory of deep trenches formula capacitor (Deep Trench Capacitor).Owing to have the dynamic random access memory of deep trenches formula capacitor, its deep trenches formula capacitor is to be formed among the substrate, therefore compared to dynamic random access memory with stacked capacitor, on making, be difficult for producing the problem of planarization, thereby help the making of undersized memory component.But, when component size more and more hour, the dynamic random access memory with deep trenches formula capacitor equally also suffers from more and more many problems.
Figure 1A illustrate is the vertical view of existing a kind of deep trenches formula dynamic random access memory.Figure 1B illustrate is the profile of existing a kind of deep trenches formula dynamic random access memory, wherein Figure 1B illustrate among Figure 1A along the section of A-A ' line.
Please refer to Figure 1A and Figure 1B, dynamic random access memory comprises ditching type capacitor 102, shallow-channel isolation region 104, active element 106 and flush type conductive strips 108 (buried strap).Ditching type capacitor 102 is arranged in substrate 100, and it comprises bottom electrode 110, dielectric layer 112, top electrode 114 (being made of conductor layer 114a, conductor layer 114b and conductor layer 114c).Between conductor layer 114b and substrate 100, be provided with neck oxide layer (collar oxide) 116.In addition, shallow-channel isolation region 104 is arranged in substrate 100, and the shallow-channel isolation region 104 of part is arranged in ditching type capacitor 102.In addition, active element 106 is positioned at substrate 100 tops, and it comprises source electrode 118a/ drain electrode 118b and grid structure 120 (comprising gate dielectric layer 120a, grid 120b and cap layer 120c), and this active element 106 is electrically connected with flush type conductive strips 108.Source electrode 118a is electrically connected with bit line 126 via connector 124.Be provided with clearance wall 122 at grid structure 120 sidewalls.
Yet, in the above-mentioned dynamic random access memory, because active element 106 normally utilizes lithography technology to make, therefore the channel region length d of active element 106 can be subjected to the restriction of lithography technology and can't further dwindle, and makes the element integrated level further to promote.On the other hand, the channel region length d dwindles the problem that also can produce active element start voltage deviation and so-called short-channel effect.In order to solve the above problems, existing a kind of method is the concentration of dopant that improves in the raceway groove of active element, but this kind practice can increase a junction leakage (field junctionleakage) on the contrary, and influences the reliability of element.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of dynamic random access memory and manufacture method thereof exactly, can make the channel length of active element can not be subject to lithography technology, and can the lift elements integrated level.
Purpose of the present invention is providing a kind of dynamic random access memory and manufacture method thereof exactly, and this kind manufacture method is simple, and can reduce cost of manufacture.
The invention provides a kind of dynamic random access memory, comprise substrate, active element and deep trenches formula capacitor.Substrate has trench isolation regions and deep trenches.Active element is arranged on the substrate, and this active element comprises grid structure and doped region.Grid structure is provided with on the substrate, and fills up irrigation canals and ditches.Doped region is arranged in the substrate of first side of grid structure.Deep trenches formula capacitor is arranged in this deep trenches of this substrate of second side of grid, and second side is relative with first side, and the top electrode of deep trenches formula capacitor is in abutting connection with the irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, deep trenches formula capacitor comprises bottom electrode, top electrode and capacitance dielectric layer.Bottom electrode is arranged in the deep trenches substrate of bottom portion.Top electrode is arranged in the deep trenches.Capacitance dielectric layer is arranged on the sidewall and the bottom of deep trenches.
In above-mentioned dynamic random access memory, top electrode comprises first conductor layer, second conductor layer and the 3rd conductor layer.First conductor layer is arranged at the deep trenches bottom.Second conductor layer is arranged on first conductor layer.The 3rd conductor layer is arranged on second conductor layer, and in abutting connection with the irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, more comprise the neck dielectric layer, be arranged at the deep trenches sidewall on first conductor layer, and around second conductor layer.The material of neck dielectric layer comprises silica.In above-mentioned dynamic random access memory, more comprise the flush type conductive strips, in abutting connection with the 3rd conductor layer and irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, capacitance dielectric layer is arranged between the sidewall and bottom of first conductor layer and deep trenches.
In above-mentioned dynamic random access memory, the material of first conductor layer, second conductor layer and the 3rd conductor layer comprises doped polycrystalline silicon.
In above-mentioned dynamic random access memory, grid structure comprises grid and gate dielectric layer.Grid is provided with on the substrate, and fills up irrigation canals and ditches.Gate dielectric layer is arranged between grid and the substrate.The material of gate dielectric layer comprises silica.
The invention provides a kind of dynamic random access memory, comprise substrate, two grid structures, doped region, two deep trenches formula capacitors.Substrate has two irrigation canals and ditches and two deep trenches at least, and two irrigation canals and ditches are arranged between two deep trenches.Two grid structures are arranged on the substrate between two deep trenches, and fill up two irrigation canals and ditches respectively.Doped region is arranged in the substrate between two grid structures.Two deep trenches formula capacitors are provided with respectively in two deep trenches of substrate, and the top electrode of two deep trenches formula capacitors is respectively in abutting connection with two irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, deep trenches formula capacitor comprises bottom electrode, top electrode and capacitance dielectric layer.Bottom electrode is arranged in the deep trenches substrate of bottom portion.Top electrode is arranged in the deep trenches.Capacitance dielectric layer is arranged on the sidewall and the bottom of deep trenches.
In above-mentioned dynamic random access memory, top electrode comprises first conductor layer, second conductor layer and the 3rd conductor layer.First conductor layer is arranged at the deep trenches bottom.Second conductor layer is arranged on first conductor layer.The 3rd conductor layer is arranged on second conductor layer, and in abutting connection with the irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, more comprise the neck dielectric layer, be arranged at the deep trenches sidewall on first conductor layer, and around second conductor layer.The material of neck dielectric layer comprises silica.
In above-mentioned dynamic random access memory, more comprise the flush type conductive strips, in abutting connection with the 3rd conductor layer and irrigation canals and ditches bottom.
In above-mentioned dynamic random access memory, capacitance dielectric layer is arranged between the sidewall and bottom of first conductor layer and deep trenches.
In above-mentioned dynamic random access memory, the material of first conductor layer, second conductor layer and the 3rd conductor layer comprises doped polycrystalline silicon.
In above-mentioned dynamic random access memory, grid structure comprises grid and gate dielectric layer.Grid is provided with on the substrate, and fills up irrigation canals and ditches.Gate dielectric layer is arranged between grid and the substrate.The material of gate dielectric layer comprises silica.
In dynamic random access memory of the present invention, because the active element below is provided with irrigation canals and ditches, and the grid of active element is inserted in the irrigation canals and ditches, and the top electrode of deep trenches formula capacitor is in abutting connection with the bottom of irrigation canals and ditches, thus active element be with trench sidewall and doped region to the zone between the top electrode of deep trenches formula capacitor as channel region (rectilinear channel region).Because the channel region of active element is to be arranged in the substrate of trench sidewall (rectilinear channel region), therefore the width of grid on substrate of active element can dwindle and can increase the element integrated level, and can control the length of channel region exactly, and then the problem that is produced can avoid component size to dwindle the time by the degree of depth of control irrigation canals and ditches.
In dynamic random access memory of the present invention, because the some of the grid of active element is arranged in the irrigation canals and ditches of substrate, so the channel length of active element can not be subject to lithography technology, and can the lift elements integrated level.And, control the length of channel region, the problem that is produced in the time of also can avoiding component size to dwindle exactly by the degree of depth of the irrigation canals and ditches of control active element below.
The invention provides a kind of manufacture method of dynamic random access memory, substrate at first is provided, formed first mask layer and the deep trenches that is formed in the substrate of patterning on this substrate, and first mask layer of patterning exposes deep trenches.Then, in deep trenches, form deep trenches formula capacitor, and deep trenches formula capacitor comprises bottom electrode, top electrode, capacitance dielectric layer.In first mask layer and substrate, form component isolation structure, to define active area.Remove first mask layer on the active area, after exposing substrate, on the substrate that exposes, form semiconductor material layer.Patterned semiconductor material layer and substrate are to form irrigation canals and ditches, the top electrode of the bottom contiguous ditching type capacitor of these irrigation canals and ditches.Form grid structure on substrate, this grid structure fills up irrigation canals and ditches.Afterwards, in the substrate of grid structure one side, form doped region.
In the manufacture method of above-mentioned dynamic random access memory, the material of semiconductor material layer is a polysilicon.
In the manufacture method of above-mentioned dynamic random access memory, the step that forms deep trenches formula capacitor in deep trenches is to form bottom electrode earlier in the deep trenches substrate of bottom portion.After the deep trenches surface forms capacitance dielectric layer, insert first conductor layer in the deep trenches bottom, and remove the capacitance dielectric layer that is not covered by first conductor layer.Then, on the deep trenches sidewall that is not covered, form the neck oxide layer by first conductor layer, and insert second conductor layer in deep trenches to cover first conductor layer.Remove part second conductor layer and top oxide layer, make the second conductor layer surface be lower than substrate surface after, insert the 3rd conductor layer in deep trenches, wherein first conductor layer, second conductor layer and the 3rd conductor layer constitute top electrode.
In the manufacture method of above-mentioned dynamic random access memory, more be included in and form the flush type conductive strips in the substrate, in abutting connection with the 3rd conductor layer and irrigation canals and ditches bottom.
In the manufacture method of above-mentioned dynamic random access memory, be to form gate dielectric layer on prior to substrate in the step that forms grid structure on the substrate.Then, form conductor layer on gate dielectric layer, this conductor layer fills up irrigation canals and ditches.Afterwards, patterning conductor layer and gate dielectric layer.
In the manufacture method of above-mentioned dynamic random access memory, more be included in the grid structure sidewall and form clearance wall.
In the manufacture method of above-mentioned dynamic random access memory, more be included in and form the bit line that is electrically connected this doped region on the substrate.
In the manufacture method of above-mentioned dynamic random access memory, patterned semiconductor material layer and substrate are to comprise in the step that forms irrigation canals and ditches prior to forming second mask layer, cover part active area on the substrate.Then, be mask with component isolation structure layer by layer with second mask, remove part semiconductor material layer and substrate after, remove second mask layer.
In the manufacture method of dynamic random access memory of the present invention, because component isolation structure and mask layer with high, therefore when removing mask layer, can not cause component isolation structure to have depression to produce (recess).And, after component isolation structure forms, utilize brilliant method of heap of stone to form semiconductor material layer, and it is high together that the semi-conducting material laminar surface is risen to component isolation structure.Because component isolation structure exceeds substrate surface, and channel region is formed in the semiconductor material layer, and therefore the degree of depth of the component isolation structure under substrate surface does not need to do too deeply, and technology is oversimplified.And, because the process integration of the technology of making active element and shallow slot isolation structure is together, therefore can simplify technology.
And, in the manufacture method of dynamic random access memory of the present invention, when forming irrigation canals and ditches since with second mask layer and component isolation structure as alignment mask, so can increase process margin.
In addition, in the manufacture method of dynamic random access memory of the present invention, because the some of the grid of active element is formed in the irrigation canals and ditches of substrate, so the channel length of active element can not be subject to lithography technology, and can the lift elements integrated level.And, control the length of channel region, the problem that is produced in the time of also can avoiding component size to dwindle exactly by the degree of depth of the irrigation canals and ditches of control active element below.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A illustrate is the vertical view of existing a kind of deep trenches formula dynamic random access memory;
Figure 1B illustrate is the profile of existing a kind of deep trenches formula dynamic random access memory;
Fig. 2 A illustrate is the vertical view of the deep trenches formula dynamic random access memory of a preferred embodiment of the present invention;
Fig. 2 B illustrate is the profile of deep trenches formula dynamic random access memory of the present invention;
The manufacturing process profile of a kind of DRAM cell of the preferred embodiment of the present invention that Fig. 3 A to Fig. 3 J is illustrated.
Description of reference numerals
100,200,300: substrate
102,206: ditching type capacitor
104: shallow-channel isolation region
106,204: active element
108,226,322: the flush type conductive strips
110,222,308: bottom electrode
112: dielectric layer
114,218: top electrode
114a, 114b, 114c, 218a, 218b, 218c, 312,316,318,334: conductor layer
116,224,314: the neck oxide layer
118a: source electrode
118b: drain electrode
120,212,338: grid structure
120a, 212a, 332: gate dielectric layer
120b, 212b: grid
120c, 212c, 336: cap layer
122,216,340: clearance wall
124,228,344: connector
126,230,346: bit line
202,324: component isolation structure
208,306: deep trenches
210,330: irrigation canals and ditches
214,342: doped region
214a: heavily doped region
214b: light doping section
220,310: capacitance dielectric layer
302: bed course
304,328: mask layer
325: active area
326: semiconductor material layer
334a: doped polysilicon layer
334b: metal silicide layer
Embodiment
Fig. 2 A illustrate is the vertical view of the deep trenches formula dynamic random access memory of a preferred embodiment of the present invention.Fig. 2 B illustrate is the profile of deep trenches formula dynamic random access memory of the present invention, wherein Fig. 2 B illustrate among Fig. 2 A along the section of B-B ' line.
Please refer to Fig. 2 A and Fig. 2 B, dynamic random access memory comprises substrate 200, component isolation structure 202, active element 204 and deep trenches formula capacitor 206.
Substrate 200 for example is a silicon substrate.For example be to be provided with deep trenches 208 and irrigation canals and ditches 210 in substrate 200.The degree of depth of deep trenches 208 for example is the degree of depth greater than irrigation canals and ditches 210.
Component isolation structure 202 for example is to be arranged on the substrate 200, to define active area.Component isolation structure 202 for example is a shallow slot isolation structure.
Active element 204 for example is to be arranged on the substrate 200.Active element 204 comprises grid structure 212 and doped region 214.
Grid structure 212 is made of gate dielectric layer 212a, grid 212b.Grid 212b is provided with on the substrate 200, and fills up irrigation canals and ditches 210.The material of grid 212b for example is a doped polycrystalline silicon.Gate dielectric layer 212a is arranged between grid 212b and the substrate 200.The material of gate dielectric layer 212a for example is a silica.On grid 212b, also can look actual needs and be provided with cap layer 212c.The material of cap layer 212c comprises insulating material, for example is silica or silicon nitride etc.Also can look actual needs and be provided with clearance wall 216 at the sidewall of grid structure 212.The material of clearance wall 216 comprises insulating material, for example is silica or silicon nitride etc.
Doped region 214 for example is to be arranged in the substrate 200 of a side of grid 212.Doped region 214 is made of heavily doped region 214a and light doping section 214b.Light doping section 214b is arranged in the substrate 200 of clearance wall 216 belows.Doped region 214 for example is N type doped region or P type doped region.
Deep trenches formula capacitor 206 for example is to be arranged in the deep trenches 208 of substrate 200 of opposite side of grid 212.That is deep trenches formula capacitor 206 is provided with respectively in the substrate 200 of grid 212 both sides with doped region 214.
Deep trenches formula capacitor 206 is made of top electrode 218, capacitance dielectric layer 220, bottom electrode 222.Top electrode 218 for example is in abutting connection with irrigation canals and ditches 210 bottoms.In the present embodiment, top electrode 218 is made of conductor layer 218a, 218b, 218c.Conductor layer 218c is arranged at deep trenches 208 bottoms.Conductor layer 218b is arranged on the conductor layer 218c.Conductor layer 218a is arranged on the conductor layer 218b, and in abutting connection with irrigation canals and ditches 210 bottoms.The material of conductor layer 218a, 218b, 218c for example is a doped polycrystalline silicon.
The bottom electrode 222 of deep trenches formula capacitor 206 for example is arranged in deep trenches 208 substrate of bottom portion 200.Bottom electrode 222 for example is a doped region.Capacitance dielectric layer 220 for example is arranged on the sidewall and the bottom of deep trenches 206.That is capacitance dielectric layer 220 for example is to be arranged between conductor layer 218c and the bottom electrode 222 (substrate 200).Neck oxide layer 224 for example is arranged between conductor layer 218b and the substrate 200.The material of neck oxide layer 224 for example is a silica.
In addition, for example be more to be provided with flush type conductive strips 226 contiguous conductor layer 218a and irrigation canals and ditches 210 bottoms in substrate 200.And, for example be to be provided with bit line 230 on substrate 200, doped region 214 for example is to be electrically connected with bit line 230 via connector 228.
In above-mentioned dynamic random access memory, because active element 204 belows are provided with irrigation canals and ditches 210, and the grid 212b of active element 204 inserts in the irrigation canals and ditches 210, and the top electrode 218 of deep trenches formula capacitor 206 is in abutting connection with the bottom of irrigation canals and ditches 210, thus active element 204 be with irrigation canals and ditches 210 sidewalls and doped region 214 to the zone between the top electrode 218 of deep trenches formula capacitor 206 as channel region 232 (rectilinear channel region).Because the channel region 232 of active element 204 is to be arranged in the substrate 200 of irrigation canals and ditches 210 sidewalls (rectilinear channel region), therefore the width of grid on substrate 200 of active element 204 can dwindle and can increase the element integrated level, and can control the length of channel region 232 exactly, and then the problem that is produced can avoid component size to dwindle the time by the degree of depth of control irrigation canals and ditches 210.
In the above embodiment of the present invention, the top electrode of deep trenches formula capacitor is to do explanation by three layers of conductor layer (conductor layer 218a, 218b, 218c) example that constituted, certainly the top electrode of deep trenches formula capacitor also can be that the conductor layer more than three layers constitutes even by one deck conductor layer, two-layer conductor layer.And, if active element 204 is positioned at the top electrode 218 that the part of the bottom of irrigation canals and ditches 210 directly is electrically connected deep trenches formula capacitor 206, just do not need to be provided with flush type conductive strips 226 certainly.
In addition, in the above description, have only the explanation of single deep trenches formula DRAM cell.But shown in Fig. 2 B, deep trenches formula DRAM cell normally with two one group, forms mirror configuration.Two irrigation canals and ditches 210 can be arranged between two deep trenches 208.Two active elements 204 are arranged on the substrate 200 between two deep trenches, and fill up two irrigation canals and ditches 210.Doped region 214 is arranged in two substrates 100 between the active element 204.Two active elements 204 are shared a doped region 214.
In dynamic random access memory of the present invention, because the some of the grid of active element is arranged in the irrigation canals and ditches of substrate, the channel length of active element can be decided by the degree of depth of irrigation canals and ditches, therefore the channel length of active element can not be subject to lithography technology, and can the lift elements integrated level.And, control the length of channel region, the problem that is produced in the time of also can avoiding component size to dwindle exactly by the degree of depth of the irrigation canals and ditches of control active element below.
Then, please refer to the manufacturing process profile of a kind of DRAM cell of the preferred embodiment of the present invention that Fig. 3 A to Fig. 3 J illustrated, it is in order to illustrate the manufacture method of DRAM cell of the present invention.
At first, please refer to Fig. 3 A, substrate 300 is provided, substrate 300 for example is a silicon substrate.After forming one deck bed course 302 on the substrate 300, on bed course 302, form one deck mask layer 304.The material of bed course 302 for example is a silica, and its formation method for example is to carry out thermal oxidation technology.In addition, the material of mask layer 304 for example is a silicon nitride, and its formation method for example is to carry out chemical vapour deposition (CVD) (ChemicalVapor Deposition, CVD) technology.
Then, mask layer 304 and bed course 302 are carried out lithography process and etch process, with bed course 302 and the mask layer 304 that forms patterning.Then, be mask with the mask layer 304 and the bed course 302 of patterning, carry out etch process, to form deep trenches 306 in substrate 300, wherein the etch process that is carried out for example is a dry etch process.
Afterwards, in deep trenches 306 substrate of bottom portion 300, form bottom electrode 308.Wherein, bottom electrode 308 for example is a doped region, and its formation method for example is the sidewall formation one deck doping insulating barrier prior to deep trenches 306 bottoms, then, inserts one deck photoresist layer in deep trenches 306.Then, remove the doping insulating barrier that is not covered, and the photoresist layer is removed by the photoresist layer.Afterwards, form a conformal layer insulating after, carry out thermal process, so that to substrate 300, continue insulating barrier and doping insulating barrier are removed of the diffuse dopants in the doping insulating barrier.In a preferred embodiment, the dopant kenel of bottom electrode 308 for example is the n type.Detailed making about bottom electrode 308 is well known to those skilled in the art, and repeats no more in this.
Then, please refer to Fig. 3 B, form capacitance dielectric layer 310 and conductor layer 312 in deep trenches 306 bottoms.For instance, capacitance dielectric layer 310 is as described below with the formation method of conductor layer 312.Prior to forming one dielectric layer (not illustrating) on the substrate 300, the material of this dielectric layer for example is silica, silicon nitride, silicon oxynitride or other suitable dielectric material, and its formation method for example is to carry out thermal oxidation technology, chemical vapor deposition method or other suitable technology.On substrate 300, form conductor layer 312 then, and the dielectric layer of cover part.The material of conductor layer 312 for example is polysilicon, doped polycrystalline silicon or other suitable conductor material, and its formation method for example is the mode with (In-Situ) dopant ion of coming personally, utilize chemical vapour deposition technique after forming one deck doped polysilicon layer on the substrate 200, remove beyond the deep trenches 306 and the doped polysilicon layer of the part at deep trenches 306 tops, and form it.The method that removes of doped polysilicon layer for example is to carry out dry etch process or wet etch process.Continue it, remove the dielectric layer that is not covered, to form capacitance dielectric layer 310 by conductor layer 312.The method that removes of dielectric layer for example is to carry out dry etch process or wet etch process.The material of capacitance dielectric layer 310 for example is silica, silicon nitride, silicon oxynitride or other suitable dielectric material, and its formation method for example is to carry out thermal oxidation technology, chemical vapor deposition method or other suitable technology.
Then, please refer to Fig. 3 C, on deep trenches 306 sidewalls that do not covered, form neck oxide layer 314 by conductor layer 312.Wherein, the material of neck oxide layer 314 for example is a silica, and its formation method for example is to carry out chemical vapor deposition method earlier, to form a conformal neck oxidation material layer, remove beyond the deep trenches 306 afterwards again and the neck oxidation material layer at conductor layer 312 tops, and form it.Wherein, the method that removes part neck oxidation material layer for example is to carry out an anisotropic etch process.
Then, insert conductor layer 316 in deep trenches 306, it also covers conductor layer 312, and this conductor layer 316 is electrically connected with conductor layer 312.Remove segment conductor layer 316 then and lead oxide layer 314, make conductor layer 316 and neck oxide layer 314 be lower than substrate 300 surfaces with part.Similar about the material of conductor layer 316 and relevant formation method and conductor layer 312, and in aforementioned content, conductor layer 312 is explained, so repeat no more in this.
Then, please refer to Fig. 3 D, insert conductor layer 318 in deep trenches 306, it also covers conductor layer 314, and this conductor layer 318 is electrically connected with conductor layer 314.Similar about the material of conductor layer 318 and relevant formation method and conductor layer 312, and in aforementioned content, conductor layer 312 is explained, so repeat no more in this.
Then, carry out the related process of active element.Please refer to Fig. 3 E, in the substrate 300 of a side of conductor layer 318, form irrigation canals and ditches 320, and irrigation canals and ditches 320 expose part substrate 300 and conductor layer 316,318.Wherein, the formation method of irrigation canals and ditches 320 for example is to carry out etch process.After irrigation canals and ditches 320 form, visual actual needs and form flush type conductive strips 322.The formation method of flush type conductive strips 322 for example is an ion implantation.
Please refer to Fig. 3 F, in irrigation canals and ditches 320, insert insulating material and form component isolation structure 324, and define active area 325.The material of component isolation structure 324 for example is silica or other suitable material as passage.The formation method of component isolation structure 324 for example be carry out earlier depositing operation form fill up one deck insulation material layer of irrigation canals and ditches 320 after, utilize chemical mechanical polishing method or etch-back method to remove SI semi-insulation material layer beyond the irrigation canals and ditches 320, and form it.
Afterwards, please refer to Fig. 3 G, remove mask layer 304 and bed course 302 to expose substrate 300.On substrate 300, form semiconductor material layer 326 then.The material of semiconductor material layer 326 for example is a polysilicon.The formation method of semiconductor material layer 326 for example is a selectivity brilliant method of heap of stone.Crystal silicon of heap of stone will optionally be grown up on the surface with silicon, and the crystal silicon of heap of stone after growing up will have with its under the same lattice position of silicon material to (crystal orientation).Carry out a flatening process afterwards, make semiconductor material layer 316 and component isolation structure 324 have a smooth in fact surface.
Then, please refer to Fig. 3 H, expose part semiconductor material layer 326 in forming on one deck mask layer 328 on the substrate 300.Mask layer 328 for example is a patterning photoresist layer.The formation method of mask layer 328 for example is after forming earlier one deck photoresist layer, forms it through overexposure, development.Be mask with mask layer 328 and component isolation structure 324 then, etching semiconductor material layer 326 forms irrigation canals and ditches 330 with substrate 300.Wherein irrigation canals and ditches 330 need expose flush type conductive strips 322 at least.Because, component isolation structure 324 is just to complete before irrigation canals and ditches 330 form, and be to be alignment mask when forming irrigation canals and ditches 330 with mask layer 328 and component isolation structure 324, can cover the part active area as long as therefore be positioned at the pattern form of the mask layer 328 on the semiconductor material layer 326, not have any restriction.For instance, the pattern form of mask layer 328 can be strip, circle or oval.If mask layer 328 is circular or oval, then can increase grid width.
Then, please refer to Fig. 3 I, remove after the mask layer 328, on substrate 300, form gate dielectric layer 332, to cover exposed semiconductor material layer 326 and substrate 300 surfaces.The material of gate dielectric layer 332 for example is a silica, and its formation method for example is thermal oxidation method or chemical vapour deposition technique.Then, form conductor layer 334 on substrate 300, covering gate dielectric layer 332 also fills up irrigation canals and ditches 330.The material of conductor layer 334 for example is multi-crystal silicification metal (polycide), and it is made of one deck doped polysilicon layer 334a and layer of metal silicide layer 334b.After the formation method of multi-crystal silicification metal for example is to form one deck doped polysilicon layer with chemical vapour deposition technique earlier, direct plated metal silicide on doped polysilicon layer, its material for example is tungsten silicide or titanium silicide.Certainly, conductor layer 334 also can be made of the simple layer conductor material, perhaps is made of two-layer above conductor material.
Then, on conductor layer 334, form one deck cap layer 336.The material of this cap layer 336 comprises insulating material, for example is silicon nitride or silica.The formation method of cap layer 336 for example is a chemical vapour deposition technique.
Continue it, please refer to Fig. 3 J, patterning cap layer 336, conductor layer 334, gate dielectric layer 332 are to form grid structure 338.Then, the sidewall in grid structure 338 forms clearance wall 340.The material of clearance wall 340 comprises insulating material, for example is silicon nitride or silica.The formation method of clearance wall 340 for example is after forming one deck insulation material layer with chemical vapour deposition technique earlier, to carry out anisotropic etch process to form it.Then, in the substrate 300 of grid structure 338 1 sides, form doped region 342.In addition, after doped region 342 formed, more the interconnecting process that can be correlated with by contact hole 344, made doped region 342 be electrically connected with conductor layer 346 (bit line).
In the manufacture method of dynamic random access memory of the present invention, the top electrode of deep trenches formula capacitor is to be that example is done explanation to form three layers of conductor layer (conductor layer 312,314,316), certainly the top electrode of deep trenches formula capacitor also can be that the conductor layer more than three layers constitutes even by one deck conductor layer, two-layer conductor layer.And, if active element is positioned at the top electrode 318 that the part of the bottom of irrigation canals and ditches 330 directly is electrically connected deep trenches formula capacitor, just do not need to form flush type conductive strips 322 certainly.
And, in the manufacture method of dynamic random access memory of the present invention,, therefore when removing mask layer 304, can not cause component isolation structure 324 that depression generation (recess) is arranged with bed course 302 because component isolation structure 324 is high together with mask layer 304.And, after component isolation structure 324 forms, utilize brilliant method of heap of stone to form semiconductor material layer 326, and it is high together that semiconductor material layer 326 surfaces are risen to component isolation structure 324.Because component isolation structure 324 exceeds substrate 300 surfaces, and channel region is formed in the semiconductor material layer 326, and therefore the degree of depth at substrate 300 subsurface component isolation structures does not need to do too deeply, and technology is oversimplified.And, because the process integration of the technology of making active element and shallow slot isolation structure is together, therefore can simplify technology.
In addition, in the manufacture method of dynamic random access memory of the present invention, when forming irrigation canals and ditches 330 since with mask layer 328 and component isolation structure 324 as alignment mask, therefore can increase process margin.
And, in the manufacture method of dynamic random access memory of the present invention, because the some of the grid of active element is formed in the irrigation canals and ditches of substrate, the channel length of active element can be decided by the degree of depth of irrigation canals and ditches, therefore the channel length of active element can not be subject to lithography technology, and can the lift elements integrated level.And, control the length of channel region, the problem that is produced in the time of also can avoiding component size to dwindle exactly by the degree of depth of the irrigation canals and ditches of control active element below.
In addition, the related process of above-mentioned disclosed deep trenches formula capacitor is not in order to limit the present invention only in order to explanation the present invention.In other words, in other embodiments, also can utilize other deep trenches formula capacitor technology to finish after the deep trenches formula capacitor earlier, carry out the related process of the active element of the present invention such as Fig. 3 E to Fig. 3 J again, the channel region length that also can solve existing active element equally like this can be subjected to the restriction of lithography technology and can't further dwindle, and makes the element integrated level further to promote; And the problem of active element start voltage deviation and so-called short-channel effect.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (28)
1. dynamic random access memory comprises:
One substrate has irrigation canals and ditches and a deep trenches;
One active element is arranged on this substrate, and this active element comprises:
One grid structure is provided with on this substrate, and fills up this irrigation canals and ditches; And
One doped region is arranged in this substrate of one first side of this grid structure;
One deep trenches formula capacitor is arranged in this deep trenches of this substrate of one second side of this grid, and this second side is relative with this first side, and a top electrode of this deep trenches formula capacitor is in abutting connection with this irrigation canals and ditches bottom.
2. dynamic random access memory as claimed in claim 1, wherein this deep trenches formula capacitor comprises:
One bottom electrode is arranged in this substrate of this deep trenches bottom;
This top electrode is arranged in this deep trenches; And
One capacitance dielectric layer is arranged on the sidewall and the bottom of this deep trenches.
3. dynamic random access memory as claimed in claim 1, wherein this top electrode comprises:
One first conductor layer is arranged at this deep trenches bottom;
One second conductor layer is arranged on this first conductor layer; And
One the 3rd conductor layer is arranged on this second conductor layer, and in abutting connection with this irrigation canals and ditches bottom.
4. dynamic random access memory as claimed in claim 3, wherein this deep trenches formula capacitor more comprises a neck dielectric layer, is arranged at this deep trenches sidewall on this first conductor layer, and around this second conductor layer.
5. dynamic random access memory as claimed in claim 4, wherein the material of this neck dielectric layer comprises silica.
6. dynamic random access memory as claimed in claim 3, wherein this deep trenches formula capacitor more comprises flush type conductive strips, in abutting connection with the 3rd conductor layer and this irrigation canals and ditches bottom.
7. dynamic random access memory as claimed in claim 3, wherein this capacitance dielectric layer is arranged between the sidewall and bottom of this first conductor layer and this deep trenches.
8. dynamic random access memory as claimed in claim 3, wherein the material of this first conductor layer, this second conductor layer and the 3rd conductor layer comprises doped polycrystalline silicon.
9. dynamic random access memory as claimed in claim 3, wherein this grid structure comprises:
One grid is provided with on this substrate, and fills up this irrigation canals and ditches; And
One gate dielectric layer is arranged between this grid and this substrate.
10. dynamic random access memory as claimed in claim 3, wherein the material of this gate dielectric layer comprises silica.
11. a dynamic random access memory comprises:
One substrate has two irrigation canals and ditches and two deep trenches at least, and these two irrigation canals and ditches are arranged between this two deep trenches;
Two grid structures are arranged on this substrate between this two deep trenches, and fill up this two irrigation canals and ditches;
One doped region is arranged in this substrate between this two grid structure;
Two deep trenches formula capacitors are provided with respectively in this two deep trenches of this substrate, and a top electrode of this two deep trenches formula capacitor is respectively in abutting connection with this two irrigation canals and ditches bottom.
12. dynamic random access memory as claimed in claim 11, wherein this two deep trenches formula capacitor comprises separately:
One bottom electrode is arranged in this substrate of this deep trenches bottom;
This top electrode is arranged in this deep trenches; And
One capacitance dielectric layer is arranged on the sidewall and the bottom of this deep trenches.
13. dynamic random access memory as claimed in claim 11, wherein this top electrode comprises:
One first conductor layer is arranged at this deep trenches bottom;
One second conductor layer is arranged on this first conductor layer; And
One the 3rd conductor layer is arranged on this second conductor layer, and in abutting connection with this irrigation canals and ditches bottom.
14. dynamic random access memory as claimed in claim 13, wherein this deep trenches formula capacitor more comprises a neck dielectric layer, is arranged at this deep trenches sidewall on this first conductor layer, and around this second conductor layer.
15. dynamic random access memory as claimed in claim 14, wherein the material of this neck dielectric layer comprises silica.
16. dynamic random access memory as claimed in claim 13, wherein this deep trenches formula capacitor more comprises flush type conductive strips, in abutting connection with the 3rd conductor layer and this irrigation canals and ditches bottom.
17. dynamic random access memory as claimed in claim 13, wherein this capacitance dielectric layer is arranged between the sidewall and bottom of this first conductor layer and this deep trenches.
18. dynamic random access memory as claimed in claim 13, wherein the material of this first conductor layer, this second conductor layer and the 3rd conductor layer comprises doped polycrystalline silicon.
19. dynamic random access memory as claimed in claim 13, wherein this grid structure comprises:
One grid is provided with on this substrate, and fills up this irrigation canals and ditches; And
One gate dielectric layer is arranged between this grid and this substrate.
20. dynamic random access memory as claimed in claim 13, wherein the material of this gate dielectric layer comprises silica.
21. the manufacture method of a dynamic random access memory comprises:
One substrate is provided, formed one first mask layer and a deep trenches that is formed in this substrate of patterning on this substrate, and this first mask layer of patterning exposes this deep trenches;
In this deep trenches, form a deep trenches formula capacitor, and this deep trenches formula capacitor comprises a bottom electrode, a top electrode, a capacitance dielectric layer;
In this first mask layer and this substrate, form an element isolation structure, to define an active area;
Remove this first mask layer on this active area, to expose this substrate;
On this substrate that exposes, form the semiconductor material layer;
This semiconductor material layer of patterning and this substrate are to form irrigation canals and ditches, this top electrode of this ditching type capacitor of bottom contiguous of these irrigation canals and ditches;
Form a grid structure on this substrate, this grid structure fills up this irrigation canals and ditches; And
In this substrate of this grid structure one side, form a doped region.
22. the manufacture method of dynamic random access memory as claimed in claim 21, wherein the material of this semiconductor material layer is crystal silicon of heap of stone.
23. the manufacture method of dynamic random access memory as claimed in claim 21, the step that wherein forms this deep trenches formula capacitor in this deep trenches comprises:
In this substrate of this deep trenches bottom, form a bottom electrode;
Form a capacitance dielectric layer on this deep trenches surface;
Insert one first conductor layer in this deep trenches bottom;
Remove this capacitance dielectric layer that is not covered by this first conductor layer;
Form a neck oxide layer on this deep trenches sidewall that is not covered by this first conductor layer;
Insert one second conductor layer in this deep trenches, to cover this first conductor layer;
Remove this second conductor layer of part and this top oxide layer, make this second conductor layer surface be lower than this substrate surface; And
Insert one the 3rd conductor layer in this deep trenches, wherein this first conductor layer, this second conductor layer and the 3rd conductor layer constitute this top electrode.
24. the manufacture method of dynamic random access memory as claimed in claim 23 more is included in and forms flush type conductive strips in this substrate, in abutting connection with the 3rd conductor layer and this irrigation canals and ditches bottom.
25. the manufacture method of dynamic random access memory as claimed in claim 23, the step that wherein forms this grid structure on this substrate comprises:
On this substrate, form a gate dielectric layer;
Form a conductor layer on this gate dielectric layer, this conductor layer fills up this irrigation canals and ditches; And
This conductor layer of patterning and this gate dielectric layer.
26. the manufacture method of dynamic random access memory as claimed in claim 25 more is included in this grid structure sidewall and forms a clearance wall.
27. the manufacture method of dynamic random access memory as claimed in claim 25 more is included in and forms a bit line that is electrically connected this doped region on this substrate.
28. the manufacture method of dynamic random access memory as claimed in claim 25, wherein this semiconductor material layer of patterning and this substrate comprise to form the step of these irrigation canals and ditches:
Form one second mask layer, this active area of cover part on this substrate;
With this second mask is mask with this component isolation structure layer by layer, removes this semiconductor material layer of part and this substrate; And
Remove this second mask layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014169505A1 (en) * | 2013-04-19 | 2014-10-23 | 中国科学院微电子研究所 | Memory device, and manufacturing method and access method thereof |
| CN111916452A (en) * | 2019-05-07 | 2020-11-10 | 力晶积成电子制造股份有限公司 | Memory structure and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1307722C (en) * | 2003-09-01 | 2007-03-28 | 茂德科技股份有限公司 | Dynamic RAS with slit capacitor and its mfg. method |
| CN1290180C (en) * | 2003-10-21 | 2006-12-13 | 茂德科技股份有限公司 | Producing method and structure for dynamic random access storage |
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2005
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014169505A1 (en) * | 2013-04-19 | 2014-10-23 | 中国科学院微电子研究所 | Memory device, and manufacturing method and access method thereof |
| CN111916452A (en) * | 2019-05-07 | 2020-11-10 | 力晶积成电子制造股份有限公司 | Memory structure and manufacturing method thereof |
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