CN1307722C - Dynamic RAS with slit capacitor and its mfg. method - Google Patents
Dynamic RAS with slit capacitor and its mfg. method Download PDFInfo
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- CN1307722C CN1307722C CNB031557716A CN03155771A CN1307722C CN 1307722 C CN1307722 C CN 1307722C CN B031557716 A CNB031557716 A CN B031557716A CN 03155771 A CN03155771 A CN 03155771A CN 1307722 C CN1307722 C CN 1307722C
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- 239000003990 capacitor Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010276 construction Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The present invention relates to a dynamic random access storage (RAS) with a channel capacitor and a manufacturing method thereof, which is characterized in that a first electrode plate is arranged on a side wall at the lower part of an island-shaped semiconductor structure of a substrate, a second electrode plate is arranged on the surface of the lower part of the island-shaped semiconductor structure and on the surface of the substrate at the external side of the island-shaped semiconductor structure, and a capacitor dielectric layer is arranged between the second electrode plate and the first electrode plate. A transistor for controlling the channel capacitor is arranged on the island-shaped semiconductor structure and is provided with a first source electrode/drain electrode, a second source electrode/drain electrode and a gate electrode. An embedded band is arranged between the second source electrode/drain electrode and the first electrode plate, and a conducting plug is arranged between the first source electrode/drain electrode and a bit line.
Description
Technical field
The present invention relates to a kind of dynamic random access memory (Dynamic Random AccessMemory, abbreviation DRAM) structure and manufacture method thereof relate to a kind of structure and manufacture method thereof with dynamic random access memory of trench capacitor (trench capacitor) especially.
Background technology
In the technology of monocrystalline integrated circuit, capacitor is a common element.In dram chip, need a large amount of capacitors, and each capacitor needs in conjunction with a field-effect transistor (Field EffectTransistor is called for short FET).Along with the increase of the quantity of required reservior capacitor, thereby must improve the packaging density of unit-area capacitance device.Yet the design of classic flat-plate electric capacity can occupy the area of too many chip surface.Technology in the another kind of deep trench that capacitor design is formed on Silicon Wafer then can obtain bigger capacitor density, and be the trend in future.
Yet trench capacitor needs the very high Deep narrow slot groove of depth-width ratio (aspect ratio), and its depth-width ratio all surpasses 40: 1 usually.The formation of trench capacitor is normally at above-mentioned dark narrow trench sidewall deposition one layer insulating, and inserts doped polycrystalline silicon layer as electric pole plate.The silicon trench wall that mixes is then as lower electrode plate.
Usually, depth-width ratio promptly is considered as having high depth-width ratio greater than 4: 1 groove.And when the depth-width ratio of deep trench surpassed 10: 1, the technology of trench fill is difficulty more and more.The deep trench first half can receive more deposition, therefore can hinder the bottom that reactant diffuses to deep trench.Usually, such result causes in the filler of deep trench to produce hole.And such hole can seriously increase the resistance of imbedding plate (buried plate, abbreviation BP).In case insert silicon in the deep trench, the hole of the inside can not disappear with extra technology, and in fact, it is more and more big that hole can become along with different anneal cycles on the contrary, particularly can be even more serious in the situation of deep trench for inserting amorphous silicon.
In addition, along with the increase of the memory cell that is integrated into one chip, need continue to dwindle size of component.Yet the dwindling of component size can be caused the pattern misalignment (misaligned) of deep trench (deep trench is called for short DT) and active area (activearea, abbreviation AA).The problem that so derives is, because the resistance of imbedding band (buried strap is called for short BS) and deep trench and active area is overlapping relevant, so deep trench and active area is overlapping as if misalignment, then can cause the serious change of resistance value of imbedding band.
For allowing above-mentioned problem become apparent more, following conjunction with figs. is done with explanation.Fig. 1 is the vertical view of traditional semiconductor element with many channel capacitors, and the memory cell on its left side is represented the overlapping misalignment of deep trench and active area, and normal layout is represented on the right.Fig. 2 is the profile along the intercepting of the II-II among Fig. 1, the schematic diagram of its expression memory cell.Fig. 3 is the profile along the intercepting of the III-III among Fig. 1.
Memory cell among Fig. 2 comprises trench capacitor 10 in the deep trench DT, in order to shallow channel isolation area STI, bit line contacting window CB, gate electrode G (word line WL is corresponding to the part of active area AA), grid oxic horizon 16 and the N+ source electrode of definition active area AA or drain 12 and 14.In addition, also comprise connect the deep groove capacity node to transistorized source electrode or drain 14 imbed band (buriedstrap, abbreviation BS).Traditionally, transistor is disposed at the next door of deep trench DT usually, and such memory cell can occupy the sizable area of substrate.
As shown in Figure 3, when the pattern misalignment of deep trench DT and active area AA, the lap between deep trench DT and the active area AA can be different, and the lap 22 of a side can be many, and the lap 24 of opposite side is then fewer.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of trench capacitor technology, with the problem of avoiding traditional high depth-width ratio that hole was run into to be derived.
In addition, another object of the present invention is to provide a kind of technology with DRAM of trench capacitor, define active area (AA) and deep trench (DT) simultaneously by using with mask, can reduce the mask of one definition active area, avoiding problems of missing aim between active area and the deep trench, and can avoid problems of missing aim between gate electrode and the active area.
In addition, the object of the present invention is to provide a kind of memory cell of trench capacitor, the size of memory cell can further be dwindled.
The invention provides a kind of dynamic random access memory with trench capacitor, its architectural overview is as follows.One first battery lead plate is arranged on the sidewall of lower part of island semiconductor structure of substrate.One second battery lead plate be arranged in the lower part surface of island semiconductor structure and the substrate surface in the island semiconductor structure outside in.One capacitor dielectric is arranged between second battery lead plate and first battery lead plate.One transistor is arranged on the island semiconductor structure, and this transistor has one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode.One imbeds band is arranged between second source electrode or the drain electrode and first battery lead plate.One conductive plunger is arranged between first source electrode or drain electrode and the bit line, in order to connect first source electrode or to drain to bit line.
The present invention also provides a kind of dynamic random access memory with trench capacitor, and it is applicable to a plurality of memory cell, and wherein each memory cell comprises a transistor and a reservior capacitor.Wherein each reservior capacitor is arranged on the sidewall of each island semiconductor structure lower part of substrate, and each reservior capacitor comprises a tubulose first battery lead plate, a capacitor dielectric and one second battery lead plate.Each tubulose first battery lead plate is arranged on the sidewall of each island semiconductor structure lower part.Each capacitor dielectric is arranged between each tubulose first battery lead plate and each second battery lead plate.The second above-mentioned battery lead plate is arranged in the island semiconductor structure, and extends in the interstructural substrate of island semiconductor, makes second battery lead plate adjacent to each other and be electrically connected each other.Each transistor is arranged on each island semiconductor structure, and each transistor comprises one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode.One isolation structure is arranged between tubulose first battery lead plate.And band is imbedded in setting between each second source electrode or drain electrode and each tubulose first battery lead plate.And, between each first source electrode or drain electrode and corresponding bit lines, conductive plunger is set, in order to being electrically connected to each other.
The present invention also provides a kind of manufacture method with dynamic random access memory of trench capacitor, and its method is summarized as follows.Form a deep trench in substrate, to define an island semiconductor structure, this island semiconductor structure is an active area.Then, in the surface of island semiconductor structure lower part and in the surface of deep trench bottom, form a flush type second battery lead plate.And on flush type second battery lead plate, form a capacitor dielectric.Afterwards, on the capacitor dielectric surface of the lower part sidewall of island semiconductor structure, form tubulose first battery lead plate of a compliance.Continue at the peripheral isolation structure that forms of island semiconductor structure and cover first battery lead plate.Then, form a transistor on the island semiconductor structure, this transistor has one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode.Continue between second source electrode or drain electrode and first battery lead plate and to form one and imbed after the band, form a conductive plunger and connect first source electrode or drain electrode to a bit line.
Description of drawings
Shown in Fig. 1 is the vertical view of the traditional semiconductor element with trench capacitor;
Shown in Fig. 2 is the profile that intercepts along the II-II among Fig. 1, the schematic diagram of its expression memory cell;
Shown in Fig. 3 is the profile that intercepts along the III-III among Fig. 1;
Shown in Fig. 4 A～4F is a vertical view, and it is represented according to the manufacturing process with DRAM of trench capacitor of the present invention;
Shown in Fig. 5 A～5F is the profile that intercepts along the V-V among Fig. 4 A～4F.
Description of reference numerals
The background technology part
Deep trench: DT
Active area: AA
Shallow channel isolation area: STI
Bit line contacting window: CB
Word line: WL
Gate electrode: G
Trench capacitor: 10
Grid oxic horizon: 16
N+ source electrode or drain electrode: 12,14
Imbed band: BS
Lap between deep trench and the active area: 22,24
The embodiment part
Substrate: 100
Mask layer: 102
Deep trench: 104
Island semiconductor structure: 106
Buried electrode plate: 110
Capacitor dielectric: 112
Hollow edged electrode plate: 114
Trench capacitor: C
Groove isolation construction: 116,116a
Grid oxic horizon: 120
Word line: WL
Gate electrode: G
First source electrode or drain electrode: 123
Second source electrode or drain electrode: 124
Imbed band: 126
Insulating barrier: 130
Contact window: 132
Conductive plunger: 134
Bit line: BL
Embodiment
Structure with DRAM of trench capacitor
The invention provides a kind of structure with dynamic random access memory (DRAM) of channel capacitor, this DRAM is made of the memory cell of arranged, each memory cell comprises a transistor and a reservior capacitor, its transistor is arranged on the island semiconductor structure, and reservior capacitor is arranged on the side of lower part of this island semiconductor structure.Below will cooperate Fig. 4 F and Fig. 5 F that structure of the present invention is elaborated.Wherein Fig. 4 F is the vertical view of the DRAM of channel capacitor type, and Fig. 5 F is the profile along the intercepting of the V-V among Fig. 4 F.
Shown in Fig. 4 F and Fig. 5 F, a substrate 100 is the semiconductor-based end for example, is preferably silicon base, its upper part, i.e. and top layer has into the island semiconductor structure 106 of arranged.
The transistor T of DRAM is arranged at the top of island semiconductor structure 106, and reservior capacitor C is arranged on the sidewall of island semiconductor structure 106 lower parts.
Each reservior capacitor C includes a tubulose first battery lead plate 114, a capacitor dielectric 112 and one second battery lead plate 110.Wherein, tubulose first battery lead plate 114 is arranged on the sidewall of island semiconductor structure 106 lower parts, and its material comprises the polysilicon of doping.Capacitor dielectric 112 is arranged between tubulose first battery lead plate 114 and second battery lead plate 110, and its material comprises the material of silica-silicon nitride (ON) lamination, silica-silicon-nitride and silicon oxide (ONO) lamination or other similar this character.Second battery lead plate 110 is arranged in the island semiconductor structure 106, and extend in the substrate 100 between the island semiconductor structure 106, make second battery lead plate 110 adjacent to each other and be electrically connected to each other and become one and share battery lead plate (common plate), this second battery lead plate 110 is the N+ doped region, and its pattern is latticed (grid-shaped).
Each transistor T includes one first source electrode or drains 123,1 second source electrode or the 124 and one gate electrode G that drains, wherein second source electrode or drain 124 and above-mentioned tubulose first battery lead plate 114 between be electrically connected to each other by imbedding band (BS) 126, first source electrode or drain 123 and corresponding bit lines BL be electrically connected by conductive plunger 134.Wherein corresponding to word line (wordline) WL of island semiconductor structure 106 tops usefulness as the gate electrode G of transistor T.
Dispose isolation structure 116a between adjacent tubulose first battery lead plate 114 of above-mentioned reservior capacitor C, the pattern of this isolation structure 116a is latticed (grid-shaped).The height of close second source electrode of this isolation structure 116a or 124 1 sides that drain is lower than the top of tubulose first battery lead plate 114, and the height of the isolation structure 116a in other zone (comprising at least near first source electrode or 123 1 sides that drain) is higher than the top of tubulose first battery lead plate 114.
Second battery lead plate 110 of above-mentioned reservior capacitor C and first source electrode of transistor T or drain 123 and second source electrode or 124 distances of being separated by that drain can not interfere with each other to guarantee conductivity to each other.In addition, tubulose first battery lead plate 114 of above-mentioned reservior capacitor C also with first source electrode of transistor T or 123 distances of being separated by that drain, can not interfere with each other to guarantee conductivity to each other.
Manufacture method with DRAM of trench capacitor
Below cooperate Fig. 4 A～4F and Fig. 5 A～5F to describe a embodiment in detail according to the manufacture method of the structure of the DRAM with trench capacitor of the present invention.Wherein Fig. 4 A～4F is a vertical view, and Fig. 5 A～5F is the profile along the intercepting of the V-V among Fig. 4 A～4F.
Shown in Fig. 4 A and 5A, one substrate 100 is provided, it for example is silicon base, in substrate 100, form a mask layer 102, this mask layer 102 for example is made of pad oxide and silicon nitride layer, it has matrix pattern, and its pattern is the zone of exposing deep trench, can be in order to define the zone of active area (AA) and deep trench (DT) simultaneously.Then carry out etching technics, with the design transfer of this mask layer 102 to substrate 100, in substrate 100, to form deep trench 104, also promptly, the upper part of substrate 100, i.e. top layer, being matrix type island semiconductor structure 106, for example is the silicon island, and island semiconductor structure 106 is active area.
Follow shown in Fig. 4 B and Fig. 5 B, in lower part formation buried electrode plate (BP) 110 of deep trench 104 and the capacitor dielectric 112 of compliance, and the hollow edged electrode plate 114 that forms compliance in the lower part of island semiconductor structure 106.Wherein, buried electrode plate 110 is a N+ type doped region, is positioned at inner and deep trench 104 bottoms of island semiconductor structure 106, and adjacent to each other and mutual conducting becomes a shared battery lead plate and this buried electrode plate 110 is by the doped region of deep trench 104 bottoms.Wherein hollow edged electrode plate 114 be arranged at island semiconductor structure 106 around, be not arranged at deep trench 104 bottoms.Therefore, formed trench capacitor C is surrounded on the sidewall of island semiconductor structure 106 lower parts.
The formation of above-mentioned buried electrode plate 110 for example is to form the dielectric layer that one deck N+ type mixes on the surface of deep trench 104, arsenic silex glass (arsenic silicate glass for example, be called for short ASG), then in deep trench 104, insert the photo anti-corrosion agent material of a desired depth, remove not the dielectric layer of the doping that is covered by photo anti-corrosion agent material again by wet etching, and the diffusion of impurities in the dielectric layer that mixes is advanced in the substrate 100 via thermal process, thereby 100 surfaces of the substrate in deep trench 104 form the N+ doped region, with as buried electrode plate 110, afterwards photo anti-corrosion agent material is removed.Then form the capacitor dielectric 112 and the conductive layers of one deck compliances, and utilize back etching to remove the conductive layer of upper part, to become hollow edged electrode plate 114 as shown in the figure on whole substrate 100 surfaces.Wherein the material of capacitor dielectric 112 for example is the laminated construction of silica-silicon nitride (oxide-nitride is called for short ON) or the laminated construction of silica-silicon-nitride and silicon oxide (oxide-nitride-oxide is called for short ONO).Wherein the material of hollow edged electrode plate 114 for example is the polysilicon that mixes.
Then shown in Fig. 4 C and 5C figure, deposit a layer insulating, material is a silica for example, and removes the unnecessary insulating barrier of mask layer 102 tops, to form groove isolation construction 116 in deep trench 104, removes mask layer 102 afterwards again.
Then shown in Fig. 4 D and 5D figure, in substrate 100 upper surfaces, it is the upper surface of island semiconductor structure 106, form one deck grid oxic horizon 120, then in whole substrate 100, form one deck conductive layer, and define this conductive layer and become word line WL, and this word line WL in corresponding to the zone of island semiconductor structure 106 as the usefulness of gate electrode G, and this word line WL is coated by insulating barrier 122.The zone that is not covered by gate electrode G in island semiconductor structure 106 forms first source electrode or 123 and second source electrode or drain 124 of draining afterwards.
Then shown in Fig. 4 E and 5E figure, in second source electrode or drain 124 and hollow edged electrode plate 114 between form and imbed band (BS) 126, make second source electrode of hollow edged electrode plate 114 transistor T corresponding or drain 124 electrical connections with it.
The formation of imbedding with 126 for example is to form one deck photoresist to define the pattern of imbedding band, be mask with this photoresist afterwards, carry out the etching of returning of groove isolation construction 116, the trench isolations 116a that exposes hollow edged electrode plate 114 tops with formation, continue deposition one deck conductive layer, the polysilicon of Can Zaing for example, and conductive layer returned etching, with form connect second source electrode or drain 124 and imbedding of hollow edged electrode plate 114 be with 126.
Then shown in Fig. 4 F and Fig. 5 F, in whole substrate 100, form a layer insulating 130, it for example is the boron-phosphorosilicate glass layer, and in wherein forming contact window 132 to expose source electrode or to drain 123, and in contact window 132, form conductive plunger 134, for example be tungsten plug, in order to connect source electrode or to drain 123 and with the bit line BL that forms.
In sum, the technology of trench capacitor of the present invention, can reduce one the definition active area (AA) mask because in the present invention, active area defines with mask simultaneously with deep trench.Therefore, problems of missing aim between active area and the channel capacitor can be avoided, problems of missing aim between gate electrode and the active area can also be avoided in addition.
In addition, the memory cell size of trench capacitor of the present invention can further be dwindled.Its reason is, formed deep trench is simultaneously in order to forming trench capacitor and groove isolation construction in the substrate, and transistor arrangement is on by the island semiconductor structure that deep trench defined.
Moreover the present invention be not the traditional pore space structure of etching, but the zone outside the etching island semiconductor structure also is the latticed pattern of etching when the definition deep trench, does not therefore have the problem of traditional quite high depth-width ratio that hole ran into.
Incidentally, though the present invention needs additionally to imbed together the mask of band (BS), the accuracy requirement of this road mask is lower, therefore can not increase the degree of difficulty and the complexity of technology.
Though the present invention discloses as above with preferred embodiment; so it is not to be used for limiting the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention is with being as the criterion that claim was defined.
Claims (18)
1. dynamic random access memory with trench capacitor comprises:
One substrate, the upper part of this substrate have an island semiconductor structure;
One first battery lead plate is arranged at the sidewall of the lower part of this island semiconductor structure, and this first battery lead plate in a tubular form;
One second battery lead plate is arranged in the surface of lower part of this island semiconductor structure and in the surface of this substrate in this island semiconductor structure outside;
One capacitor dielectric is arranged between this second battery lead plate and this first battery lead plate;
One transistor is arranged on this island semiconductor structure, and wherein this transistor has one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode; And
One imbeds band, is arranged between this second source electrode or drain electrode and this first battery lead plate.
2. the dynamic random access memory with trench capacitor as claimed in claim 1 also comprises an isolation structure, and it covers this first battery lead plate.
3. the dynamic random access memory with trench capacitor as claimed in claim 2, wherein the height of close this second source electrode of this isolation structure or the side that drains is lower than the top of this first battery lead plate, and this isolation structure is higher than the top of this first battery lead plate near the height of this first source electrode or the side that drains.
4. the dynamic random access memory with trench capacitor as claimed in claim 1, wherein this first battery lead plate comprises doped polycrystalline silicon layer, this second battery lead plate comprises N+ type doped region.
5. the dynamic random access memory with trench capacitor as claimed in claim 1, wherein this material of imbedding band comprises doped polycrystalline silicon layer.
6. the dynamic random access memory with trench capacitor as claimed in claim 1 also comprises a conductive plunger, in order to connect this first source electrode or drain electrode to a bit line.
7. the dynamic random access memory with trench capacitor is applicable to a plurality of memory cell, and wherein each memory cell comprises a transistor and a reservior capacitor, comprising:
The semiconductor substrate has a plurality of island semiconductor structures;
Reservior capacitor, each reservior capacitor are arranged on the sidewall of each island semiconductor structure lower part, and each reservior capacitor comprises a tubulose first battery lead plate, a capacitor dielectric and one second battery lead plate;
Tubulose first battery lead plate, each tubulose first battery lead plate is arranged on the sidewall of each island semiconductor structure lower part;
Capacitor dielectric, each capacitor dielectric are arranged between each tubulose first battery lead plate and each second battery lead plate;
Second battery lead plate, those second battery lead plates are arranged in those island semiconductor structures, and extend in this substrate between those island semiconductor structures, make those second battery lead plates adjacent to each other and be electrically connected to each other;
Transistor, each transistor are arranged on each island semiconductor structure, and each transistor comprises one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode;
One isolation structure is arranged between those tubulose first battery lead plates;
A plurality of bands of imbedding are arranged at respectively between each second source electrode or drain electrode and each tubulose first battery lead plate; And
A plurality of conductive plungers are respectively in order to connect each first source electrode or drain electrode to a corresponding bit lines.
8. the dynamic random access memory with trench capacitor as claimed in claim 7, wherein those second battery lead plates are adjacent to each other and be electrically connected to each other into one latticed.
9. the dynamic random access memory with trench capacitor as claimed in claim 7, wherein this isolation structure is one latticed.
10. the dynamic random access memory with trench capacitor as claimed in claim 7, wherein the height of close each second source electrode of this isolation structure or the side that drains is lower than the top of corresponding tubulose first battery lead plate, and this isolation structure is higher than the top of this tubulose first battery lead plate of correspondence near the height of each first source electrode or the side that drains.
11. the dynamic random access memory with trench capacitor as claimed in claim 7, wherein this first battery lead plate comprises doped polycrystalline silicon layer, and this second battery lead plate comprises N+ type doped region.
12. the dynamic random access memory with trench capacitor as claimed in claim 7, wherein this material of imbedding band comprises doped polycrystalline silicon layer.
13. the manufacture method with dynamic random access memory of trench capacitor comprises:
One substrate is provided;
In this substrate, form a deep trench, to define an island semiconductor structure;
In the surface of this island semiconductor structure lower part and in the surface of this deep trench bottom, form a flush type second battery lead plate;
On this flush type second battery lead plate, form a capacitor dielectric;
On this capacitor dielectric surface on the sidewall of the lower part of this island semiconductor structure, form tubulose first battery lead plate of a compliance;
Form an isolation structure and cover this first battery lead plate in this island semiconductor structure is peripheral;
Form a transistor on this island semiconductor structure, this transistor has one first source electrode or drain electrode, one second source electrode or a drain electrode and a gate electrode; And
Between this second source electrode or drain electrode and this first battery lead plate, form one and imbed band.
14. the manufacture method with dynamic random access memory of trench capacitor as claimed in claim 13, wherein in this substrate, form this deep trench with in the step that defines this island semiconductor structure, this substrate surface comprises that also a mask layer is in order to as etching mask, thereby form this deep trench so that etching is carried out in this substrate, this mask layer is removed at this island semiconductor structure this isolation structure of peripheral formation and after covering this first battery lead plate.
15. the manufacture method with dynamic random access memory of trench capacitor as claimed in claim 13, the formation method that wherein forms this tubulose first battery lead plate comprises:
On this capacitor dielectric, form the conductive layer of a compliance; And
Return this conductive layer of etching.
16. the manufacture method with dynamic random access memory of trench capacitor as claimed in claim 13, wherein this formation method of imbedding band comprises:
Etching is corresponding to this isolation structure of this second source electrode or the side that drains, until the top of exposing this tubulose first battery lead plate;
Deposit a conductive layer; And
Return this conductive layer of etching.
17. the manufacture method with dynamic random access memory of trench capacitor as claimed in claim 13 also comprises forming a conductive plunger in order to connect this first source electrode or drain electrode to a bit line.
18. the manufacture method with dynamic random access memory of trench capacitor as claimed in claim 13, wherein the formation method of this conductive plunger comprises:
Form an insulating barrier, and cover this and imbed on band, this isolation structure and this transistor;
In this insulating barrier, form a bit line contacting window and expose this first source electrode or drain region; And
In this bit line contacting window, fill up an electric conducting material.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031557716A CN1307722C (en) | 2003-09-01 | 2003-09-01 | Dynamic RAS with slit capacitor and its mfg. method |
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| CNB031557716A CN1307722C (en) | 2003-09-01 | 2003-09-01 | Dynamic RAS with slit capacitor and its mfg. method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7232719B2 (en) * | 2005-03-28 | 2007-06-19 | Promos Technologies Inc. | Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate |
| CN100446257C (en) * | 2005-10-12 | 2008-12-24 | 茂德科技股份有限公司 | Dynamic random access memory and mfg. method thereof |
| JP5033807B2 (en) * | 2005-11-08 | 2012-09-26 | エヌエックスピー ビー ヴィ | Integrated capacitor placement for extremely high capacitance values |
| CN101582425B (en) * | 2008-05-12 | 2010-12-08 | 南亚科技股份有限公司 | Dynamic random access memory and memory array |
| CN110223982B (en) * | 2018-03-01 | 2021-07-27 | 联华电子股份有限公司 | Dynamic random access memory and manufacturing method thereof |
| CN112331653B (en) * | 2020-10-29 | 2021-11-05 | 长江存储科技有限责任公司 | Semiconductor device, three-dimensional memory and semiconductor device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212454A (en) * | 1997-09-22 | 1999-03-31 | 日本电气株式会社 | High reliable trench capacitor type memor cell |
| US6583464B1 (en) * | 1997-11-28 | 2003-06-24 | Infineon Technologies Ag | Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor |
| CN1117397C (en) * | 1992-01-09 | 2003-08-06 | 国际商业机器公司 | Diffusing buried polar plate slot DRAM unit array |
-
2003
- 2003-09-01 CN CNB031557716A patent/CN1307722C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117397C (en) * | 1992-01-09 | 2003-08-06 | 国际商业机器公司 | Diffusing buried polar plate slot DRAM unit array |
| CN1212454A (en) * | 1997-09-22 | 1999-03-31 | 日本电气株式会社 | High reliable trench capacitor type memor cell |
| US6583464B1 (en) * | 1997-11-28 | 2003-06-24 | Infineon Technologies Ag | Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1591875A (en) | 2005-03-09 |
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