CN1855360A - Production of semiconductor for preventing from being brokendown - Google Patents
Production of semiconductor for preventing from being brokendown Download PDFInfo
- Publication number
- CN1855360A CN1855360A CN 200510065609 CN200510065609A CN1855360A CN 1855360 A CN1855360 A CN 1855360A CN 200510065609 CN200510065609 CN 200510065609 CN 200510065609 A CN200510065609 A CN 200510065609A CN 1855360 A CN1855360 A CN 1855360A
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- doped region
- type doped
- prevents
- punctures
- semiconductor element
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- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000012774 insulation material Substances 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The invention is applied in a substrate on which multi element isolation structures arrayed in parallel have been formed to define multi active zones, and the upper surfaces of said multi isolation structures bulge out from the surface of the substrate. In addition, on the substrate multi strips of conduction layer arrayed in parallel are formed and interleave with the said element isolation structure. On the portion under the conductor layer and between the two element isolation structures, multi trench type elements are formed. Each said trench element includes a first conduction doping region. The method comprises: forming a spacer on sidewall of the element isolation structure and the of the conduction layer; taking the spacer as mask to inject dopant so as to form a second conduction type doping region between two adjacent first conduction type doping region.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, particularly relate to a kind of manufacture method that prevents the semiconductor element of puncture (anti-punch-through).
Background technology
Along with the fast development of IC industry, requiring under the more and more higher situation of circuit integration, the design of entire circuit element size also is forced to advance toward the direction that size does not stop to dwindle.When the size of semiconductor element was dwindled gradually, what the distance between the element also can be relative dwindled, and after its distance shortened to certain certain degree, various problems of being derived because of the raising of technology integrated level just can take place.Therefore, how to produce that size is dwindled, high integration, the semiconductor element that can take into account its quality again is the consistent target of industry.
Fig. 1 illustrate is the generalized section of existing a kind of semiconductor element.Please refer to Fig. 1, semiconductor element comprises substrate 100, dielectric layer 102, plough groove type element 104 and doped region 106.Wherein, dielectric layer 102 is positioned at substrate 100 tops, and plough groove type element 104 is arranged in part substrate 100 and dielectric layer 102, and doped region 106 is arranged in the substrate 100 of plough groove type element 104 belows.
Yet along with the raising of semiconductor element integrated level, many challenges have appearred in the manufacture method of traditional semiconductor element.For example be, because the raising of semiconductor technology integrated level, and the distance between the adjacent grooves formula element 104 also shortens relatively, therefore cause easily between the two adjacent doped regions 106 and produce the problem that electrically punctures (punch through) (arrow 108 as shown in fig. 1), this problem can cause and produce abnormal electrically conducting between the adjacent grooves formula element 104, and make element operation speed and element efficiency not good, or even cause element short circuit (short) or open circuit (open), and then influence the rate of finished products and the reliability of whole technology widely.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method that prevents the semiconductor element that punctures is being provided, can avoid problem, make element operation speed and element efficiency not good, and then have influence on the rate of finished products and the reliability of technology because of the electrical puncture between the element.
The present invention proposes a kind of manufacture method that prevents the semiconductor element that punctures, the method is applicable to substrate, and be formed with a plurality of component isolation structures of being arranged in parallel in this substrate defining a plurality of active areas, and the upper surface of these component isolation structures protrudes in substrate surface.In addition, the many conductor layers that are arranged in parallel in substrate, have been formed with, these conductor layers and component isolation structure are staggered, be formed with a plurality of plough groove type elements below the conductor layer and between per two component isolation structures, and the plough groove type element comprises the first conductivity type doped region that is arranged at channel bottom.The method comprises prior to the sidewall of component isolation structure and conductor layer and forms clearance wall, and then is that mask carries out the alloy injection technology with the clearance wall, to form the second conductivity type doped region between the two adjacent first conductivity type doped regions.
Described according to the preferred embodiments of the present invention, the method for above-mentioned formation clearance wall is included in and forms insulation material layer in the substrate, carries out an anisotropic etching process then, removes the SI semi-insulation material layer to form it.Wherein, the material of clearance wall comprises silicon nitride.
Described according to the preferred embodiments of the present invention, the scope of the above-mentioned second conductivity type doped region is adjusted by the thickness of clearance wall.
Described according to the preferred embodiments of the present invention, the above-mentioned first conductivity type doped region is a P type doped region, and the second conductivity type doped region then is a N type doped region.
Described according to the preferred embodiments of the present invention, the above-mentioned first conductivity type doped region is a N type doped region, and the second conductivity type doped region then is a P type doped region.
Described according to the preferred embodiments of the present invention, above-mentioned plough groove type element is the plough groove type memory.
Described according to the preferred embodiments of the present invention, above-mentioned plough groove type element is a slot type capacitor.
Described according to the preferred embodiments of the present invention, above-mentioned plough groove type element is the plough groove type transistor.
Because the present invention utilizes clearance wall as mask, in the mode of aiming at voluntarily, carry out the alloy injection technology, have the zone that prevents breakdown characteristics between the doped region of element, to form.Therefore, the present invention can avoid because of producing the problem of electrical puncture, and makes element efficiency not good, and then has influence on the rate of finished products and the reliability of technology.And the present invention can utilize the thickness of clearance wall to prevent the size in the zone of breakdown characteristics with control accurately.In addition, formation of the present invention have prevent breakdown characteristics regional employed technology can with the high-k metal gate devices process integration together, therefore need not expend huge cost, can bring into play very big effect.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrate is the generalized section of existing a kind of semiconductor element.
Fig. 2 A to Fig. 2 C illustrates the flow process top view for the manufacture method that prevents the semiconductor element that punctures of one embodiment of the present invention.
Fig. 3 A to Fig. 3 C illustrates the flow process profile for the manufacture method that prevents the semiconductor element that punctures of one embodiment of the present invention, and it illustrates among Fig. 2 A to Fig. 2 C the profile along I-I ' line respectively.
Fig. 4 A to Fig. 4 C illustrates the flow process profile for the manufacture method that prevents the semiconductor element that punctures of one embodiment of the present invention, and it illustrates among Fig. 2 A to Fig. 2 C the profile along II-II ' line respectively.
The simple symbol explanation
100,200: substrate
102,214: dielectric layer
104: the plough groove type element
106: doped region
108: arrow
202: component isolation structure
204: active area
206: conductor layer
208: the plough groove type element
210: groove
212:N type doped region
216: insulation material layer
216a: clearance wall
218:P type doped region
220: the alloy injection technology
Embodiment
Fig. 2 A to Fig. 2 C illustrates the flow process top view for the manufacture method that prevents the semiconductor element that punctures of one embodiment of the present invention.Fig. 3 A to Fig. 3 C is for illustrating among Fig. 2 A to Fig. 2 C the profile along I-I ' line respectively.Fig. 4 A to Fig. 4 C is for illustrating among Fig. 2 A to Fig. 2 C the profile along II-II ' line respectively.
At first, please provide a substrate 200 simultaneously with reference to Fig. 2 A, Fig. 3 A and Fig. 4 A.This substrate 200 for example is a silicon base.This substrate 200 has been formed with a plurality of component isolation structures 202 that are arranged in parallel, and defining a plurality of active areas 204, and the upper surface of these component isolation structures 202 protrudes in substrate 200 surfaces.Wherein, the formation method of component isolation structure 202 for example be the shallow trench isolation method (ShallowTrench Isolation, STI).
In addition, in substrate 200, be formed with the many conductor layers 206 that are arranged in parallel, and these conductor layers 206 are staggered with component isolation structure 202.Wherein, the material of conductor layer 206 for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it; Perhaps also can adopt the mode of (in-situ) injection alloy when participating in the cintest, utilize chemical gas-phase method to form it.And, be formed with a plurality of plough groove type elements 208 below each conductor layers 206 and in the active area 204 between per two component isolation structures 202, wherein, plough groove type element 208 for example is slot type capacitor, plough groove type transistor or plough groove type memory.
In one embodiment, can form dielectric layer 214 in substrate 200, wherein the material of dielectric layer 214 for example is silica, silicon oxide/silicon nitride/silicon oxide or other suitable material, and its formation method for example is a chemical vapour deposition technique.
In addition, plough groove type element 208 comprises the N type doped region 212 that is arranged at groove 210 bottoms.Wherein, the formation method of N type doped region 212 for example is an ion implantation technology.Similarly, because the raising of technology integrated level, the problem of (punch through) also takes place electrically to puncture in two adjacent N type doped regions 212 easily.
Then, please in substrate 200, form one deck insulation material layer 216 simultaneously with reference to Fig. 2 B, Fig. 3 B and Fig. 4 B.Wherein, the material of this insulation material layer 216 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Continue it, please remove SI semi-insulation material layer 216 simultaneously with reference to Fig. 2 C, Fig. 3 C and Fig. 4 C, and in the sidewall formation clearance wall 216a of component isolation structure 202 with conductor layer 206.Wherein, removing SI semi-insulation material layer 216 for example is to carry out an anisotropic etching process with the method that forms clearance wall 216a.
Subsequently, be mask with clearance wall 216a, carry out an alloy injection technology 220, between two adjacent N type doped regions 212, to form a P type doped region 218.
Particularly, P type doped region 218 and N type doped region 212 be the doped region of different alloys each other, has the zone that prevents breakdown characteristics so P type doped region 218 can be used as, with the problem that prevents from electrically to puncture.That is be that P type doped region 218 can be in order to avoiding because of electrically conducting between the adjacent N type doped region 212, and influence the problem of element efficiency.
In the above-described embodiment, the conductivity type doped region of plough groove type element 208 with have a zone that prevents breakdown characteristics to adopt N type doped region and P type doped region respectively be example describing it in detail, yet the present invention is not limited thereto.In addition, the present invention also can adopt the conductivity type doped region of plough groove type element 208 and have the technology that the zone that prevents breakdown characteristics is respectively P type doped region and N type doped region.That is to say that the present invention also can form N type doped region to prevent electrical puncture, with the rate of finished products of improving technology and the reliability that improves technology between adjacent P type doped region.
In the present invention, the scope of P type doped region 218 (shown in Fig. 2 C) can be by the thickness adjustment of clearance wall 216a.In other words, the present invention utilizes position and the range size of thickness to define preformed doped region accurately of clearance wall 216a.
From the above, the present invention forms the doped region (P type doped region 218) with its different alloys between the doped region (N type doped region 212) of element, to avoid interelement electrical puncture, and it utilizes clearance wall 216a to be mask, define in (selg-aligned) mode of aiming at voluntarily and to have the zone (the P type doped region 218 of Fig. 2 C) that can prevent breakdown characteristics, to avoid adjacent interelement to produce the phenomenon of electrical undesired conducting, that is, it can avoid interelement electrical puncture, so can improve the rate of finished products and the reliability that improves technology of technology.
In addition, the doped region that punctures that prevents of the present invention is positioned at the central area (shown in Fig. 2 C) that is crossed by component isolation structure 202 and conductor layer 206, and it is a mask with clearance wall 216a, carry out ion implantation technology with alignment so voluntarily, therefore will be not can be influential other the problem of doped region (as N type doped region 212).
It should be noted that the present invention prevent in order to formation the doped region that punctures method can with the high-k metal gate devices process integration together.Therefore, the present invention need not expend huge manpower and cost, can bring into play very big effect.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (9)
1, a kind of manufacture method that prevents the semiconductor element that punctures, be applicable to a substrate, a plurality of component isolation structures of being arranged in parallel have been formed with in this substrate to define a plurality of active areas, and the upper surface of those component isolation structures protrudes in this substrate surface, the many conductor layers that are arranged in parallel in this substrate, have been formed with, those conductor layers and those component isolation structures are staggered, below each those conductor layer, and a plurality of plough groove type elements have been formed with in those active areas between per two those component isolation structures, each those plough groove type element comprises the one first conductivity type doped region that is arranged at a channel bottom, and this method comprises:
Sidewall in those component isolation structures and those conductor layers forms a clearance wall; And
With this clearance wall is that mask carries out an alloy injection technology, to form one second conductivity type doped region between two adjacent these first conductivity type doped regions.
2, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, the method that wherein forms this clearance wall comprises:
In this substrate, form an insulation material layer; And
Carry out an anisotropic etching process, remove this insulation material layer of part.
3, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the material of this clearance wall comprises silicon nitride.
4, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein the scope of this second conductivity type doped region is by the thickness adjustment of this clearance wall.
5, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein this first conductivity type doped region is a P type doped region; This second conductivity type doped region is a N type doped region.
6, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein this first conductivity type doped region is a N type doped region; This second conductivity type doped region is a P type doped region.
7, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein those plough groove type elements are the plough groove type memory.
8, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein those plough groove type elements are slot type capacitor.
9, the manufacture method that prevents the semiconductor element that punctures as claimed in claim 1, wherein those plough groove type elements are the plough groove type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100656098A CN100382236C (en) | 2005-04-18 | 2005-04-18 | Production of semiconductor for preventing from being brokendown |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100656098A CN100382236C (en) | 2005-04-18 | 2005-04-18 | Production of semiconductor for preventing from being brokendown |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1855360A true CN1855360A (en) | 2006-11-01 |
| CN100382236C CN100382236C (en) | 2008-04-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100656098A Active CN100382236C (en) | 2005-04-18 | 2005-04-18 | Production of semiconductor for preventing from being brokendown |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100382236C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529330B (en) * | 2014-09-17 | 2019-01-01 | 美光科技公司 | memory structure and manufacturing method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0121992B1 (en) * | 1993-03-03 | 1997-11-12 | 모리시다 요이치 | Semiconductor device and method of manufacturing the same |
| JP3691963B2 (en) * | 1998-05-28 | 2005-09-07 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US6077748A (en) * | 1998-10-19 | 2000-06-20 | Advanced Micro Devices, Inc. | Advanced trench isolation fabrication scheme for precision polysilicon gate control |
| JP2002076287A (en) * | 2000-08-28 | 2002-03-15 | Nec Kansai Ltd | Semiconductor device and its manufacturing method |
| US6777737B2 (en) * | 2001-10-30 | 2004-08-17 | International Business Machines Corporation | Vertical DRAM punchthrough stop self-aligned to storage trench |
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2005
- 2005-04-18 CN CNB2005100656098A patent/CN100382236C/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529330B (en) * | 2014-09-17 | 2019-01-01 | 美光科技公司 | memory structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN100382236C (en) | 2008-04-16 |
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Owner name: POWERCHIP TECHNOLOGY CO., LTD. Free format text: FORMER NAME: POWERCHIP SEMICONDUCTOR CORP. |
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| CP03 | Change of name, title or address |
Address after: Hsinchu Science Park, Taiwan, China Patentee after: Powerflash Technology Corporation Address before: Hsinchu City, Taiwan, China Patentee before: Powerchip Semiconductor Corp. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20190626 Address after: Hsinchu Science Park, Taiwan, China Patentee after: Lijing Jicheng Electronic Manufacturing Co., Ltd. Address before: Hsinchu Science Park, Taiwan, China Patentee before: Powerflash Technology Corporation |
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