CN1873922A - 一种具有高k栅介质层和硅化物栅电极的半导体器件的制造方法 - Google Patents

一种具有高k栅介质层和硅化物栅电极的半导体器件的制造方法 Download PDF

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CN1873922A
CN1873922A CNA2005101291503A CN200510129150A CN1873922A CN 1873922 A CN1873922 A CN 1873922A CN A2005101291503 A CNA2005101291503 A CN A2005101291503A CN 200510129150 A CN200510129150 A CN 200510129150A CN 1873922 A CN1873922 A CN 1873922A
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silicide
gate electrode
barrier layer
metal
oxide
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M·多茨
J·布拉斯克
J·卡瓦利罗斯
M·梅茨
S·达塔
R·仇
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Intel Corp
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Abstract

描述了一种制造半导体器件的方法。该方法包括：在衬底上形成高k栅介质层，在该高k栅介质层上形成阻挡层，和在该阻挡层上形成全硅化物栅电极。

Description

一种具有高k栅介质层和硅化物栅电极的半导体器件的制造方法
技术领域
本发明涉及一种半导体器件，特别涉及具有高k栅介质层和硅化物栅电极的半导体器件。
背景技术
具有由二氧化硅制成的很薄的栅介质的互补金属氧化物半导体(“CMOS”)器件可能会遇到令人无法接受的栅极泄漏电流的情况。由某种高k电介质材料，而不是二氧化硅形成的栅介质可以减少栅极漏电。然而，当直接在这种电介质上形成一种全硅化物栅电极的时候，栅电极和电介质之间的相互作用可能导致费米能级钉扎。结果，具有直接形成在高k栅介质上的全硅化物栅电极的晶体管可能具有相对高的阈值电压。
发明内容
因此，有必要改进形成具有高k栅介质的半导体器件的工艺。需要有这样一种形成具有全硅化物栅电极和高k栅介质的器件的工艺，这种器件没有表现出不希望的高阈值电压。本发明提供这样一种方法。
附图说明
图1a-1d表示当实施本发明的方法的一个实施例时可形成的结构的横截面图。
图2a-2d表示当实施本发明的方法的第二个实施例时可形成的结构的横截面图。
这些附图中显示的部件未按比例绘制。
具体实施方式
描述了一种制造半导体器件的方法。该方法包括在衬底上形成高k栅介质层，在该高K栅介质层上形成阻挡层，并在该阻挡层上形成全硅化物栅电极。在以下的说明中，为提供对本发明的深入理解而陈述了很多细节。然而，本领域技术人员显然明白，本发明可以用这里明确说明的方式以外的很多其他方式实施。本发明不局限于下面公开的具体细节。
图1a-1d表示当实施本发明的方法的一个实施例时可形成的结构的横截面图。如图1a所示，在这个实施例中，高k栅介质层101形成在衬底100上，阻挡层102形成在高k栅介质层101上，且多晶硅层103形成在阻挡层102上。衬底100可以包含任何可以作为在其上构建半导体器件的基础的材料。
可以用来制造高k栅介质层101的一些材料包括：氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物和铌化铅锌。特别优选氧化铪、氧化锆和氧化铝。这里说明了用来形成高k栅介质层101的材料的几个例子，但该层也可以由其他材料制成。
在衬底100上可以使用常规的淀积方法来形成高k栅介质层101，例如，使用常规的化学汽相淀积(“CVD”)、低压CVD或物理汽相淀积(“PVD”)工艺栅介质。优选使用常规的原子层CVD工艺。在这种工艺中，可以在选择的流速下将金属氧化物的前体(例如，金属氯化物)和蒸汽输送到CVD反应室，然后在一种选择的温度和压力下进行操作，以在衬底100和高k栅介质层101之间产生原子平滑界面。该CVD反应室应该工作足够长时间以形成具有理想厚度的层。在大多数的应用中，高k栅介质层101应该少于约60埃厚，并且更优选介于约5埃到大约40埃厚之间。
如果高k栅介质层101包含氧化物，根据用来制造它的工艺，会在任意的表面处出现氧空位同时出现令人不能接受的杂质能级。层101淀积后，希望在层101上除去某些杂质并氧化该层，以产生具有接近理想的金属：氧配比的化学计量。
阻挡层102最好是导电的且功函数透明的。在一个实施例中，阻挡层102可包含金属氮化物，例如，氮化钛或氮化钽。可以通过使用常规的CVD或PVD工艺在高k栅介质层101上形成阻挡层102，这对于本领域技术人员来说是显而易见的。阻挡层102一定要足够厚以防止全硅化物栅电极(将形成在阻挡层102上)与高k栅介质层101相互作用而产生不希望的费米能级钉扎。应该优化该厚度以确保阻挡层102不会显著影响该器件的阈值电压，该电压最好将由随后形成的全硅化物栅电极的功函数设定。在许多应用中，介于约5埃和约50埃之间厚度(和更优选介于约10埃和约20埃之间厚度)的阻挡层可以在保持功函数透明的同时缓和费米能级钉扎。
通过使用常规的淀积工艺，可以在阻挡层102上形成多晶硅层103，优选介于约100和约2,000埃之间的厚度，并且更优选介于约500和约1,600埃的厚度。在这个工艺阶段，多晶硅层103可以是非掺杂的，n型掺杂的(例如，用砷、磷或其他n型材料)或p型掺杂的，例如，用硼。
在形成图1a的结构之后，刻蚀多晶硅层103、阻挡层102和高k栅介质层101，以产生图1b所示的结构。可以使用常规的图案化和刻蚀工艺，这对本领域技术人员来说是显而易见的。然后，邻近该结构形成间隔层104和105，且邻近这些间隔层形成介电层106。间隔层104和105优选包含氮化硅，而介电层106可以包含二氧化硅或低K材料。因为本领域技术人员对于形成这种结构可以使用的常规工艺步骤很熟悉，所以在这里将不做进一步的详细说明。如所示，介电层106已被回抛光，例如，通过常规的化学机械抛光(“CMP”)的操作，以暴露出多晶硅层103并且生成图1c结构。尽管没有示出，但是该结构可以包含许多其他的部件(例如，氮化硅刻蚀停止层、源和漏区和一层或多层的缓冲层)，这些部件可以使用常规的工艺形成。
在形成图1c结构后，基本上所有的多晶硅层103(且优选所有的该层)转变为硅化物107，如图1d所示。全硅化物栅电极107可以包含，例如，硅化镍、硅化钴、硅化钛或这些材料的混合物。通过在整个该结构上淀积适合的金属，然后在足够的温度下加热足够长的时间由多晶硅层103生成金属硅化物(例如，NiSi)，多晶硅层103可以转变为全硅化物栅电极107。
在一个优选的实施例中，通过在该整个结构上，包括层103的暴露的表面，溅射适合的金属(例如，镍)形成硅化物107。为了使硅化物107完全在整个多晶硅层103上延伸，可能有必要在该溅射操作后进行高温退火，例如在至少约450℃的温度下的快速热退火。当形成硅化镍时，退火优选在介于约500℃和约550℃之间的温度下进行。当形成硅化钴时，退火优选在至少约600℃的温度下进行。
可以运用常规的CMP步骤在形成硅化物107后，从该结构上去除多余的金属，介电层106作为抛光停止层。硅化物107可以作为全硅化物栅电极，该栅电极适合作为全硅化物PMOS栅电极或全硅化物NMOS栅电极。硅化物107是作为全硅化物PMOS栅电极还是全硅化物NMOS栅电极，取决于多晶硅层103获得的掺杂处理、用来产生硅化物的金属和制造它的工艺。在一些实施例中，本发明的工艺可以用来产生既包括全硅化物PMOS栅电极又包括全硅化物NMOS栅电极的CMOS器件。
在高k栅介质层101和全硅化物栅电极107之间的阻挡层102的存在，可以阻止会导致费米能级钉扎的、栅电极和电介质之间的不希望的相互作用。结果，本发明的工艺可以使具有全硅化物栅电极和高k栅介质层的器件不表现出不希望的高阈值电压成为可能。
图2a-2d示出当实施本发明的方法中的第二个实施例时可以形成的结构的横截面图。在这个实施例中，形成包括金属NMOS栅电极和全硅化物PMOS栅电极的CMOS器件。图2a示出在制造CMOS器件时可能形成的中间结构。该结构包括衬底200的第一部分201和第二部分202。隔离区203将第一部分201与第二部分202分开。高k栅介质层205形成在衬底200上，阻挡层207形成在高k栅介质层205上。多晶硅层形成在阻挡层207上。多晶硅层的第一部分204被一对侧壁间隔层208和209夹在中间，并且多晶硅层的第二部分206被一对侧壁间隔层210和211夹在中间。电介质212与该侧壁间隔层相邻。
衬底200可以包含任何可以作为在其上构建半导体器件的基础的材料。隔离区203可以包含二氧化硅或其他可以隔离晶体管有源区的材料。高k栅介质层205和阻挡层207可以包含上面确定的任何材料，并且可以使用正如上面说明的常规工艺来形成。多晶硅层的第一和第二部分204和206各自优选介于约100和约2,000埃之间的厚度，更优选介于约500和约1,600埃之间的厚度。
第一部分204可以非掺杂或掺杂砷、磷或其他n型材料。在一优选实施例中，第一部分204是n型掺杂而第二部分206是p型掺杂，例如，用硼掺杂第二部分206。当掺杂硼的时候，p型多晶硅层206应该包含足够浓度的该元素，以确保在为了去除第一部分204而进行的后续的湿法刻蚀时不会去除大量的p型多晶硅层206。间隔层208、209、210和211优选包含氮化硅，而电介质212可以包含二氧化硅或低k材料。
常规的工艺步骤、材料和设备可以用来产生图2a的结构，这对本领域技术人员来说是显而易见的。如所示，电介质212已经被回抛光，例如，通过常规的CMP的操作，以暴露出多晶硅层的第一和第二部分204和206。尽管没有示出，但是图2a结构可以包含许多其他的部件(例如，氮化硅刻蚀停止层、源和漏区和一层或多层的缓冲层)，这些部件可以使用常规的工艺形成。
在形成图2a的结构后，可去除第一部分204。在一个优选实施例中，通过运用湿法刻蚀工艺对于p型多晶硅层206上的第一部分204有选择地去除第一部分204而不去除p型多晶硅层206的大部分来去除第一部分204。这种湿法刻蚀工艺可包括在足够的温度下把第一部分204暴露于包含氢氧化物源的水溶液足够的时间，以基本上去除所有的部分204。该氢氧化物源可以包含在去离子水中体积百分比介于约2％和约30％之间的氢氧化铵或氢氧化四烷基铵，例如，氢氧化四甲铵(“TMAH”)。
例如，第一部分204可以通过将其暴露于溶液而选择性地去除，该溶液的温度维持在介于约15℃和约90℃之间(且优选低于约40℃)，该溶液包含在去离子水中体积百分比约2和约30之间的氢氧化铵。在该优选持续至少一分钟的暴露步骤中，理想的方式是在介于约1和约10瓦特/cm2之间损耗的同时施加频率介于约10KHz和约2,000KHz之间的声波能量。
在一特别优选的实施例中，具有约1,350埃的厚度的第一部分204可以通过在约25℃下暴露于溶液约30分钟而被选择性地去除，该溶液包含去离子水中体积百分比约15％的氢氧化铵，同时施加频率约1,000KHz的声波能量，以约5瓦特/cm2损耗。这种刻蚀工艺将基本上去除所有的n型多晶硅层而不去除合乎要求的(meaningful)的一定量的p型多晶硅层206。
作为一个选择方案，第一部分204可以通过将其暴露于溶液至少一分钟而被选择性的去除，该溶液的温度维持在介于约60℃和约90℃之间，该溶液包含去离子水中体积百分比介于约20％和约30％之间的TAMH，同时施加声波能量。通过将其在80℃下暴露于溶液去约2分钟，去除具有约1,350埃厚度的第一部分204，该溶液包含去离子水中的体积百分比约25％的TAMH，同时在约1,000KHz下施加声波能量，以约5瓦特/cm2损耗。这种刻蚀工艺将基本上去除所有的第一部分204而不去除大量的p型多晶硅层206。
去除第一部分204后，可以去除阻挡层207下面部分，例如，应用选择性地刻蚀高k栅介质层205上的阻挡层207的工艺。去除第一部分204和阻挡层207生成沟槽213，它们位于侧壁间隔层208和209之间，如图2b所示。尽管在这个实施例中，在去除上面的多晶硅层的第一部分204之后(或同时)去除阻挡层207，在可选择的实施例中，可以保留阻挡层207，这取决于第一部分204的成分和用来去除它的工艺。
在这个实施例中，在去除第一部分204和下面的阻挡层207部分之后，在沟槽213内和高k栅介质层205上形成n型金属层215，产生了图2c的结构。N型金属215可以包含任何n型导电材料，金属NMOS栅电极可由该导电材料获得。可以用来形成n型金属层215的材料包括：铪、锆、钛、钽、铝和它们的合金，例如包含这些元素的金属碳化物，即，碳化铪、碳化锆、碳化钛、碳化钽和碳化铝。另外，N型金属层215也可包含铝化物，例如，一种包含铪、锆、钛、钽或钨的铝化物。
使用公知的PVD或CVD工艺，例如，常规的溅射或原子层CVD工艺可以在高k栅介质层205上形成N型金属层215。如所示，除了填充沟槽213的位置上的部分，n型金属层215被去除。通过适当的CMP操作从该器件的其他部分去除层215。当从它的表面去除层215时，电介质212可以作为抛光停止层。N型金属层215优选作为具有介于约3.9eV和约4.2eV之间的功函数的金属NMOS栅极，并且栅极厚度介于约100埃和约2,000埃之间，且更优选厚度介于约500埃和约1,600埃之间。
尽管图2c表示一种n型金属层215填充整个沟槽213的结构，但是在另一可选实施例中，n型金属层215可以仅填充部分的沟槽213，沟槽的剩余部分填充容易抛光的材料，例如，钨、铝、钛或氮化钛。在这种可选实施例中，作为功函数金属的n型金属层215的厚度可以介于约50和约1,000埃之间，并且更优选厚度至少约100埃。
在该图示的实施例中，在沟槽213内形成n型金属层215后，基本上整个p型多晶硅层206(且最好是该层的全部)转变为硅化物216，如图2d所示。全硅化物栅电极216可以包含硅化镍、硅化钴、硅化钛、这些材料的混合物或其他可以产生高性能的全硅化物PMOS栅极的硅化物。通过在该整个结构上淀积适合的金属，然后在足够时间内加热足够温度以由p型多晶硅层206产生金属硅化物(例如，NiSi)，P型多晶硅层206可以转变为全硅化物栅电极216。
在一个优选实施例中，通过在整个结构上，包括层206的暴露表面，溅射适合的金属(例如，镍)而形成硅化物216。为了使硅化物216完全在整个p型多晶硅层206上延伸，有必要在进行了该溅射后进行高温退火，例如，在至少约450℃的温度下进行的快速热退火。当形成硅化镍时，退火温度优选在介于约500℃和约550℃之间。当形成硅化钴时，退火温度优选在至少约600℃。
可以运用常规的CMP步骤在形成硅化物216后，从该结构上去除多余的金属，电介质212作为抛光停止层。在一优选实施例中，硅化物216作为具有介于约4.3eV和约4.8eV之间的禁带中间(mid-gap)功函数的全硅化物PMOS栅极，并且栅极厚度介于约100埃和约2,000埃之间，且更优选厚度介于约500埃和约1,600埃之间。
这里对用来形成n型金属层215和硅化物216的材料说明了几个例子，但是金属层和硅化物还可以由许多其他的材料制造，这对于本领域的技术人员来说是显而易见的。在形成硅化物216后，完成该器件的工艺步骤可以按照以下步骤：例如，在图2d所示的结构上形成覆盖介电层，然后形成器件接触、金属互连和钝化层。这种工艺步骤对于本领域技术人员来说是公知的，这里将不做更详细的说明。
本发明方法的第二实施例的使包含金属NMOS栅电极和全硅化物PMOS栅电极的CMOS器件不具有不希望的高阈值电压成为可能。上面说明的实施例对于形成这种器件的工艺提供了例子，但是本发明并不局限于这些特定实施例。
图2d的半导体器件包含分别形成在高k栅介质层205和阻挡层207上的金属NMOS栅电极215和全硅化物PMOS栅电极216。高k栅介质层205和阻挡层207可以包含以上罗列的任何材料。金属NMOS栅电极215可以完全由以上确定的一种或多种n型金属构成，或者作为另一种选择方案，可以包含由沟槽填充金属覆盖的n型功函数金属。金属NMOS栅电极215优选介于约100和约2,000埃之间的厚度，且具有介于约3.9eV和约4.2eV之间的功函数。全硅化物PMOS栅电极216优选介于约100和约2,000埃之间的厚度，具有介于4.3eV和约4.8eV之间的中间功函数，且包含以上确定的硅化物之一。
本发明的半导体器件可以用上面详细提到的工艺制造，但也可以使用其他类型的工艺。因此，半导体器件并不局限于用上述工艺制造的器件。
本发明的方法可以使具有全硅化物栅电极和高k栅介质层的器件不表现出不希望的高阈值电压成为可能。上面的描述说明了本发明中可以使用的具体的某些步骤和材料，但本领域技术人员明白：可以作出许多修改和替代。因此，所有这些修改、改变、替换和增加应被视为不脱离附加的权利要求所限定的本发明的精神和范围。

Claims (20)

1、一种制造半导体器件的方法，包括：
在衬底上形成高k栅介质层；
在该高k栅介质层上形成阻挡层；
且在该阻挡层上形成全硅化物栅电极。
2、如权利要求1所述的方法，其中该高k栅介质层包含从氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物和铌化铅锌构成的组中选择的一种材料。
3、如权利要求1所述的方法，其中，所述阻挡层是导电的和功函数透明的。
4、如权利要求3所述的方法，其中，所述阻挡层包含金属氮化物。
5、如权利要求1所述的方法，其中，所述全硅化物栅电极包含从硅化镍、硅化钴和硅化钛构成的组中选择的一种材料。
6、如权利要求1所述的方法，其中，基本上所有的p型多晶硅层转变为硅化物以生成该全硅化物栅电极。
7、如权利要求1所述的方法，其中，所有的p型多晶硅层转变为硅化物以生成该全硅化物栅电极。
8、一种制造半导体器件的方法，包括：
在衬底上形成高k栅介质层；
在该高K栅介质层上形成阻挡层；
在该阻挡层上形成多晶硅层；
去除该多晶硅层的第一部分以生成位于一对侧壁间隔层之间的沟槽；
在该沟槽内形成n型金属层；
在该多晶硅层的第二部分淀积第二金属层；
在足够的温度下加热足够长的时间使多晶硅层的第二部分基本上全部转变为金属硅化物。
9、如权利要求8所述的方法，其中，所述n型金属层包含从铪、锆、钛、钽、铝、金属碳化物和铝化物构成的组中选择的一种材料。
10、如权利要求8所述的方法，其中，所述金属硅化物从硅化镍、硅化钴和硅化钛构成的组中选择。
11、如权利要求8所述的方法，其中，所述n型金属层具有介于约3.9eV和约4.2eV之间的功函数，并且所述金属硅化物具有介于约4.3eV和约4.8eV之间的功函数。
12、如权利要求8所述的方法，其中，所述多晶硅层的第二部分是p型多晶硅层，使用对多晶硅层的第二部分上的多晶硅层的第一部分具有选择性的湿法刻蚀工艺去除该多晶硅层的第一部分。
13、如权利要求8所述的方法，其中，所有的多晶硅层的第二部分转变为金属硅化物。
14、如权利要求8所述的方法，其中，高K栅介质层包含从氧化铪、氧化锆、氧化铝构成的组中选择的一种材料，且该阻挡层包含金属氮化物。
15、如权利要求14所述的方法，其中，所述阻挡层包含从氮化钛和氮化钽构成的组中选择的一种材料。
16、一种半导体器件，包括：
形成在衬底上的高k栅介质层；
形成在该高k栅介质层上的阻挡层；
和形成在该阻挡层上的全硅化物栅电极。
17、如权利要求16的半导体器件，其中，所述阻挡层包含金属氮化物，并且所述栅电极包含从硅化镍、硅化钴和硅化钛构成的组中选择的一种金属硅化物。
18、如权利要求17的半导体器件，其中，所述高k栅介质层包含从氧化铪、氧化锆、氧化铝构成的组中选择的一种材料，且所述阻挡层包含从氮化钛和氮化钽构成的组中选择的一种材料。
19、如权利要求16的半导体器件，其中，所述全硅化物栅电极包含PMOS栅电极，还包含金属NMOS栅电极。
20、如权利要求19的半导体器件，其中，所述金属NMOS栅电极的厚度介于约100和约2,000埃之间，具有介于约3.9eV和约4.2eV之间的功函数，且包含从铪、锆、钛、钽、铝、金属碳化物和铝化物构成的组中选择的一种材料；且所述PMOS栅电极的厚度介于约100和约2,000埃之间，具有介于约4.3eV和约4.8eV之间的功函数。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102299077A (zh) * 2010-06-28 2011-12-28 中国科学院微电子研究所 一种半导体器件及其制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7557032B2 (en) * 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
JP2007158065A (ja) * 2005-12-06 2007-06-21 Nec Electronics Corp 半導体装置の製造方法および半導体装置
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7871915B2 (en) * 2008-09-26 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming metal gates in a gate last process
US8222132B2 (en) * 2008-11-14 2012-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Fabricating high-K/metal gate devices in a gate last process
KR20210057201A (ko) * 2018-10-08 2021-05-20 어플라이드 머티어리얼스, 인코포레이티드 금속 기반 전구체들과 함께 ald(atomic layer deposition) 프로세스들을 사용하는 nmos(n-type metal oxide semiconductor) 금속 게이트 재료들을 위한 방법들 및 장치

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164805A (en) * 1988-08-22 1992-11-17 Massachusetts Institute Of Technology Near-intrinsic thin-film SOI FETS
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US6265749B1 (en) * 1997-10-14 2001-07-24 Advanced Micro Devices, Inc. Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant
US20020197790A1 (en) * 1997-12-22 2002-12-26 Kizilyalli Isik C. Method of making a compound, high-K, gate and capacitor insulator layer
US6255698B1 (en) * 1999-04-28 2001-07-03 Advanced Micro Devices, Inc. Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
US6184072B1 (en) * 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6475874B2 (en) * 2000-12-07 2002-11-05 Advanced Micro Devices, Inc. Damascene NiSi metal gate high-k transistor
US6602781B1 (en) * 2000-12-12 2003-08-05 Advanced Micro Devices, Inc. Metal silicide gate transistors
US6544906B2 (en) * 2000-12-21 2003-04-08 Texas Instruments Incorporated Annealing of high-k dielectric materials
KR100387259B1 (ko) * 2000-12-29 2003-06-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6410376B1 (en) * 2001-03-02 2002-06-25 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration
US6365450B1 (en) * 2001-03-15 2002-04-02 Advanced Micro Devices, Inc. Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
US6420279B1 (en) * 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US6573193B2 (en) * 2001-08-13 2003-06-03 Taiwan Semiconductor Manufacturing Co., Ltd Ozone-enhanced oxidation for high-k dielectric semiconductor devices
US6797599B2 (en) * 2001-08-31 2004-09-28 Texas Instruments Incorporated Gate structure and method
US6667246B2 (en) * 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
US6620713B2 (en) * 2002-01-02 2003-09-16 Intel Corporation Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
US6696345B2 (en) * 2002-01-07 2004-02-24 Intel Corporation Metal-gate electrode for CMOS transistor applications
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6617210B1 (en) * 2002-05-31 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7081409B2 (en) * 2002-07-17 2006-07-25 Samsung Electronics Co., Ltd. Methods of producing integrated circuit devices utilizing tantalum amine derivatives
DE10234931A1 (de) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6770568B2 (en) * 2002-09-12 2004-08-03 Intel Corporation Selective etching using sonication
US6746967B2 (en) * 2002-09-30 2004-06-08 Intel Corporation Etching metal using sonication
US6689675B1 (en) * 2002-10-31 2004-02-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6713358B1 (en) * 2002-11-05 2004-03-30 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6787440B2 (en) * 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
US6709911B1 (en) * 2003-01-07 2004-03-23 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP4209206B2 (ja) * 2003-01-14 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US6716707B1 (en) * 2003-03-11 2004-04-06 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US7279413B2 (en) * 2004-06-16 2007-10-09 International Business Machines Corporation High-temperature stable gate structure with metallic electrode
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102299077A (zh) * 2010-06-28 2011-12-28 中国科学院微电子研究所 一种半导体器件及其制造方法
CN102299077B (zh) * 2010-06-28 2013-04-10 中国科学院微电子研究所 一种半导体器件及其制造方法

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