CN1855544B - 具有屏蔽电极的半导体器件及其方法 - Google Patents
具有屏蔽电极的半导体器件及其方法 Download PDFInfo
- Publication number
- CN1855544B CN1855544B CN200610075128XA CN200610075128A CN1855544B CN 1855544 B CN1855544 B CN 1855544B CN 200610075128X A CN200610075128X A CN 200610075128XA CN 200610075128 A CN200610075128 A CN 200610075128A CN 1855544 B CN1855544 B CN 1855544B
- Authority
- CN
- China
- Prior art keywords
- type surface
- type
- layer
- electrode
- tagma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000009411 base construction Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 8
- 238000012216 screening Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 142
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 230000003321 amplification Effects 0.000 description 11
- 238000003199 nucleic acid amplification method Methods 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000005260 corrosion Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 8
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 239000008186 active pharmaceutical agent Substances 0.000 description 7
- 125000004429 atom Chemical group 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 239000004408 titanium dioxide Substances 0.000 description 2
- 229910000632 Alusil Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-O phosphonium Chemical compound [PH4+] XYFCBTPGUUZFHI-UHFFFAOYSA-O 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
在一个实施方案中,半导体器件被形成在半导体材料的本体中。此半导体器件包括分隔于沟道区的屏蔽电极。
Description
技术领域
本发明一般涉及到半导体器件,更确切地说是涉及到功率开关器件及其制造方法,此功率开关器件包括诸如RF功率放大器之类的高速器件。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是一种普通的功率开关器件。MOSFET器件包括源区、漏区、延伸在源区与漏区之间的沟道区、以及提供在沟道区附近的栅结构。此栅结构包括排列在沟道区附近且被薄的介质层分隔于沟道区的导电的栅电极。
当MOSFET器件处于开通状态时,电压被施加到栅结构,以便在源区与漏区之间形成导电沟道区,使电流能够流过器件。在关断状态下,施加到栅结构的任何电压都足够低,致使不形成导电沟道区,电流因而不流动。在关断状态过程中,器件必须承受源区与漏区之间的高电压。
在优化MOSFET器件的性能时,设计者常常面对器件参数性能的折中。具体地说,可得到的器件结构或制作工艺的选择可以改善一种器件参数,但这些选择可能同时使其它的一个或多个器件参数变坏。例如,对MOSFET器件的输出或驱动电流(IDS)容量和开态电阻有改善的可用结构和工艺,同时也使其击穿电压(BVDSS)容量变坏,还增大栅-漏电容。
因此,需要有改进了的半导体器件结构及其制造方法来解决上述和其它的问题。
发明内容
根据本发明的一方面,提供一种半导体器件,它包含:具有主表面的衬底,其中,衬底包含第一导电类型;形成且覆盖在部分主表面上的基座结构;沿基座结构侧面设置以限定半导体器件第一导电电极的边沿的导电材料;形成在第一导电电极附近的主表面中的第二导电类型的第一掺杂区,其中,当半导体器件工作时,部分第一掺杂区构成沟道区;形成在第一掺杂区中的第一导电类型的第一电流承载区;以及形成在主表面附近和第一掺杂区紧邻的屏蔽电极。
根据本发明的另一方面,提供一种半导体器件,它包含:具有第一导电类型的半导体层的半导体衬底,其中,半导体层具有主表面;设置在半导体层中用来形成半导体器件的沟道的第二导电类型的本体区;形成在本体区中的第一导电类型的第一电流承载区;形成在邻近沟道的顶部表面上的栅结构;以及形成在紧邻本体区的半导体层中的屏蔽电极。
根据本发明的另一方面,提供一种制作半导体器件的方法,它包含下列步骤:提供具有第一导电类型的半导体层的半导体衬底,其中,半导体层具有主表面;形成设置在半导体层中用来形成半导体器件的沟道的第二导电类型的本体区;在本体区中形成第一导电类型的第一电流承载区;形成邻接沟道附近主表面的栅结构;以及在紧邻本体区的半导体层中形成屏蔽电极。
附图说明
图1示出了根据本发明一个实施方案的半导体结构的高度放大的局部剖面图;
图2曲线示出了本发明各种实施方案的漏饱和电流(IDSat)与屏蔽电极偏压(VOS)的函数关系;
图3曲线示出了本发明各种实施方案的击穿电压(BVDSS)与屏蔽电极偏压(VOS)的函数关系;
图4曲线示出了本发明各种实施方案在图2和3的各种屏蔽电极偏压下的IDSat与BVDSS的相互关系;
图5示出了本发明一个实施方案在制造的早期阶段的高度放大的局部剖面图;
图6示出了本发明一个实施方案在制造稍后期阶段的高度放大的局部剖面图;
图7示出了本发明一个实施方案在制造更后期阶段的高度放大的局部剖面图;
图8示出了本发明一个实施方案在制造更后期阶段的高度放大的局部剖面图;
图9示出了本发明一个实施方案在制造更后期阶段的高度放大的局部剖面图;而
图10示出了本发明一个实施方案在额外制造阶段之后的高度放大的局部剖面图。
具体实施方式
为了易于理解,附图中的各元件无须按比例绘制,相似的参考号被用于所有附图的适当地方。虽然下面的讨论描述了一种n沟道器件,但本发明也涉及到可以借助于反转所述层和区的导电类型来制作的p沟道器件。
此外,本发明的器件可以包括网格设计(其中,本体区是多个网格区)或单体设计(其中,本体区由形成在典型为螺旋图形的伸长图形中的单个区域组成)。但为了易于理解,在整个描述中,本发明的器件将被描述成网格设计。应该理解的是,本发明包罗了网格设计和单体设计二者。此外,虽然本发明的器件被示为MOSFET器件,但本发明也适用于双极晶体管和绝缘栅双极晶体管以及包含输入端子、输出端子、和控制电极的其它器件。
图1为放大的局部剖面图,示出了根据本发明一个实施方案的绝缘栅场效应晶体管(IGFET)、MOSFET、功率晶体管、或开关器件和单元10。举例来说,器件10是与逻辑和/或其它元件集成到一个半导体芯片中作为功率集成电路部分的许多这种器件中的一种。或者,器件10是集成到一起以形成分立晶体管器件的许多这种器件中的一种。
器件10包括半导体材料区11,此半导体材料区11包含例如电阻率约为0.001-0.005欧姆厘米的n型硅衬底12,并可以用砷来掺杂。在所示实施方案中,衬底12提供了漏接触即第一电流承载接触。半导体层或延伸的漏区14被形成在衬底12中或衬底12上。在一个实施方案中,用常规外延生长技术来形成半导体层14。或者,用常规的掺杂和扩散技术来形成半导体层14。在适合于50V器件的一个实施方案中,半导体层14是掺杂浓度约为每立方厘米1.0×1015原子且厚度约为3-5微米的n型。半导体层14的厚度和掺杂剂浓度依赖于器件10所希望的BVDSS额定值而被增大或减小。要理解的是,包括硅锗、硅锗碳、掺碳的硅、碳化硅等的其它材料也可以被用于半导体材料11的本体或其各个部分。此外,在一个变通实施方案中,衬底12的导电类型被转换成相反于半导体层14的导电类型,以便制作绝缘栅双极晶体管10。
器件10还包括形成在半导体材料区11上部主表面18中或附近的n型区即满铺层17.n型区17提供了器件10的低阻电流通路.在一个示例性实施方案中,n型区17的最高浓度约为每立方厘米6.0×1016原子,深度约为0.4微米。
本体区、基区、或掺杂区31被形成在半导体层14中,并从主表面18延伸。举例来说,本体区31包含p型导电性,并具有适合于形成用作器件10导电沟道45的反型层的掺杂剂浓度。本体区31从主表面18延伸到例如约为0.5-3.0微米的深度。n型源区即电流承载区33被形成在本体区31内,并从主表面18延伸到例如约为0.1-0.5微米的深度。p型本体接触即接触区36也被形成在本体区31中,并提供到主表面18处本体区31的较低的接触电阻。此外,接触区36降低了源区33下方的本体区31的薄层低阻,这就抑制了寄生双极效应。
第一介质层41被形成在部分主表面上或附近。例如,介质层41包含厚度约为0.05-0.2微米的热氧化层。第二介质层42被形成在介质层41上。在一个实施方案中,第二介质层42包含氮化硅,且厚度约为0.05-0.1微米。
根据本发明,沟槽电极、屏蔽电极、屏蔽端子、或第二控制端子结构21,以间隔关联于本体区31,或紧贴本体区31的方式,被形成在本体区31附近。在一个实施方案中,各个结构21包含形成在部分半导体层14中的沟槽23。结构21还包括形成在沟槽23表面上的第三介质层、电极隔离层、或栅绝缘层24。第三介质层24包含例如厚度约为0.03-0.1微米的氧化硅层。在一个变通实施方案中,第三介质层24包含氮化硅、五氧化钽、二氧化钛、钛酸锶钡、或它们的组合,包括与氧化硅的组合等。
掺杂的多晶半导体层即导电层46被形成在第三介质层24和第二介质层42上。在一个实施方案中,导电层46包含掺杂浓度约为每立方厘米5.0×1020原子且厚度约为0.1微米的n型导电类型的掺杂多晶硅。在一个变通实施方案中,导电层46包含p型导电性。举例来说,沟槽23被分隔于本体区31大约0.5-3.0微米的距离26。再举例来说,沟槽23从主表面18延伸大约0.5-1.5微米的距离27。
第四介质层48被形成在导电层46上,且第五介质层51被形成在第四介质层48上。举例来说,介质层48包含氮化硅(例如厚度约为0.05微米),且介质层51包含淀积的氧化硅(例如厚度约为0.7微米)。在一个实施方案中,介质层51包含整平了的介质,以便补偿沟槽23的存在。例如,在淀积之后,用化学机械抛光技术之类来整平介质层51。导电层53被形成在介质层51上,且包含例如n型多晶硅(例如厚度约为0.3微米)。
栅介质层43被形成在邻近本体区31的其它部分主表面18上或贴近主表面18。栅介质层43包含例如氧化硅,且厚度约为0.01-0.1微米。在变通实施方案中,栅介质层43包含氮化硅、五氧化钽、二氧化钛、钛酸锶钡、或它们的组合,包括与氧化硅的组合等。
导电的隔板栅区、垂直隔板栅区、或确定栅区的隔板即导电电极57,被形成在栅介质层43上,并被介质隔板59隔离于导电层46。导电隔板栅区57与栅介质层43一起构成控制电极、栅电极、或第一控制端子结构58。导电隔板栅区57包含例如n型多晶硅,且厚度约为0.2-0.8微米。在一个示例性实施方案中,介质隔板59包含氮化硅,且厚度约为0.1微米。隔板栅区57被耦合到导电层53,以便提供导电的栅结构,此栅结构控制着沟道45的形成以及电流在器件10中的传导。
在所示的实施方案中,导电连接部分77将隔板栅区57耦合到导电层53.导电连接部分77包含例如n型多晶硅.确定栅区的隔板指的是由淀积在一个表面上的栅材料形成以控制形成在另一与之垂直的表面上沟道的控制电极.在器件10的情况下,沟道45被形成在主表面18处,主表面18被认为是水平表面.用来形成隔板栅区57的控制电极膜沿垂直于表面18的垂直表面68被淀积.
与常规器件相比,导电隔板栅区57提供了最小的栅-漏重叠,从而显著地减少了栅电荷。此外,在器件10中,栅的电通路由抬高到主表面18上方的导电层53提供,从而进一步减少了栅电荷。而且,导电层46除了其它作用之外,还用作接地平面或插入在栅区与漏区之间的屏蔽层,以便进一步减小栅-漏电容。这些特点提供了提高的开关速度和降低了的输入电荷要求。
第六介质层61被形成在部分器件10上,且包含例如厚度约为0.05微米的氮化硅。层间介质(ILD)层62被提供在部分器件10上,且包含例如厚度约为0.8微米的淀积氧化硅。窗口被形成在这些介质层中,以便提供到源接触层63的器件10的接触。如所示,部分主表面18被腐蚀,使源接触层63形成到源区33和本体区36二者的接触。在一个实施方案中,源接触层63包含铝硅合金之类。漏接触层或导电电极66被形成在半导体材料区11的反面上,且包含诸如钛-镍-银、铬-镍-金之类的可焊接的金属结构。
器件10的工作如下进行。假设源或输入端子63工作于0V的电位VS,隔板栅区57接收大于器件10的导电阈值的控制电压VG=2.5V,且漏或输出端子66工作于漏电位VD=5.0V。VG和VD的数值引起隔板栅区57下方的本体区31反型而形成沟道45,使源区33电连接到层17。器件电流IDS从源端子63通过源区33、沟道45、层17、以及半导体层14流到漏端子66。在一个实施方案中,IDS=1.0A。为了将器件10转换到关断状态,小于器件导电阈值的控制电压VG被施加到隔板栅57(例如VG小于2.5V)。这就消除了沟道45,IDS因而不再流过器件10。
屏蔽电极21被连接、耦合、或固定到相同于电源电压、中间电压、独立电压、电压信号、或地电位的电位VO。在关断状态下,屏蔽电极21用作栅控制电极58与漏或输出电极66之间的电压屏蔽。亦即,屏蔽电极21用来整平静电电位,并在器件10处于关断或锁闭状态时,用来减小出现在本体区31和半导体层14的角落处的曲率半径效应。
更确切地说,屏蔽电极21将器件10的输入与输出之间的大电位差分成二个部分,较大的部分在屏蔽电极21与输出端子(例如漏端子66)之间,而较小的部分在屏蔽电极21与栅结构58和输入端子(例如源端子63)之间。此电压差产生一些结果。
首先,传统的高电压技术能够被用来适应屏蔽电极21与输出端子之间的电位差的较大部分,这使器件10更兼容现有的高电压技术。这些技术包括调整半导体层14的厚度和掺杂剂浓度以及介质层24的厚度,以便满足击穿电压要求。由于屏蔽电极21的电压屏蔽作用,诸如栅氧化物43的厚度或层17的掺杂剂浓度之类的器件10的其它部分就能够按比例缩放到若没有电压屏蔽作用则可能不容易做到的数值。这改善了器件10的总体性能,包括电流容量和开关速度的改善。
此外,由于屏蔽电极21将控制电极58隔离于输出端子66及其终端负载(VD),故能够得到更理想的输出特性。例如,提供的隔离导致了输出电流(IDS)对输出电压(VD)的变化更不敏感,从而仅仅依赖于控制电压(VG)的改变。
最后,当器件10处于开通状态时,屏蔽电极21能够被用来在沟槽23的表面处产生电荷积累,这进一步用来提高漏电流IDS,并降低开态低阻。
图2曲线示出了器件10在VGS偏压5.0V下的漏电流IDS与施加到屏蔽电极21的独立屏蔽-源电压(VOS=VO-VS)的函数关系性能。此外,图2比较了具有p型导电层46的器件10(数据3A)和具有n型导电层46的器件10(数据4A)。这二种结构被进一步与具有平坦或无沟槽结构的具有p型电极的器件进行了比较(数据1A)以及与具有平坦或无沟槽结构的具有n型电极的器件进行了比较(数据2A)。
图3曲线示出了击穿电压(BVDSS)与施加到屏蔽电极21的独立屏蔽-源电压(VOS)的函数关系。此外,图3比较了具有p型导电层46的器件10(数据3B)和具有n型导电层46的器件10(数据4B)。这二种结构被进一步与具有平坦或无沟槽结构的具有p型电极的器件进行了比较(数据1B)以及与具有平坦或无沟槽结构的具有n型电极的器件进行了比较(数据2B)。
作为图2和3的一种合成或相互关系,图4曲线示出了IDSAT与BVDSS的函数关系。数据组成部分1C相当于具有p型电极的平坦结构,数据组成部分2C相当于具有n型电极的平坦结构,数据组成部分3C相当于具有p型导电层46的器件10,数据组成部分4C相当于具有n型导电层46的器件10。如图4所示,根据本发明的具有屏蔽电极21的器件10提供了增强的BVDSS性能,同时得到了优异的IDSAT特性。
现在参照图5-10来描述根据本发明的制作器件10的工艺。图5示出了器件10在制造的早期阶段中的放大局部剖面图。半导体材料11的本体由形成在半导体层14中的n型层17提供。在一个实施方案中,在约为每平方厘米2.0×1012原子的剂量和600KeV的注入能量下,磷被注入,以便形成n型层17。第一介质层41被形成在主表面18上,且包含例如厚度约为0.05-0.2微米的氧化硅。在大约900℃下生长的热氧化物是合适的。然后,第二介质层42被淀积在第一介质层41上,且包含例如厚度约为0.05-0.1微米的氮化硅。接着,常规的光刻和腐蚀步骤被用来在第一和第二介质层41和42中形成窗口,以便暴露部分主表面18。接着,沟槽23被形成在半导体层14中,且从主表面18延伸。举例来说,在采用氟基或氯基化学剂的干法腐蚀系统中来腐蚀沟槽23。沟槽23包含单个连续沟槽或连接的沟槽矩阵。或者,沟槽23包含具有端部靠近并被半导体材料11本体部分分隔的多个分立的沟槽。然后,第三介质层24被形成在沟槽23的表面上,且包含例如厚度约为0.03-0.1微米的氧化硅。
图6示出了器件10在稍后制作阶段中的高度放大局部剖面图。然后,导电层46被形成在第三介质层24以及第二介质层42的剩余部分上。在一个实施方案中,导电层46包含大约0.1微米的多晶硅,并被淀积成掺杂的或不掺杂的。若导电层46一开始被淀积成不掺杂的,则随后用例如离子注入技术来对导电层46进行掺杂。在一个实施方案中,导电层46是用磷掺杂的n型的。大约每平方厘米5.0×1015原子~每平方厘米1.0×1016原子的磷离子注入剂量和大约60KeV的注入能量,足以对导电层46进行掺杂。在一个变通实施方案中,导电层46包含p型导电性,且大约每平方厘米5.0×1015原子~每平方厘米1.0×1016原子的硼离子注入剂量和大约30KeV的注入能量,足以对导电层46进行掺杂。
接着,第四介质层48被形成在导电层46上,且第五介质层51被形成在第四介质层48上。第四介质层48包含例如氮化硅(例如厚度约为0.05微米),而介质层51包含淀积的氧化物(例如厚度约为0.7微米)。在一个实施方案中,用例如化学机械抛光工艺之类来整平第五介质层51的上表面。
然后,导电层53被形成在第五介质层51上,且包含例如n型多晶硅(例如厚度约为0.3微米)。保护层54被形成在导电层53上,且包含例如大约0.15微米的氮化硅。
完成光刻和腐蚀步骤,以便腐蚀穿过部分层54、53、51、48、46、42,以提供窗口70。这也形成了由层42、46、48、51、53、54的剩余部分组成的一些基座叠层结构56。在一个实施方案中,窗口70具有约为5.0-8.0微米的宽度73。
图7示出了器件10在形成介质隔板59的其它加工步骤之后的放大局部剖面图。在一个实施方案中,氮化硅膜被淀积在基座叠层结构56和第一介质层41上。举例来说,用化学气相淀积技术,淀积了大约0.1微米厚的氮化硅膜。接着,常规各向异性回腐蚀步骤被用来清除基座叠层结构56和第一介质层41上的部分氮化硅层,同时留下侧壁即垂直表面68上的部分氮化硅层,以形成介质隔板59。
然后,在以下的步骤中,氧化硅湿法腐蚀被用来清除窗口70内的部分介质层41。举例来说,稀释的氢氟酸(例如50∶1)被用来腐蚀介质层41。在一个示例性实施方案中,腐蚀时间被延长(例如8-15分钟),以便钻蚀,即从介质隔板59下面清除介质层41的材料以形成凹陷部分74。以这种方式使介质层41凹陷,确保了形成在本体区31中的沟道45(图1所示)延伸进入到半导体层14中,以便使沟道电流能够更有效地流动。在一个示例性实施方案中,部分74在介质隔板59下方被凹陷一个小于大约0.1微米的距离。然后,热氧化硅被生长在窗口内的主表面18上,厚度约为0.0125微米,以便形成栅绝缘层43。
图8示出了器件10在其它加工之后的放大局部剖面图。厚度约为0.1-0.15微米的半导体材料的共形层571被淀积在器件10上。然后通过窗口70和半导体材料共形层571,将硼掺杂剂引入到主表面18中,以便提供本体区31的p型掺杂剂。举例来说,半导体材料的共形层571包含不掺杂的多晶硅,且通过不掺杂的多晶硅,硼被注入到半导体层14中。对于50V的器件,约为每平方厘米1.0×1013原子的离子注入剂量和大约120KeV的注入能量,是合适的。
图9示出了器件10在进一步加工之后的放大局部剖面图。第二半导体材料共形层被淀积在半导体材料共形层571上,并对二个层进行腐蚀,以便提供隔板栅57。举例来说,第二半导体材料共形层包含大约0.2微米的n型多晶硅,此n型多晶硅可以在淀积工艺过程中被掺杂,或随后用离子注入或其它掺杂技术来掺杂。在形成隔板栅57之后,额外的0.015微米的栅介质(例如氧化硅)被加于隔板栅57的表面,并暴露部分栅氧化物43。
在一个实施方案中,形成隔板栅57的腐蚀步骤也暴露了保护层54和介质隔板59的上部。然后,对保护层54和介质隔板59的上部进行腐蚀,以便清除保护层54,并在隔板栅57与导电层53之间清除介质隔板59的上部。这就在导电层53与隔板栅57之间留下一个间隙。
在以下的步骤中,诸如多晶硅之类的导电材料被淀积,以便提供连接用的导电部分77。连接用的导电部分77填充了在保护层54和部分介质隔板59清除过程中所形成的间隙,并将隔板栅57耦合即电连接到导电层53。然后完成n型掺杂步骤,以便对连接用的导电部分77进行掺杂,从而为源区33提供掺杂剂。在一个示例性实施方案中,每平方厘米3.0×1015原子的砷注入剂量和80KeV的注入能量,被用于此掺杂步骤。在一个实施方案中,注入的掺杂剂然后在制作的这一阶段被激活而扩散。或者,在下面图10所述的步骤之后来激活和扩散掺杂剂。
图10示出了器件10在进一步制作步骤之后的放大局部剖面图。第六介质层61被淀积,且包含例如大约0.05微米的氮化硅。然后,ILD层62被淀积在第六介质层61上。在一个示例性实施方案中,ILD层62包含厚度约为0.8微米的淀积的氧化硅。可选的ILD锥形腐蚀被用来形成ILD层62的锥形部分62a,这有助于随后形成的各个层的台阶覆盖。
接着,常规的光刻和腐蚀步骤被用来形成暴露部分主表面18的接触窗口81。然后,利用p型离子注入步骤,通过窗口81来形成接触区36。举例来说,采用了每平方厘米3.0×1014原子的硼离子注入剂量和80KeV的注入能量。然后,共形隔板层被淀积和腐蚀,以便形成隔板82。在一个示例性实施方案中,0.3微米的氮化硅层被淀积和腐蚀,来形成隔板82。此时,快速退火步骤被用来激活和扩散各种离子注入剂。例如,器件10被暴露于大约1030℃的温度大约45秒钟。
然后,用腐蚀步骤来清除部分主表面18,以便形成凹陷部分84。这使源接触层63能够与源区33和接触区36二者相接触,将这些区域短路到一起。然后清除隔板82。在随后的加工中,源接触层63被淀积并图形化。然后可选地减薄衬底12,并淀积漏接触层66,以便提供图1所示的结构。还要理解的是,可以在淀积源接触层63之前来形成诸如硅化物层之类的其它导电层。
考虑到上述所有情况,显然公开了一种新颖的器件及其制造方法。除了其它特点之外,所包括的是一种具有屏蔽电极的半导体器件,这些屏蔽电极形成在器件沟道区附近,提高了击穿电压性能。这些屏蔽电极还使得能够使用沟道区与屏蔽电极之间的n型掺杂区,这就改善了漏电流和开态电阻而不对开关性能造成明显的冲击。
虽然参照器具体实施方案已经描述了本发明,但不要认为本发明局限于这些示例性实施方案。本技术领域的熟练人员可以理解的是,能够作出各种修正和改变而不偏离本发明的构思。
因此认为本发明包罗了所附权利要求范围内的所有这些改变和修正。
Claims (10)
1.一种半导体器件,其特征在于包含:
具有主表面的衬底,其中,衬底包含第一导电类型;
形成且覆盖在部分主表面上的基座结构,所述基座结构具有与所述主表面垂直的侧面;
沿基座结构的所述侧面设置以限定半导体器件第一导电电极的边沿的导电材料;
形成在第一导电电极附近的并在所述主表面附近的第二导电类型的第一掺杂区,其中,当半导体器件工作时,部分第一掺杂区构成沟道区;
形成在第一掺杂区中的第一导电类型的第一电流承载区;以及
形成在所述衬底中并与所述第一掺杂区横向隔开地形成的屏蔽电极,所述衬底的一部分在所述主表面处位于所述第一掺杂区与所述屏蔽电极之间,所述屏蔽电极的特征在于包含:
形成在所述主表面中的沟槽,
形成在所述沟槽的表面上方的介质层,以及
形成在所述介质层上方的导电层。
2.权利要求1的半导体器件,其特征还在于:
具有在所述主表面处位于所述屏蔽电极与所述第一掺杂区之间的第一导电类型的第二掺杂区,所述第二掺杂区被配置为提供低阻电流通路。
3.权利要求1的半导体器件,其中,屏蔽电极被耦合到第一电流承载区。
4.权利要求1的半导体器件,其中,屏蔽电极被构造成独立地偏置。
5.一种半导体器件,其特征在于包含:
具有第一导电类型的半导体层的半导体衬底,其中,半导体层具有主表面;
设置在所述半导体层中用来形成半导体器件的沟道的第二导电类型的本体区;
形成在本体区中的第一导电类型的第一电流承载区;
形成在邻近沟道的上述主表面上的栅结构;以及
形成在所述半导体层中的屏蔽电极,所述屏蔽电极从所述主表面延伸并与所述本体区横向隔开,使得所述半导体层的第一部分位于所述屏蔽电极与所述本体区之间,其中所述屏蔽电极的特征在于包含:
形成在所述主表面中的沟槽,
形成在所述沟槽中的介质层,
形成在所述介质层上的导电电极,以及
形成在所述第一部分中、紧邻所述主表面的第一导电类型区,所述第一导电类型区被配置为提供低阻电流通路。
6.权利要求5的半导体器件,其中,所述导电电极包含具有第二导电类型的多晶硅。
7.权利要求5的半导体器件,其中,所述半导体衬底具有第二导电类型。
8.一种制作半导体器件的方法,其特征在于包含下列步骤:
提供具有第一导电类型的半导体层的半导体衬底,其中,半导体层具有主表面;
在所述半导体层中形成第一导电类型区,所述第一导电类型区被配置为提供低阻电流通路;
形成设置在半导体层中用来形成半导体器件的沟道的第二导电类型的本体区;
在本体区中形成第一导电类型的第一电流承载区;
形成邻接沟道附近主表面的栅结构;以及
在紧邻本体区的半导体层中形成屏蔽电极,所述第一导电类型区的一部分在所述主表面处位于所述屏蔽电极与所述本体区之间,其中形成所述屏蔽电极的特征在于包含以下步骤:
在所述主表面中形成沟槽,
在所述沟槽中形成介质层,
在所述介质层上形成导电电极。
9.权利要求8的方法,其特征在于,形成栅结构的步骤包含下列步骤:
在所述主表面上形成基座结构,所述基座结构具有与所述主表面垂直的侧面;
沿所述侧面形成导电电极。
10.权利要求9的方法,其中,形成导电电极的步骤的特征在于包括形成n型多晶硅电极的步骤。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/112,570 | 2005-04-25 | ||
US11/112,570 US7276747B2 (en) | 2005-04-25 | 2005-04-25 | Semiconductor device having screening electrode and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1855544A CN1855544A (zh) | 2006-11-01 |
CN1855544B true CN1855544B (zh) | 2010-05-12 |
Family
ID=37185967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200610075128XA Expired - Fee Related CN1855544B (zh) | 2005-04-25 | 2006-04-24 | 具有屏蔽电极的半导体器件及其方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7276747B2 (zh) |
KR (2) | KR101293927B1 (zh) |
CN (1) | CN1855544B (zh) |
HK (1) | HK1097098A1 (zh) |
TW (1) | TWI420675B (zh) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010050374A (ja) * | 2008-08-25 | 2010-03-04 | Seiko Instruments Inc | 半導体装置 |
US7915672B2 (en) * | 2008-11-14 | 2011-03-29 | Semiconductor Components Industries, L.L.C. | Semiconductor device having trench shield electrode structure |
US7902017B2 (en) * | 2008-12-17 | 2011-03-08 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a trench and a conductive structure therein |
US7989857B2 (en) * | 2008-12-17 | 2011-08-02 | Semiconductor Components Industries, Llc | Electronic device including an insulating layer having different thicknesses and a conductive electrode and a process of forming the same |
US7868379B2 (en) | 2008-12-17 | 2011-01-11 | Semiconductor Components Industries, Llc | Electronic device including a trench and a conductive structure therein |
US8124468B2 (en) | 2009-06-30 | 2012-02-28 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a well region |
US8222695B2 (en) | 2009-06-30 | 2012-07-17 | Semiconductor Components Industries, Llc | Process of forming an electronic device including an integrated circuit with transistors coupled to each other |
US8299560B2 (en) * | 2010-02-08 | 2012-10-30 | Semiconductor Components Industries, Llc | Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same |
US8389369B2 (en) * | 2010-02-08 | 2013-03-05 | Semiconductor Components Industries, Llc | Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same |
US8298886B2 (en) * | 2010-02-08 | 2012-10-30 | Semiconductor Components Industries, Llc | Electronic device including doped regions between channel and drain regions and a process of forming the same |
US9029945B2 (en) * | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
CN102263133B (zh) * | 2011-08-22 | 2012-11-07 | 无锡新洁能功率半导体有限公司 | 低栅极电荷低导通电阻深沟槽功率mosfet器件及其制造方法 |
CN103918079B (zh) | 2011-09-11 | 2017-10-31 | 科锐 | 包括具有改进布局的晶体管的高电流密度功率模块 |
US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
US8647970B2 (en) | 2011-12-15 | 2014-02-11 | Semiconductor Components Industries, Llc | Electronic device comprising conductive structures and an insulating layer between the conductive structures and within a trench |
US8592279B2 (en) | 2011-12-15 | 2013-11-26 | Semicondcutor Components Industries, LLC | Electronic device including a tapered trench and a conductive structure therein and a process of forming the same |
US8541302B2 (en) | 2011-12-15 | 2013-09-24 | Semiconductor Components Industries, Llc | Electronic device including a trench with a facet and a conductive structure therein and a process of forming the same |
US8679919B2 (en) | 2011-12-15 | 2014-03-25 | Semiconductor Components Industries, Llc | Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same |
US9818831B2 (en) | 2013-03-11 | 2017-11-14 | Semiconductor Components Industreis, Llc | DMOS transistor including a gate dielectric having a non-uniform thickness |
US9520390B2 (en) | 2013-03-15 | 2016-12-13 | Semiconductor Components Industries, Llc | Electronic device including a capacitor structure and a process of forming the same |
US9195132B2 (en) * | 2014-01-30 | 2015-11-24 | Globalfoundries Inc. | Mask structures and methods of manufacturing |
WO2015152904A1 (en) | 2014-04-01 | 2015-10-08 | Empire Technology Development Llc | Vertical transistor with flashover protection |
US9406750B2 (en) | 2014-11-19 | 2016-08-02 | Empire Technology Development Llc | Output capacitance reduction in power transistors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2070331A (en) * | 1980-02-22 | 1981-09-03 | Rca Corp | Vertical MOSFET with a shield electrode |
DE10317381A1 (de) * | 2003-04-15 | 2004-11-18 | Infineon Technologies Ag | Leistungstransistor mit niedriger Gate-Drain-Kapazität und Verfahren zu dessen Herstellung |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303961B1 (en) * | 1998-04-29 | 2001-10-16 | Aqere Systems Guardian Corp. | Complementary semiconductor devices |
KR20000051294A (ko) * | 1999-01-20 | 2000-08-16 | 김덕중 | 전기적 특성이 향상된 디모스 전계 효과 트랜지스터 및 그 제조 방법 |
JP2002151686A (ja) * | 2000-11-15 | 2002-05-24 | Nec Corp | 半導体装置およびその製造方法 |
JP2002299609A (ja) * | 2001-03-29 | 2002-10-11 | Nec Corp | 半導体装置及びその製造方法 |
US6803317B2 (en) * | 2002-08-16 | 2004-10-12 | Semiconductor Components Industries, L.L.C. | Method of making a vertical gate semiconductor device |
US7045845B2 (en) * | 2002-08-16 | 2006-05-16 | Semiconductor Components Industries, L.L.C. | Self-aligned vertical gate semiconductor device |
US7397084B2 (en) * | 2005-04-01 | 2008-07-08 | Semiconductor Components Industries, L.L.C. | Semiconductor device having enhanced performance and method |
US7446354B2 (en) * | 2005-04-25 | 2008-11-04 | Semiconductor Components Industries, L.L.C. | Power semiconductor device having improved performance and method |
-
2005
- 2005-04-25 US US11/112,570 patent/US7276747B2/en active Active
-
2006
- 2006-04-03 TW TW095111820A patent/TWI420675B/zh active
- 2006-04-24 CN CN200610075128XA patent/CN1855544B/zh not_active Expired - Fee Related
- 2006-04-25 KR KR1020060037060A patent/KR101293927B1/ko active IP Right Grant
-
2007
- 2007-02-15 HK HK07101793.0A patent/HK1097098A1/xx not_active IP Right Cessation
-
2013
- 2013-04-05 KR KR1020130037703A patent/KR20130038896A/ko not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2070331A (en) * | 1980-02-22 | 1981-09-03 | Rca Corp | Vertical MOSFET with a shield electrode |
DE10317381A1 (de) * | 2003-04-15 | 2004-11-18 | Infineon Technologies Ag | Leistungstransistor mit niedriger Gate-Drain-Kapazität und Verfahren zu dessen Herstellung |
Non-Patent Citations (1)
Title |
---|
JP特开平11-87486A 1999.03.30 |
Also Published As
Publication number | Publication date |
---|---|
HK1097098A1 (en) | 2007-06-15 |
KR20130038896A (ko) | 2013-04-18 |
TW200727498A (en) | 2007-07-16 |
TWI420675B (zh) | 2013-12-21 |
US20060237780A1 (en) | 2006-10-26 |
US7276747B2 (en) | 2007-10-02 |
KR101293927B1 (ko) | 2013-08-08 |
CN1855544A (zh) | 2006-11-01 |
KR20060111859A (ko) | 2006-10-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1855544B (zh) | 具有屏蔽电极的半导体器件及其方法 | |
CN1855543B (zh) | 改进性能的功率半导体器件及其方法 | |
US6365932B1 (en) | Power MOS transistor | |
CN101083284B (zh) | 具有槽电荷补偿区的半导体器件及方法 | |
US8722477B2 (en) | Cascoded high voltage junction field effect transistor | |
TWI804649B (zh) | 絕緣閘極半導體器件及用於製造絕緣閘極半導體器件的區域的方法 | |
US7417296B2 (en) | Dielectric isolation type semiconductor device | |
CN105280714A (zh) | 具有屏蔽电极结构的绝缘栅半导体装置和方法 | |
CN101043053B (zh) | 具有改善性能的功率半导体器件和方法 | |
CN100573910C (zh) | 半导体器件及其制造方法 | |
CN101142687A (zh) | 具有改进性能的半导体器件及方法 | |
US10038082B2 (en) | Cascoded high voltage junction field effect transistor | |
CN106601731B (zh) | 带有esd保护结构的半导体结构及其制作方法 | |
CN103094324B (zh) | 沟槽型绝缘栅双极型晶体管及其制备方法 | |
US8115273B2 (en) | Deep trench isolation structures in integrated semiconductor devices | |
JPH043115B2 (zh) | ||
CN103489916A (zh) | 阶梯栅氧化层有源漂移区结构的n型ldmos及其制作方法 | |
CN104465764A (zh) | 半导体元件及制造半导体元件的方法 | |
US6104060A (en) | Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate | |
CN101165863A (zh) | 具有深槽电荷补偿区的半导体器件及方法 | |
JPH0332234B2 (zh) | ||
US20160322484A1 (en) | Bidirectional Bipolar Transistor Structure with Field-Limiting Rings Formed by the Emitter Diffusion | |
US5563437A (en) | Semiconductor device having a large sense voltage | |
JP2002141425A (ja) | フラッシュ・メモリセル性能を改良するための側壁プロセス | |
CN115425079A (zh) | 一种沟槽型双层栅功率器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1097098 Country of ref document: HK |
|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: GR Ref document number: 1097098 Country of ref document: HK |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100512 Termination date: 20210424 |