CN1855529A - 具有场稳定膜的半导体器件和方法 - Google Patents

具有场稳定膜的半导体器件和方法 Download PDF

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CN1855529A
CN1855529A CNA2006100732109A CN200610073210A CN1855529A CN 1855529 A CN1855529 A CN 1855529A CN A2006100732109 A CNA2006100732109 A CN A2006100732109A CN 200610073210 A CN200610073210 A CN 200610073210A CN 1855529 A CN1855529 A CN 1855529A
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CN1855529B (zh
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杜尚晖
石黑武
藏前文香
近江隆二
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Semiconductor Components Industries LLC
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Abstract

在一个实施方案中，用第一介质层和包含形成在第一介质层上的可流动的玻璃的电荷稳定层，制作了高压半导体器件。

Description

具有场稳定膜的半导体器件和方法
技术领域
本发明一般涉及到半导体器件，更确切地说是涉及到高电压开关器件及其制造方法。
背景技术
高压功率半导体器件被用于许多功率转换和控制应用中。这种器件包括二极管、双极晶体管、绝缘栅双极晶体管(IGBT)、闸流管、以及金属氧化物场效应晶体管(MOSFET)。初看起来，半导体高压功率器件物理似乎与低压功率器件物理完全相同。然而，虽然器件工作的某些特点是相似的，但器件物理的许多方面在高压工作的条件下仍然有重要的不同。
通常，高压半导体器件(亦即能够承受超过200V或以上的击穿电压的器件)必须能够在关断状态下支持高的闭锁电压，并能够在开通状态下以最小的功耗在大电流电平下导电(亦即开态电阻低)。但高的闭锁电压和低的开态电阻提出了二个相互冲突的设计参数，对高压器件的设计者和制造者提出了挑战。
其中，二极管结型器件的反向击穿电压由p-和n-区域的电阻率以及掺杂分布确定。高压器件要求制造者采用高电阻率原材料和/或区域。举例来说，与典型集成电路器件的0.15-0.20欧姆厘米的电阻率数值相比，高压器件的电阻率数值普遍大于1-3欧姆厘米。更高的电阻率结合正在发展的设计限制，提出了一些挑战，使得难以生产长时间稳定而可靠的高电压功率器件。这些设计限制包括更小的器件尺寸、多层金属化、以及与其它灵敏器件(例如集成电路器件)的集成。
此外已经发现，当被用于较高电压器件时，目前用于较低电压器件的方法和结构是不可靠的。例如，这种方法和结构导致击穿电压随时间而退化的器件、不希望有的场反转效应、以及寄生泄漏效应。
因此，需要改进了的功率半导体器件结构及其制造方法来处理上述问题等。
发明内容
根据本发明的一方面，提供一种高压半导体器件，它包括：包括第一导电类型的半导体材料本体；形成在半导体材料本体中的第一掺杂区，其中，第一掺杂区包括第二导电类型，且其中，第一掺杂区与半导体材料本体形成高压结；形成在半导体材料本体上的第一介质层；以及形成在第一介质层上的电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的可流动的玻璃材料。
根据本发明的另一方面，提供一种高压半导体器件，包括：电阻率大于大约1欧姆厘米的第一导电类型的半导体材料区；形成在半导体材料区中的第二导电类型的第一掺杂区；形成在半导体材料区中的第一导电类型的本体区；形成在本体区中的源区；形成在第一掺杂区中的漏接触；形成在本体区附近的栅结构；形成在部分半导体材料区上的第一介质层；以及形成在第一介质层上的电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的硅玻璃材料。
根据本发明的另一方面，提供一种制作高压半导体器件的方法，包括下列步骤：提供具有第一导电类型的半导体材料本体；在半导体材料本体中形成第一掺杂区，其中，第一掺杂区包括第二导电类型，且其中，第一掺杂区与半导体材料本体形成高压结；在半导体材料本体上形成第一介质层；以及在第一介质层上形成电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的可流动的玻璃材料。
附图说明
图1示出了根据本发明一个实施方案的高压半导体结构的高度放大剖面图；
图2示出了根据本发明另一个实施方案的高压半导体结构的高度放大剖面图；
图3示出了根据本发明另一个实施方案的高压半导体结构的高度放大剖面图；
图4示出了根据本发明另一个实施方案的高压半导体结构的高度放大剖面图；
具体实施方式
为了易于理解，各附图中的元件无须按比例绘制，且相似的参考号被用于所有附图的恰当地方。为了附图清晰起见，器件结构的掺杂区被示为通常具有直线边沿和角度精确的边角。但本技术领域的熟练人员理解的是，由于掺杂剂的扩散和激活，掺杂区的边沿通常不是直线，且边角也不是精确的角度而典型为圆角。此外，为了简化描述，省略了对众所周知的步骤和元件的描述。虽然这些器件在此处被解释为某些N沟道器件，但本技术领域的一般熟练人员可以理解的是，根据本发明，P沟道器件和互补器件也是可以的。
图1示出了根据本发明一个实施方案的功率半导体器件、高压结构、或高压功率器件10的高度放大局部剖面图。举例来说，器件10是一种高压二极管器件，或者是双极晶体管、IGBT、闸流管的终端部分或其它部分，或其中存在高击穿电场的MOSFET器件。器件10包含半导体材料本体、区域、或衬底11。半导体材料本体11或其各个部分包含硅或IV-IV族半导体材料(例如SiGe、SiC、SiGeC等)，III-V族半导体材料或它们的组合。举例来说，区域11的电阻率对于200V器件约为1-10欧姆厘米，对于500V器件约为10-20欧姆厘米，而对于750V器件约为20-80欧姆厘米。
器件10还包括第一掺杂区18，掺杂区18的导电类型与区域11的相反，以便形成高压结21。举例来说，第一掺杂区18的峰值浓度约为每立方厘米1.0×1015原子到每立方厘米1.0×1018原子，而结深度约为3-30微米。在一个可选实施方案中，导电类型相同于第一掺杂区18的第二掺杂区19，被形成在第一掺杂区中，以便将表面浓度提高到高于大约每立方厘米1.0×1020原子，以便得到改进了的欧姆接触。在另一实施方案中，第二掺杂区19包含相反的导电类型，以便形成发射极、源、或阴极区。
可选的环区或电场扩展区24被形成在区域11部分中，且包含相同于第一掺杂区18的导电类型。环区24的数目和间距依赖于器件10的击穿电压，并用众所周知的技术来确定这些参数。第三掺杂或沟道停止区27被形成在器件10的外沿部分处。在一个实施方案中，第三掺杂区27包含相同于区域11的导电类型。
第一介质层31被形成在区域11的主表面12上，且包含例如热淀积的或热生长的二氧化硅。举例来说，第一介质层31的厚度约为0.5-2.0微米。第一介质层31在包含热淀积的或热生长的介质时的一个问题在于，当器件10处于高电压反向偏置条件下时，在器件10表面处得到的电场沿第一介质层31产生电荷不平衡或偶极子。本发明人发现，此偶极子效应在高压应力测试或老化过程中引起高压器件10的闭锁电压能力退化。此效应由于半导体区域11的低掺杂剂浓度即高电阻率以及高压偏置条件而被放大，在典型的低电压和/或IC器件中未曾发现过这种效应。
根据本发明，电荷稳定、电荷中和层、或玻璃稳定层33，被形成邻近(直接或间接)在第一介质层31上或上方。在一个典型的实施方案中，电荷稳定层33包含介电常数低于第一介质层31的材料。例如，电荷稳定层33包含硅玻璃材料，此材料包含的SiH含量或浓度大于第一介质层31中的SiH含量或浓度。在一个实施方案中，电荷补偿层33的折射率小于大约1.4。在另一实施方案中，电荷补偿层33的折射率约为1.36-1.38。举例来说，电荷稳定层33包含具有O-Si-O格子的硅玻璃层，此硅玻璃层的O-Si-O格子比常规热淀积或热生长的氧化硅更呈片段或笼形(caged)，常规的氧化硅更呈网络形。在另一例子中，电荷稳定层33包含比常规热淀积或生长的氧化硅更多孔的硅玻璃材料。在一个实施方案中，电荷补偿层33包含诸如硅氧烷、硅酸盐、或氢倍半硅氧烷(HSQ)旋涂玻璃(SOG)之类的液体或可流动的玻璃材料。本发明人发现，当器件10被暴露于高压反向偏置条件时，电荷补偿层33用来中和或降低偶极子效应，或扫去第一介质层31与主表面12或其各部分的界面处的表面电荷。本发明人发现，这显著地改善了器件10的击穿电压稳定性。在一个实施方案中，电荷补偿层33延伸第一介质层31的长度或横向尺寸或更多。在本发明中，电荷稳定层33不由氮化硅或半绝缘多晶硅(SIPOS)组成。
在制作器件10的方法中，当电荷补偿层33包含液体或可流动的SOG时，用分散和旋涂装置，层33被淀积或旋涂到器件10上。在将层33分散之后，首先在低温下对其进行烘焙(例如在空气中于150-350℃下烘焙1-15分钟)，然后在较高的温度下进行烘焙(例如在惰性气体中于400-500℃下烘焙30-60分钟)。存在于液体SOG中的溶剂首先被驱去，且水从膜中被放出。在典型的实施方案中，层33的最终厚度约为0.2-1.0微米。在一个实施方案中，第二介质层41被形成在电荷稳定层33上，且包含例如氮化硅或低温淀积的氧化物。举例来说，第二介质层41的厚度约为0.05-0.5微米。
器件10还包括耦合到第二掺杂区19的第一导电层36和耦合到第三掺杂区27的第二导电层37。虽然未示出，但额外的导电层可以被耦合到半导体材料11本体的下表面。导电层36和37包含例如铝、铝合金、钛/镍/银、铬/镍/金等。在一个可选实施方案中，第三导电层39被形成在第一介质层31上以及环区24上方，以便提供进一步的场成形能力。第三导电层包含例如掺杂的多晶硅或金属等。
图2示出了根据本发明另一实施方案的功率半导体器件、高压结构、或高压功率器件100的高度放大局部剖面图。举例来说，器件100是一种高压二极管器件，或者是双极晶体管、IGBT、闸流管的终端部分或其它部分，或其中存在高击穿电场的MOSFET器件。除了电荷稳定层33被淀积成第一和第二介质层31和41上的最终层之外，器件100相似于器件10。器件100还包括可选的外钝化层43，此钝化层43包含例如氮化硅或热淀积的氧化物。举例来说，层43的厚度约为0.05-1.0微米。此外，器件100被示为没有环区24或第三导电层39，但这些特点被可选地包括在器件100中。
图3示出了根据本发明另一实施方案的功率半导体器件、高压结构、或高压功率器件200的高度放大局部剖面图。在本实施方案中，器件200包含高压(亦即高于200V)横向DMOS或LDMOS器件。器件200包括半导体材料的本体或区域160，它包含例如第一导电类型的半导体衬底或区域。举例来说，当器件200是n沟道器件时，半导体区域160包含p型区，且电阻率大于大约1.0欧姆厘米。如先前所述，根据所希望的高压击穿特性来选择电阻率。
器件200还包括形成在部分区域160中并从主表面201延伸进入到区域160的第一阱区、漂移区、延伸的漏区、或掺杂区180。举例来说，第一阱区180包含n型区，且峰值掺杂浓度约为每立方厘米1.0×1015原子，而深度约为4-10微米。
在一个可选实施方案中，一个或多个p型层或p顶层181被形成在阱区180中，并从主表面201延伸，以便提供降低了表面场的区域。在器件200处于闭锁状态或关断状态时，使p型层181能够得到向下的耗尽，这使器件200能够保持较高的闭锁电压。重掺杂的n型接触或漏区190被形成在第一阱区180中。
器件200还包括形成在另一部分区域160中并从主表面201延伸的第二阱区、漂移区、延伸的漏区、或掺杂区182。举例来说，第二阱区182包含n型区，且峰值掺杂浓度约低于第一阱区180的峰值掺杂浓度。而且，在一个实施方案中，第二阱区182延伸进入到区域160中，进入的深度小于第一阱区180的深度。第一阱区180和第二阱区182与区域160形成一个pn结210，当器件200处于关断状态或在反向偏置条件下，这是器件200的主要闭锁结。
p型高压区、本体区、或扩散区240被形成在邻近阱区180和182的另一部分区域160中。p型区240的掺杂浓度高于区域160。n型源区241和p型接触区242被形成在区域240中。
第一介质层310和311被形成在器件200上，以便提供局部的钝化区。第一介质层310和311包含例如用常规热淀积或生长技术形成的半导体的局部氧化(LOCOS)区或场氧化硅区。举例来说，第一介质层310和311的厚度约为0.5-2.0微米。如图3所示，第一介质层311至少为部分阱区180提供了表面隔离。
栅结构440被形成在主表面201上，且包括薄的栅介质层441和栅电极层442。在典型实施方案中，栅介质层441包含氧化硅，且厚度约为0.02-0.1微米。举例来说，栅电极层442包含诸如掺杂的多晶硅之类的掺杂的多晶半导体材料。
第二介质层410被形成在器件200上，并被图形化，以便提供对于第一接触区或层361、362、363的一系列窗口。举例来说，第二介质层410包含诸如BPSG和PSG之类的掺杂的热淀积氧化硅。第二介质层410的厚度约为0.5-1.5微米，并用常规的加工技术来形成。
第一接触区361提供了到源区241和p型接触区242的电接触或路由；第一接触区362提供了到栅电极层442的电接触或路由；而第一接触区363提供了到漏区190的电接触或路由。举例来说，第一接触区或层361、362、363包含钛、钨、硅化钛、硅化钨、铝、铝合金(例如AlSi和AlCu)、它们的组合等。第三介质层411被形成在第一接触区361-363上，且包含例如氮化硅或热淀积的氧化硅。在一个实施方案中，第三介质层411包含低温氧化物，厚度约为0.2-0.5微米，且用常规的加工技术来形成。
根据本发明，电荷稳定层、电荷中和层、或玻璃稳定层330被形成在主表面201上，以便在器件200的结210处于闭锁模式、反向偏置条件、或关断状态时稳定形成在阱区180附近的表面电荷。在一个实施方案中，电荷稳定层330至少延伸在第一介质层311的范围或边沿上。在另一实施方案中，如图3所示，除了形成用来连接到下一层金属化的通道或窗口(未示出)的区域之外，电荷稳定层330连续地延伸跨越主表面。在典型实施方案中，电荷稳定层330包含介电常数小于第一介质层311的材料。例如，电荷稳定层330包含硅玻璃材料，此硅玻璃材料包含的SiH含量或浓度大于第一介质层311的SiH含量或浓度。在一个实施方案中，电荷补偿层330的折射率小于大约1.4。在另一实施方案中，电荷补偿层330的折射率约为1.36-1.38。举例来说，电荷稳定层330包含具有O-Si-O格子的硅玻璃层，此硅玻璃层的O-Si-O格子比常规热淀积或热生长的氧化硅更呈片断或笼形，常规的氧化硅更呈网络形。在另一例子中，电荷稳定层330包含比常规热淀积或生长的氧化硅更多孔的硅玻璃材料。在一个实施方案中，电荷稳定层330包含诸如硅氧烷、硅酸盐、或氢倍半硅氧烷(HSQ)旋涂玻璃(SOG)之类的液体或可流动的玻璃材料。举例来说，电荷稳定层330的厚度约为0.3-0.6微米。在本发明中，电荷稳定层330不由氮化硅或半绝缘多晶硅(SIPOS)组成。
第四介质层412被形成在电荷稳定层330上。在一个实施方案中，在形成第四介质层412之前，形成通道或窗口(未示出)，以便第四介质层412也给通道的壁加衬里。第四介质层412包含例如低温氧化硅层，且厚度约为0.3-0.7微米。接着，第二接触区461、462、463被形成在主表面201上方，从而提供到第一接触区361、362、362的接触或路由。举例来说，第二接触区461-463包含钛、钨、硅化钛、硅化钨、铝、铝合金(例如AlSi和AlCu)、它们的组合等。在一个实施方案中，最终的钝化层413被形成在主表面201上方，以便提供除了要形成最终接触的区域之外的第二接触区461-463的隔离和/或保护。
本发明的发明人发现，电荷补偿层330用来中和或降低偶极子效应，或在高压反向偏置条件下稳定存在于第一介质层311内的表面电荷效应，从而改善器件200的击穿电压稳定性。例如，当为700V设计的器件200与采用常规热淀积的氧化硅(例如原硅酸四乙酯(TEOS)氧化物)层代替电荷稳定层330的常规700V LDMOS器件比较时，本发明人在高压应力测试中始料未及地意外发现了大约85％的击穿电压稳定性改善。
图4示出了根据本发明另一实施方案的功率半导体器件、高压结构、或高压功率器件300的高度放大剖面图。除了电荷稳定层、电荷中和层、或玻璃稳定层330被形成在第二接触区461-463上方之外，器件300相似于器件200。而且，在此实施方案中，ILD区415将第一接触区361-363分隔于第二接触区461-463，且包含例如诸如用TEOS淀积的氧化硅之类的热淀积氧化物的第一和第二层414和416。
如器件200那样，本发明人在高压应力测试中始料未及地意外发现，与用热掺杂的氧化物代替电荷稳定层330的常规700V LDMOS器件相比，器件300显示出大约85％的击穿电压稳定性改善。
考虑到所有上述情况，显然公开了一种新颖的器件及其制作方法。其中包括了一种高压功率半导体器件，此高压功率半导体器件具有在高压反向偏置条件下提高性能的电荷稳定层。
虽然参照其具体实施方案已经描述了本发明，但不是为了将本发明局限于所述的各个实施方案。例如，可以组合额外的钝化层或多个电荷稳定层。而且，可以组合诸如填充的沟槽区(例如用介质和/或导电材料填充)、各种导电类型的额外的浮置环、SIPOS场成形层、和/或金属化环之类的其它终端结构。本技术领域的熟练人员可以理解的是，可以作出各种修正和变化而不偏离本发明的构思。因此认为本发明包罗了所附权利要求范围内的所有这些变化和修正。

Claims (10)

1.一种高压半导体器件，包括：
包括第一导电类型的半导体材料本体；
形成在半导体材料本体中的第一掺杂区，其中，第一掺杂区包括第二导电类型，且其中，第一掺杂区与半导体材料本体形成高压结；
形成在半导体材料本体上的第一介质层；以及
形成在第一介质层上的电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的可流动的玻璃材料。
2.权利要求1的器件，其中，电荷稳定层包括旋涂玻璃。
3.权利要求2的器件，其中，电荷稳定层包括硅氧烷旋涂玻璃、硅酸盐旋涂玻璃、或氢倍半硅氧烷旋涂玻璃之一。
4.权利要求1的器件，还包括形成在电荷稳定层上的第二介质层。
5.权利要求1的器件，其中，第一掺杂区包括延伸的漏区，且其中，该器件还包括：
形成在延伸的漏区中的第二导电类型的漏接触；
形成在延伸的漏区附近的第一导电类型的本体区；
形成在本体区中的第二导电类型的源区；以及
形成在半导体材料本体上的栅结构。
6.权利要求1的器件，还包括形成在半导体材料本体上方的导电层，且其中，电荷补偿层被形成在至少部分导电层上。
7.一种高压半导体器件，包括：
电阻率大于大约1欧姆厘米的第一导电类型的半导体材料区；
形成在半导体材料区中的第二导电类型的第一掺杂区；
形成在半导体材料区中的第一导电类型的本体区；
形成在本体区中的源区；
形成在第一掺杂区中的漏接触；
形成在本体区附近的栅结构；
形成在部分半导体材料区上的第一介质层；以及
形成在第一介质层上的电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的硅玻璃材料。
8.权利要求7的器件，其中，电荷稳定层包含旋涂玻璃。
9.一种制作高压半导体器件的方法，包括下列步骤：
提供具有第一导电类型的半导体材料本体；
在半导体材料本体中形成第一掺杂区，其中，第一掺杂区包括第二导电类型，且其中，第一掺杂区与半导体材料本体形成高压结；
在半导体材料本体上形成第一介质层；以及
在第一介质层上形成电荷稳定层，其中，电荷稳定层包括折射率小于大约1.4的可流动的玻璃材料。
10.权利要求9的方法，其中，形成电荷稳定层的步骤形成包括旋涂硅玻璃的电荷稳定层。
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