CN1851859A

CN1851859A - Silicon chip process test method

Info

Publication number: CN1851859A
Application number: CN 200510126382
Authority: CN
Inventors: 唐果
Original assignee: Beijing North Microelectronics Co Ltd
Current assignee: Beijing North Microelectronics Co Ltd
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2006-10-25
Anticipated expiration: 2025-12-08
Also published as: CN100362623C

Abstract

This invention relates to a method for testing silicon chips including: designing the necessary test times based on the technology requirement, adhering related numbers of films uniformly distributed on the chip, unclosing a sheet of film for testing, unclosing a new film after a test is finished and moving the opened position to the last one to carry out the next time of test and the film is PI.

Description

A kind of silicon chip process test method

Technical field

The present invention relates to technique for processing silicon chip, particularly a kind of technique for processing silicon chip test method.

Background technology

At present, the silicon chip of 300mm is the main flow of semiconductor product industry, and domestic semiconductor industry just turns to the 300mm silicon chip from the 200mm silicon chip.Generation equipment generation technology, equipment manufacturers are responsible for technique research and development, and this is the potential rule of semiconductor industry.

Series of factors such as process results and coil design, chamber pressure, temperature, gas flow, gas componant proportioning, process time are closely related.In order to obtain desirable etching result, can consume a large amount of silicon chips in the technique research and development process, traditional test method is that each test consumes a slice time, i.e. monolithic single test, for the technology of a maturation of exploitation, required silicon chip is usually in hundreds and thousands of.Enter after the 300mm technology, the price of silicon chip rises significantly, if same research and development content of the test before carrying out, only consume on this at silicon chip, the technique research and development cost of 300mm also will be 2～3 times of 200mm technique research and development, and the absolute consumption of the units up to a million of silicon chip also makes R﹠D costs rather expensive.

Traditional engineer testing adopts monolithic single test mode, promptly whenever carries out the one-time process test, needs consumption a slice inferior.Such as, if carry out the inhomogeneity orthogonal test of etch rate of polysilicon main etching step, need to consider go up RF power, the ratio, at least 7 factors such as helium back of the body blow pressure power of total gas flow, chamber pressure, silicon chip inner ring and outer ring of RF power, HBr and Cl2 down, use L ₁₈3 ⁷Orthogonal test method, need 18 silicon chips just can finish test.

The subregion that someone adopts the small size silicon chip to be covered on the technology silicon chip to realize silicon chip uses, but in High Density Plasma Etching System, plasma sheath apart from silicon chip also with regard to 1 millimeter.If the thickness as the film of insulation barrier is too high, must change plasma distribution situation in the reative cell, this has greater difference with real state of arts.

Summary of the invention

The technical problem that solves

For the technique research and development initial stage, only need definite qualitatively condition that influences the engineer testing result, the test method of monolithic single makes silicon chip not be utilized, and for the research and development purpose, obviously is very uneconomic.Purpose of the present invention just provide a kind of can be with the carrying out of silicon chip process test method repeatedly.

Technical scheme

Silicon chip process test method of the present invention may further comprise the steps:

The test number (TN) that A requires the design needs to carry out according to engineer testing;

The test number (TN) that B carries out as required sticks the film of equally distributed respective numbers on silicon chip;

The C silicon chip is opened a slice film after keeping the unlimited district of a slice membrane area or pasted film when pad pasting, carries out engineer testing;

After test of D one-time process and detection finish, open new film, and open position is moved on to previous position, test next time.

Described film is folded in half into bilayer earlier before sticking silicon chip.

Described film is a polyimides.

The thickness of described film is 45～55um.

The equipment that described engineer testing is used is the etching polysilicon machine of 300mm silicon chip.

Beneficial effect

This method focuses on to be protected silicon chip surface; thereby increase triable number of times of silicon chip, promptly adopt monolithic test of many times mode, when satisfying the engineer testing needs; reduce the consumption of silicon chip in technique research and development to greatest extent, thereby greatly reduce the technique research and development cost.The complete available monolithic of 9 silicon chips 1 silicon chip repeatedly such as the monolithic single test replaces, and has promptly saved 89%.

Description of drawings

Fig. 1 is the silicon chip pad pasting mode schematic diagram of embodiment 1 to 3;

Among the figure: 1, the position of 9 pad pastings of 2,3,4,5,6,7,8,9 expressions.

Embodiment

Following examples are used to illustrate the present invention; but be not used for limiting the scope of the invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be limited by every claim.

Before carrying out engineer testing, clearly may influence the condition element of process results, require to design the test number (TN) that needs carry out according to engineer testing.Common method is the test number (TN) that need carry out by the orthogonal method design, also can carry out determining experiment number all over time experimental technique according to experimental factors.

The test number (TN) that carries out sticks the film of equally distributed respective numbers on silicon chip as required.

Silicon chip is opened a slice film after keeping the unlimited district of a slice membrane area or pasted film when pad pasting, carries out engineer testing.

After one-time process test and detection finish, open new film, and open position is moved on to previous position, test next time.

Wherein, be attached on the silicon chip, pasting again after the film doubling for fear of the colloid of film.

Used film is Polyimide, chemistry polyimides by name.It is a kind of high temperature resistance, wearing and tearing and corrosive synthetic polymerized resin with good insulation performance.Used film, its thickness is about 45～55um.The used equipment of engineer testing is the etching polysilicon machine of 300mm silicon chip.

Embodiment 1

Pad pasting whether etch rate contrast test:

Select for use main carving technology condition to etching polysilicon, its concrete technology is as follows: going up RF power is 3000W, and following RF power is 80W, and chamber pressure is 15mT, and total gas flow rate is 230sccm, wherein Cl ₂Be 30sccm, HBr is 170sccm, or He/O ₂Gaseous mixture 30sccm, the two volume ratio is 7: 3.Adopt earlier the pad pasting silicon chip to carry out duplicate test 9 times, the pad pasting mode is seen Fig. 1, use in addition a slice not the silicon chip of pad pasting adopt above process conditions to compare.Result of the test such as following table:

Silicon chip	Pad pasting	1	Pad pasting 2	Pad pasting 3	Pad pasting 4	Pad pasting 5	Pad pasting 7	Pad pasting 8	Pad pasting 9	Pad pasting not
Silicon chip	Pad pasting	1	Pad pasting 2	Pad pasting 3	Pad pasting 4	Pad pasting 5	Pad pasting 7	Pad pasting 8	Pad pasting 9	Pad pasting not	Etch rate	1565 A/min	1659 A/min	1589 A/min	1500 A/min	1519 A/min	1499 A/min	1596 A/min	1650 A/min	1592 A/min

Can see that same process in the repeatability of the etch rate in different zones not better, and is and very approaching with the situation of pad pasting, show that the method can well reduce the etch rate test.

Embodiment 2

For groping different technology conditions respectively to the etch rate of silicon dioxide and polysilicon, can find etch rate to select by test than the process conditions that are 1: 1, need run through the step etch rate and select than test.In running through etch step, getting upper electrode power respectively is 250W, 300W and 350W, and lower electrode power is 40W, 60W and 80W, and chamber pressure is 5mT, 10mT and 15mT, and C2F6 is 40sccm, 60sccm and 80sccm, and the process time is 2 minutes.The silicon dioxide etch rate test procedure that runs through step is as follows:

A. the test number (TN) that adopts the orthogonal design method design to carry out: this test is 4 variablees, 3 levels, can adopt L ₉3 ⁴Testing program, need 9 tests altogether, the process conditions of 9 tests see Table 1.

B. on a titanium dioxide silicon chip, evenly paste 9 films, pad pasting mode such as Fig. 1.

C. open a slice film on the titanium dioxide silicon chip, carry out the etching test by the 1st test technology condition of table 1.

D. after one-time process test and detection finish, open new film, and open position is moved on to previous position, test next time, up to finishing 9 etchings tests by the process conditions of testing in the table 1 next time.

Use the same method and carry out the etching polysilicon speed trial, two comparison of test results see Table 1.

Table 1 Orthogonal Experiment and Design table

The test order	Process conditions				Result of the test
	Process conditions				Result of the test			Upper electrode power	Lower electrode power	Pressure	C2F6	The silicon dioxide etch rate	Etching polysilicon speed	Etch rate ratio
	123456789 is preferred	250W 300W 350W 250W 300W 350W 250W 300W 350W 300W	40W 40W 40W 60W 60W 60W 80W 80W 80W 80W	15mT 5mT 10mT 10mT 15mT 5mT 5mT 10mT 15mT 10mT	60sccm 40sccm 80sccm 40sccm 80sccm 60sccm 80sccm 60sccm 40sccm 60sccm	1100 935 1202 863 1280 1120 1320 800 986 800	801 1012 752 986 798 762 998 820 1290 820	Upper electrode power	Lower electrode power	Pressure	C2F6	The silicon dioxide etch rate	Etching polysilicon speed	Etch rate ratio	1.37 0.92 1.60 0.88 1.60 1.47 1.32 0.98 0.76 0.98

Compare with traditional monolithic single process test method, method of the present invention has been utilized silicon chip to greatest extent, makes the consumption of silicon chip be reduced to 1/8～1/6 of monolithic single test; Although the result who draws compares with the monolithic single of true technology, can not satisfy the quantitative analysis requirement, at the technique research and development initial stage, qualitative analysis can meet the demands.

The used polyimide film of method of the present invention is commonly used for the clad can or the overlay film of electrostatic chuck in semiconductor equipment.So, adopt this film can not cause extra pollution to reative cell.

When using method of the present invention, test silicon chip at every turn and all rotate equal angular,, guaranteed the comparativity of hardware condition so that new silicon chip part of opening wide is in same position all the time in reative cell.

Claims

1, a kind of silicon chip process test method is characterized in that, may further comprise the steps:

A. require to design the test number (TN) that needs carry out according to engineer testing;

B. the test number (TN) that carries out as required sticks the film of equally distributed respective numbers on silicon chip;

C. silicon chip is opened a slice film after keeping the unlimited district of a slice membrane area or pasted film when pad pasting, carries out engineer testing;

D. after one-time process test and detection finish, open new film, and open position is moved on to previous position, test next time.

2, silicon chip process test method as claimed in claim 1 is characterized in that, described film is folded in half into bilayer earlier before sticking silicon chip.

3, silicon chip process test method as claimed in claim 1 is characterized in that, described film is a polyimides.

4, silicon chip process test method as claimed in claim 1 is characterized in that, the thickness of described film is 45～55um.

5, silicon chip process test method as claimed in claim 1 is characterized in that, the equipment that described engineer testing is used is the etching polysilicon machine of 300mm silicon chip.