CN1826727A - 改进的离散lc滤波器的方法和设备 - Google Patents
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Abstract
本发明公开了一种离散电感-电容(LC)滤波器,其在至少两个电感器组之间选择以调谐LC滤波器。滤波器接收到输入信号,输入信号包括一个或多个频带。控制信号选择用于处理的频带。第一电感器组被选择对第一频带进行滤波,而第二电感器组被选择对第二频带进行滤波。开关电路将输入信号连接到第一电感器组或第二电感器组。如果第一频带被选择,则开关电路选择第一电感器组,而如果第二频带被选择,则开关电路选择第二电感器组。开关电路在电气上隔离输入信号的开关和第一与第二电感器组,以提高LC滤波器的Q因数。本文公开的电路和技术能减小使用MOS晶体管的电容组中的寄生电容。此外,本文还公开了基于输入信号频率调谐电感组上的耦合系数的电路和技术。
Description
技术领域
本发明针对离散滤波器领域,更具体地针对电容器和/或电感器组滤波器。
背景技术
电感器和电容器组可以被配置为实现多种不同离散滤波器。图1a示出了一个电感(L)组的实施例。对于该实施例,电感组包括五个电感器(110、108、106、104和102)。尽管电感组100包括五个电感器,但是可以使用任意数量的电感器,而不会脱离本发明的精神和范围。电感器的数量和数值是期望的滤波器的频率响应特性的函数。形成电感组100的电感器被并联设置。每个电感器通过如图1a所示的相应开关加到L组。典型地,开关可以用金属氧化物半导体(“MOS”)晶体管来实现。
图1b示出了电容组的一个实施例。对于该实例,电容组120包含有五个电容器(130、128、126、124和122)。可以选择不同数量的电容器和不同的电容值来实现不同的频率响应。同样,如图1b所示,电容器128、126、124和122是通相应开关被选择用于C组的。典型地,这些开关是用MOS晶体管实现的。
每个MOS开关晶体管在滤波器响应中引入电阻分量。这样,被选择在C组中的每个电容器增加串联阻抗。串联阻抗的增加,或并联阻抗的减小,使得Q因数减小,这又使滤波器组的性能降低。
因此,期望通过减小寄生电容和增加Q因数来改善LC滤波器的特性和性能。
发明内容
离散电感-电容(LC)滤波器在至少两个电感器组之间选择,以对一个或多个频带对LC滤波器进行调谐。滤波器接收用于处理的输入信号。输入信号包括一个或多个频带。控制信号选择用于处理的频带,包括至少一个电感器的第一电感器组被选择用于对第一频带进行滤波,也包括至少一个电感器的第二电感器组被选择用于对第二频带进行滤波。开关电路将输入信号连接到第一电感器组或第二电感器组。如果选择的是第一频带,则开关电路选择第一电感器组,而如果选择的是第二频带,则开关电路选择第二电感器组。开关电路在电气上隔离输入信号到第一和第二电感器组的转换,以提高LC滤波器的Q因数。
附图说明
图1a示出了电感(L)组的一个实施例;
图1b示出了电容组的一个实施例;
图2是表示用于实现LC滤波器的一个实施例的框图;
图3示出了放大器的输入级的一个实施例;
图4示出了在电感器组之间进行选择的放大器的输出级的一个实施例;
图5A示出了电气上连接电容器的一个实施例;
图5B示出了用于减小电容器组的寄生电容的一个实施例;
图6A示出了一个示例性的电容器组;
图6B示出了根据本发明的一个实施例配置的一个电感器组;
图7示出了示例性LC滤波器的频率响应;
图8示出了示例性的LC滤波器。
具体实施方式
图2是表示用于实现LC滤波器的一个实施例的框图。电路200包括两个信号通路:第一频带(例如,频带I)的信号通路,和第二频带(例如,频带II、III)的信号通路。在一个应用中,电路200包括电视调谐器的LC滤波器组。对于电视调谐器实施例,“频带I”的信号通路对50至285MHz频率范围内的输入信号进行滤波,而“频带II、III”的信号通路对285至880MHz频率范围内的输入信号进行滤波。
第一频带的信号通路由包括电感器206和208的电感组(即,变压器)组成。电感组(电感器206和208)从射频(“RF”)输入端202接收输入信号。电路200进一步包括,第一信号通路中的电容器组220。电容器组220包括选择性地连接到第一信号通路的多个电容器。电容器组220中的电容器与电感器206和208的选择性连接包括第一可调谐LC滤波器。电容器组220的输出是对(例如,自动增益控制的)放大器226的输入。
RF输入端202通过电容器204,也连接到第二组输入频率(例如,频带II、III)的第二信号通路。第二频带的第二信号通路包括电感器组和电容器组222,电感器组由电感器210和212组成。电容器组222包括多个电容器,它们被选择性地连接以在第二信号通路中对信号进行滤波。电容器组220的电容器和电感器210和212包括第二信号通路的第一可调谐LC滤波器。电容器组220的输出是对AGC放大器226的输入。
AGC放大器226选择性地将第一信号通路或第二信号通路连接到放大器226的输出端。例如,在电视调谐器实施例中,如果电视调谐器被设置为调谐频带I中的信道,则AGC放大器226选择第一信号通路。可替代地,如果电视调谐器被设置为调谐频带II、III中的信道,则AGC放大器226选择第二信号通路。下面结合对图3和4的讨论,更完整地描述AGC放大器226的一个实施例。
对于第一信号通路,AGC放大器226的输出端被连接到电容器组228。电容器组228的输出是对电容器组的输入。电感器组的输出又是对电容器组240的输入。对于该实施例,电感器组包括电感器234和236,和可调谐电容器230和232。与电容器组220类似,电容器组228和240的电容器被选择用来调谐LC滤波器。第一信号通路的输出是对缓冲器254的输入。
对于第二信号通路,AGC放大器226的输出端被连接到电容器组242。与第一信号通路类似,电容器组242的输出是对电感器组(即,电感器248、250和可调谐电容器230和246)的输入。电感器组的输出被输入到电容器组252。电容器组228和240的电容器被选择用来调谐或编制LC滤波器。第二信号通路的输出也是对放大器254的输入。
对于图2的实施例,电感器不包括与电感器串联的用于选择性地向LC滤波器加入电感的开关(例如,MOS晶体管)。相反,输入信号(即,用于处理的信号)被转换到信号通路(例如,图2实施例的第一和第二信号通路)之间的放大器中。在电感器组中进行串联电阻的消除,会得到LC滤波器的更好的Q因数。在第一和第二信号通路之间转换的放大器,隔离来自MOS晶体管的电阻。尽管图2的实施例隔离了输入和输出晶体管级的开关,但是可以使用任何用来隔离电开关的串联电阻与电感器配置,而不会脱离本发明的精神和范围。
图2的LC滤波器结构使线圈数达到最小。第一和第二信号通路适合于覆盖很宽的输入频率范围。例如,在图2的实施例中,第一和第二信号通路都只使用两个线圈。该结构可应用于处理UHF/VHF电视信号频带。
图3和4分别示出了放大器的输入和输出级的一个实施例。放大器在信号通路之间转换,以有效地选择输入信号的电感器组。通常,放大器接收来自第一和第二信号通路的信号,和控制信号(Band或Band′)作为输入。对于第一信号通路(例如,频带I的信号通路),晶体管328和332,当被选择时,驱动该晶体管级的输出。如果第二信号通路被选择(例如,频带II、III的信号通路),则晶体管318和320驱动该晶体管级的输出。第一信号通路的差分输入信号通路包括,电容器326和330,以及电容器318。第二信号通路接收输入到电容器314和316的差分信号。
控制信号,Band,控制第一信号通路的开关304的开关,并控制第二信号通路中开关338和340的开关。控制信号,Band′,具有与控制信号Band相反的值。控制信号Band′控制第一信号通路的开关302的开关,并控制第二信号通路中的开关322和324的开关。在一个实施例中,开关(302、304、322、324、338和340)包括金属氧化物半导体(MOS)晶体管。在操作中,为了选择第一信号通路(例如,频带I),Band被设置为低逻辑电平,而Band′被设置为高逻辑电平。在这些控制信号下,开关302被接通,而开关338和340被关断。开关302的起动使输出晶体管(328和332)导通。因此,输入信号通过晶体管328和332被传导。同样,Band上的低逻辑电平信号关断开关304,而Band′上的高逻辑电平接通开关322和324。开关322和324在闭合时,使得晶体管318和320的基极接地,并且对第二信号通路的输入信号不被传递到输入晶体管级(300)的输出端。
相反,当Band被设置为高逻辑电平而Band′被设置为低逻辑电平时,开关302打开,开关338和340闭合。在这些控制信号下,晶体管332和328的基极上的电压电平被接地,这样,就关断了晶体管328和332。因此,来自第一信号通路的输入信号不被传送到输入晶体管级(300)的输出端。同样,Band上的高逻辑电平和Band′上的低逻辑电平,使开关304闭合,并使开关332和324打开。开关304的起动使得输出晶体管,318和320,通过电阻器308和306的上拉而导通。因此,对第二信号通路的输入信号被传递到输入晶体管级(300)的输出端。该晶体管级的每个输出线路包括电流缓冲器,在图3上示为电流源334和336。
图4示出了在电感器组之间进行选择的放大器的输出级的一个实施例。放大器隔离晶体管的开关,并从而隔离晶体管对电感器组的串联电阻。在一个实施例中,放大器的输出级包括跨导(gm)放大器。对于该实施例,将电压变换成电流的跨导放大器,包括晶体管410、412、414、416、418和420,以及可变电阻器422和426和电流源428。为选择第一信号通路(例如,频带I),Band控制信号被设置为低逻辑电平,而Band′控制信号被设置为高逻辑电平。高逻辑电平Band′控制信号接通晶体管404以将晶体管410和412的基极置于高逻辑电平。因此,晶体管410和420驱动频带I或第一信号通路的输出。同样,Band′上的高逻辑电平使开关406闭合,使晶体管412和418的基极接地。因此,晶体管412和418被关断,并且输入不传递到第二信号通路(频带II、III)。
可替代地,为选择第二信号通路(频带II、III),Band控制信号被设置为高逻辑电平,而Band′控制信号被设置为低逻辑电平。高逻辑电平Band′控制信号接通晶体管404以将晶体管410和412的基极置于高逻辑电平。因此,晶体管412和418驱动第二信号通路(频带II、III)的输出。同样,Band′上的低逻辑电平使开关408闭合,使晶体管410和420的基极接地并关断晶体管(即,输入不传递到第一信号通路(频带I)到输出端)。
图5A示出了电气上连接电容器的一个实施例。通常,一个或多个电容器选择性地连接多个电容器,以形成可配置的电容器组。对于图5A的实例电路500,电容器502和506通过开关504连接。在一个实施例中,开关504包括金属氧化物半导体(MOS)晶体管。控制信号(CT)启动开关504,以在电气上连接电容器502和506。
图5B示出了用于减小寄生电容的电容器组的一个实施例。电容器组的实例包括由MOS晶体管(例如,NMOS)510选择性地连接的电容器508和512。为使寄生电容达到最小,图5B的电路包括晶体管540和550。控制信号(CT)用于选择电容器(508和512)来配置电容器组。控制信号(CT)被输入到晶体管540和550的栅极,以及通过电阻器520输入到晶体管510的栅极。晶体管540在接通时,通过电阻器514将节点560接地。如图5B所示,节点560位于连接晶体管510和电容器508的点上。同样,晶体管550在被CT启动时,通过晶体管530将节点570接地。尽管如图5B所示的电路可以用于选择性地连接两个电容器,但是该电路也可以同样选择性地连接任何数量的电容器,而不会脱离本发明的精神和范围。
在操作中,为连接电容器508和512,CT被设置成高逻辑电平。CT上的高逻辑电平接通晶体管510,从而连接电容器508和512。同样,CT上的高逻辑电平接通晶体管540并关断晶体管550。因此,晶体管540通过将经由晶体管514和530的电压向接地端下拉来降低节点560和570上的电压。在这种状态下(即,晶体管510被导通),节点560和570上的电压适当地对晶体管进行偏置。为分离电容器508和512,CT信号被设置成低逻辑电平。因此,晶体管540和510被关断,而晶体管550被接通。起动的晶体管550基于电阻器514和530和晶体管550上的偏压,使节点560和570上的电压增加。同样,CT上的低逻辑电平使晶体管510的栅极上的电压接地。晶体管510的栅极到源极电压的增加,源极(即,节点570)上电压和栅极上电压的结果,减小了晶体管510的栅极-源极结电容。类似地,晶体管510的栅极到漏极电压的增加,漏极(即,节点560)上电压和栅极上电压的结果,减小了晶体管510的漏极-栅极结电容。这样,该电路使MOS晶体管上从漏极到栅极和栅极到源极的结所产生的寄生电容达到最小。
在一个实施例中,电感组的滤波器特性得到改善。具体地,电感器组的带通特性通过基于期望的滤波器特性来调谐跨接电感器的电容而得到改善(例如,基于接收机的调谐频率选择电容以调节滤波器)。图6A示出了示例性的电感器组。如图6A的电路600所示,电感器610和620是并联配置的。电感器组600的响应是部分地基于电感器610和620之间的互耦系数。互耦系数如图6A中由带箭头的线和符号M所示。
图6B示出了根据本发明的一个实施例配置的电感器组。对于该实施例,电感器组包括电感器640和650。另外,电感器组630包括可变电容器660。可变电容器660是可调谐的,使得引入的电容可以变化。可变电容器660可以包括能够产生可变电容的任何种类的装置。
通常,电感器组(例如,变压器)的耦合系数是通过在电感之间引入电容(例如,图6B的电路630中的可变电容器660)来控制的。该电容的选择基于LC滤波器的调谐频率。相反,图6A的耦合电感器组600基于电感器的互耦系数。通过选择电容来调谐耦合系数,可以得到跨越可变LC滤波器特性的恒定的带宽(即,中心频率)。
图7示出了示例性LC滤波器的频率响应。为了命名的目的,带宽响应的特征在于中心频率fc、fc1和fc2。图8示出了示例性的LC滤波器。下面各项用于定义LC滤波器中的不同关系:
BW——带宽
kc——电容耦合
k1——电感耦合
M——互感
中心频率,fc,可以根据该表达式定义:
频率fc1和fc2之间的关系是基于响应的带宽,这样:
fc1=BW+fc2
电容耦合系数可以表示为:
电感耦合系数可以表示为:
其中,“C”和“L”是图7中所示的电容和电感。总耦合系数可以表示为电容和电感耦合之和:
k=kc+k1
总耦合系数可以表示为fc1和fc2频率的函数:
因此,LC滤波器的频带响应的中心频率范围(即,fc1到fc2)是部分地基于电容耦合系数的值可调谐的。
尽管以具体实施例的形式描述了本发明,但是应该理解,对于本领域熟练技术人员来说,可以进行不同修改和变化,而不会脱离本发明的精神和范围。
Claims (2)
1.一种可调谐离散LC滤波器,包括:
输入端,其接收用于处理的输入信号,所述输入信号包括多个频率;
控制输入端,其接收信息以选择至少一个频带用于处理;
第一电感器组,其用于对第一频带进行滤波;
第二电感器组,其用于对第二频带进行滤波;以及
开关电路,其将所述输入信号连接到所述第一电感器组和所述第二电感器组,以便分别在电气上隔离所述输入信号到所述第一电感器组和所述第二电感器组的所述开关,如果所述第一频带被选择,所述开关电路用于选择所述第一电感器组,而如果所述第二频带被选择,则用于选择所述第二电感器组。
2.一种用于调谐离散LC滤波器的方法,所述方法包括以下步骤:
接收用于处理的输入信号,所述输入信号包括多个频率;
接收信息以选择用于处理的至少一个频带;
如果选择第一频带,将所述输入信号转换到第一信号通路;
将第一电感器组连接到所述第一信号通路;
在电气上隔离所述输入信号的所述开关和所述第一电感器组;
在所述第一电感器组中对所述第一频带进行滤波;
如果选择第二频带,将所述输入信号转换到第二信号通路;
将第二电感器组连接到所述第二信号通路;
在电气上隔离所述输入信号的所述开关和所述第二电感器组;以及
在所述第二电感器组中对所述第二频带进行滤波。
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-
2004
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- 2004-07-16 CN CNA2004800207872A patent/CN1826727A/zh active Pending
- 2004-07-16 EP EP04778467A patent/EP1652298A2/en not_active Withdrawn
- 2004-07-16 JP JP2006520379A patent/JP2007537612A/ja active Pending
-
2005
- 2005-08-02 US US11/196,234 patent/US7088202B2/en not_active Expired - Fee Related
- 2005-10-07 US US11/246,475 patent/US7183880B2/en not_active Expired - Fee Related
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US9143172B2 (en) | 2009-06-03 | 2015-09-22 | Qualcomm Incorporated | Tunable matching circuits for power amplifiers |
US8963611B2 (en) | 2009-06-19 | 2015-02-24 | Qualcomm Incorporated | Power and impedance measurement circuits for a wireless communication device |
US8750810B2 (en) | 2009-07-24 | 2014-06-10 | Qualcomm Incorporated | Power amplifier with switched output matching for multi-mode operation |
CN102484464A (zh) * | 2009-08-19 | 2012-05-30 | 高通股份有限公司 | 数字可调级间匹配电路 |
US9000847B2 (en) | 2009-08-19 | 2015-04-07 | Qualcomm Incorporated | Digital tunable inter-stage matching circuit |
CN106208975A (zh) * | 2009-08-19 | 2016-12-07 | 高通股份有限公司 | 数字可调级间匹配电路 |
US9559639B2 (en) | 2009-08-19 | 2017-01-31 | Qualcomm Incorporated | Protection circuit for power amplifier |
CN111800162A (zh) * | 2019-04-04 | 2020-10-20 | 亚德诺半导体国际无限责任公司 | 具有可控谐振频率的射频开关 |
Also Published As
Publication number | Publication date |
---|---|
EP1652298A2 (en) | 2006-05-03 |
US7088202B2 (en) | 2006-08-08 |
JP2007537612A (ja) | 2007-12-20 |
US20050264376A1 (en) | 2005-12-01 |
US7183880B2 (en) | 2007-02-27 |
US20060028301A1 (en) | 2006-02-09 |
WO2005006832A3 (en) | 2005-06-16 |
US6940365B2 (en) | 2005-09-06 |
US20050012565A1 (en) | 2005-01-20 |
WO2005006832A2 (en) | 2005-01-27 |
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