CN1819156A - Method for fabricating capacitor of semiconductor memory device using amorphous carbon - Google Patents
Method for fabricating capacitor of semiconductor memory device using amorphous carbon Download PDFInfo
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- CN1819156A CN1819156A CNA2005101375000A CN200510137500A CN1819156A CN 1819156 A CN1819156 A CN 1819156A CN A2005101375000 A CNA2005101375000 A CN A2005101375000A CN 200510137500 A CN200510137500 A CN 200510137500A CN 1819156 A CN1819156 A CN 1819156A
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- protection barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming storage node contact plugs penetrating into the inter-layer insulation layer; forming a stack structure formed by stacking a first protective barrier layer and a sacrificial layer on the inter-layer insulation layer; performing an etching process to the first protective barrier layer and the sacrificial layer in a manner to have a trenches opening upper portions of the storage node contact plugs; forming storage nodes having a cylinder type inside of the trenches; forming a second protective barrier layer filling the inside of the storage nodes having the cylinder type; removing the sacrificial layer through performing a wet dip-out process; removing the first protective barrier layer and the second protective barrier layer; and sequentially forming a dielectric layer and a plate node on the storage nodes.
Description
Technical field
The present invention relates to a kind of technology of making semiconductor device; And more specifically, relate to a kind of method that is used to make the semiconductor storage unit that comprises the column type capacitor.
Background technology
Along with the minimum feature and the degree of integration increase of semiconductor device, wherein the area of capacitor formation reduces.Therefore, although wherein the area of capacitor formation reduces, the capacitor in the unit should be guaranteed the minimum aequum of each unit.Therefore, several different methods has been proposed in finite region, to form capacitor with high-capacitance.A kind of method of proposition is to form to have high dielectric-constant dielectric layer such as Ta
2O
5, Al
2O
3Or HfO
2, replace silicon dioxide layer and have the nitride layer of 7 dielectric constant (ε) with dielectric constant (ε) of 3.8.The another kind of method that proposes be by formation have three-dimensional type such as column type or matrix hearth electrode or by on the surface of hearth electrode by metastable polysilicon (MPS) particle 1.7 to the 2 times of areas that increase hearth electrode effectively of effective surface area increase of growing with hearth electrode.Also proposed a kind of by using metal level to form metal-insulator-metal (MIM) method of memory node and plate node.
Recently, for the capacitor that has more than the mim structure of the integrated dynamic random access memory in 128M position (DRAM), a kind of method that is used for titanium nitride (TiN) layer is applied to memory node has been proposed.
Figure 1A and 1B are viewgraph of cross-section, illustrate when the conventional semiconductors memory device with column type MIM capacitor is manufactured, form the conventional method of memory node by using TiN.
Shown in Figure 1A, in order to form semiconductor storage unit, interlayer insulating film 12 is formed on the substrate 11, and the technology that described substrate utilization is used to form word line, transistor and bit line is finished.Interlayer insulating film 12 is etched, forms the storage node contact hole of the predetermined portions that exposes substrate 11 thus.Then, a plurality of storage node contact plug 13 form by polysilicon is buried to be put in the storage node contact hole.
Then, etch stop layer 14 and sacrifice layer 15 are deposited on storage node contact plug 13 and the interlayer insulating film 12.At this moment, etch stop layer 14 can be formed and made sacrifice layer 15 stand to play the effect that etching stops during subsequently the etch process by nitride layer.And sacrifice layer 15 uses silicon oxide layer such as boron phosphorus silicate glass (BPSG) layer or unadulterated silicate glass (USG) layer to form, and wherein sacrifice layer 15 plays the effect that the three-dimensional structure that will form as memory node is provided.
Subsequently, mask process, the dry etching process that sacrifice layer 15 stands and another dry etching process that etch stop layer is stood are used, form a plurality of grooves 16 thus with three-dimensional structure.
Ti is deposited on a plurality of grooves 16 by chemical vapor deposition (CVD) method or physical vapor deposition (PVD) method.Then, carry out annealing process.Then, titanium silicide (TiSi) forms and the Ti that annealing process reacts not yet is removed.Thereby a plurality of barrier metal layers 17 form by above-mentioned step.
Imagination is deposited at the TiN that provides on the resulting structure of barrier metal layer 17 as memory node.Then, carry out the memory node isolation technology, thus at the groove 16 inner a plurality of TiN memory nodes 18 that form with column type.
As previously discussed, may be used for forming barrier metal layer 17, reduce the resistance on TiN memory node 18 and storage node contact plug 13 contacted surfaces by the making of lip-deep TiSi of utilizing the storage node contact plug 13 that forms with polysilicon.
Then, shown in Figure 1B, sacrifice layer 15 stands wet (wet dip-out) technology that drains out, and exposes the inner and outer wall of each the TiN memory node 18 with column type thus.At last, dielectric layer and plate node are formed on the TiN memory node 18 successively, finish the MIM capacitor with column type thus.
According to above-mentioned conventional method, carry out wet drain out technology during, the wet-chemical material trends towards being penetrated into the part of the interlayer insulating film 12 under the etch stop layer 14 in certain part of wafer, generates damage of damp bad 20 thus.Here, reference number 19 expression wet-chemical materials penetrates.Damage of damp bad 20 is typically called the infundibulate defective.And according to conventional method, the wet-chemical material penetrates along nitride layer and the TiN memory node 18 contacted surfaces as etch stop layer 14, and therefore can also form the infundibulate defective.
Owing to typically have column structure as the TiN of memory node 18, the wet-chemical material is in certain of wafer partially penetrates into crystal grain with storage node contact plug 13 contacted TiN memory nodes 18.Thereby above-mentioned infundibulate defective 20 forms.
Not only infundibulate defective 20 be cause refresh performance degradation, be the direct factor that IDD lost efficacy, and this also is proved to be to fail after generating infundibulate defective 20 corresponding to the chip of infundibulate defective 20.Especially, infundibulate defective 20 does not produce in the silicon-on-insulator silicon (Si) that uses polysilicon, but the problem of TiN itself.Therefore, infundibulate defective 20 is considered to key issue, and this is just inevitable as long as TiN is applied to the memory node of MIM capacitor of DRAM capacitor.
Summary of the invention
Therefore, an object of the present invention is to provide a kind of method that is used for producing the semiconductor devices, this method can prevent to cause the infundibulate defective, by described defective, the wet erosion that provides during draining out technology substructure that the wet-chemical material is adopted during carry out making the capacitor with column type memory node.
According to an aspect of the present invention, provide a kind of method that is used for producing the semiconductor devices, having comprised: on substrate, form interlayer insulating film; Formation is penetrated into a plurality of storage node contact plug in the interlayer insulating film; Formation is by piling up first protection barrier layer and the formed stacked structure of sacrifice layer on interlayer insulating film; Come etch process is carried out on the first protection barrier layer and sacrifice layer in the mode of the open groove in the top with the storage node contact plug of making; At the inner a plurality of memory nodes that form of groove with column type; Form the second protection barrier layer of filling memory node inside with column type; Wet drain out technology and remove sacrifice layer by carrying out; Remove the first protection barrier layer and the second protection barrier layer; And on memory node, form dielectric layer and plate node successively.
Description of drawings
Above and other objects of the present invention and feature will be about the following descriptions of the specific embodiment that combines with accompanying drawing and are become better understood, wherein:
Figure 1A and 1B are viewgraph of cross-section, illustrate the conventional method that is used for making the semiconductor device with column type metal-insulator-metal (MIM) capacitor; And
Fig. 2 A is a viewgraph of cross-section to 2G, illustrates the method that is used to make the semiconductor device with column type MIM capacitor according to a specific embodiment of the present invention.
Embodiment
Hereinafter, with the detailed description that provides with reference to the accompanying drawings some embodiment of the present invention.
Fig. 2 A is a viewgraph of cross-section to 2G, illustrates the method that is used to make the semiconductor device with column type MIM capacitor according to a specific embodiment of the present invention.
Shown in Fig. 2 A, interlayer insulating film 22 is formed on the substrate 21.Then, a plurality of storage node contact hole (not shown) that penetrate interlayer insulating film 22 form, and bury a plurality of storage node contact plug 23 formation that are put in the storage node contact hole then.Interlayer insulating film 22 has sandwich construction, because before interlayer insulating film 22 forms, provide the transistor that comprises word line and bit line technology.
A plurality of storage node contact plug 23 are formed, and the deposit spathic silicon layer is filled and carries out etch back process or chemico-mechanical polishing (CMP) technology up to storage node contact hole.
Then, buried on the interlayer insulating film of putting 22 in storage node contact plug 23, etch stop layer 24, the first protection barrier layer 25 and sacrifice layer 26 form successively.
Here, the etch stop layer 24 that plays the etching barrier effect during the dry etching process subsequently that sacrifice layer 26 is stood uses nitride layer to form.The first protection barrier layer 25 uses amorphous carbon to form, to prevent that the wet-chemical material is penetrated in the substructure during subsequently wet drains out technology.Sacrifice layer 26 forms to provide memory node to be conceived to be formed on wherein three-dimensional structure by using boron phosphorus silicate glass (BPSG) layer, unadulterated silicate glass (USG) layer, tetraethyl orthosilicate (TEOS) layer or high concentration plasma (HDP) layer.
As the amorphous carbon on the first protection barrier layer 25 with scope from about 5nm to about 1, the thickness of 000nm, scope from about 50 ℃ to about 600 ℃ temperature formation.
Shown in Fig. 2 B, sacrifice layer 26, the first wet erosion barrier layer 25 and 24 dry etching processs that stand separately of etch stop layer are carried out successively, form a plurality of grooves 27 on the top of open storage node contact plug 23 thus.
During forming groove 27, mask is formed on the sacrifice layer 26 by using photoresistance (photoresist) layer, and then by using this mask to come the sacrifice layer 26 and the first wet barrier layer 25 of corroding are carried out dry etching process.Then, mask is removed, and etch stop layer 24 optionally stands dry etching process then.Simultaneously, if the height of sacrifice layer 26 increases, then the hard mask that forms with polysilicon can be introduced during sacrifice layer 26 is carried out etch process, easily to carry out etch process.
Then, before forming the TiN memory node, a plurality of barrier metal layers 28 form.A plurality of barrier metal layers 28 are made by titanium silicide (TiSi).A plurality of barrier metal layers 28 as following formation.At first, titanium (Ti) is deposited on the whole surface that comprises groove 27 by physical vapor deposition (PVD) method or chemical vapor deposition (CVD) method.Then, annealing process is performed, and forms TiSi thus.To annealing process still the Ti of unreacted be removed.At last, form a plurality of barrier metal layers 28.Here, form by silicon (Si) as the polysilicon of storage node contact plug 23 is reacted with Ti as the TiSi of a plurality of barrier metal layers 28.TiSi does not form in the insulating material of storage node contact plug 23.
As mentioned above, if reduce the resistance on storage node contact plug 23 and the contacted surface of TiN memory node subsequently as the TiSi of barrier metal layer 28.
Shown in Fig. 2 C, the memory node isolation technology is used, thus at the groove 27 inner a plurality of TiN memory nodes 29 with column type that form.
As for the memory node isolation technology, on the surface of the sacrifice layer 26 that comprises groove 27, the TiN that is used as memory node is deposited.At this moment, TiN is deposited by CVD method, PVD method or ald (ALD) method.
Then, be filled up to groove 27, first photoresist layer 30 is formed on the TiN layer.
At this moment, first photoresist layer 30 plays the effect of passivation layer, with the inside of protection groove 27 during memory node isolation technology subsequently.Except first photoresist layer 30, oxide skin(coating) such as USG layer also can be used to passivation layer.
Therefore then, first photoresist layer 30 stands etch back process, and first photoresist layer 30 on the sacrifice layer 26 is removed.Therefore, 30 inside that are retained in groove 27 of first photoresist layer, and the TiN that therefore on the part of the reservation except groove 27, forms, be that the surface of sacrifice layer 26 is exposed.
As mentioned above, first photoresist layer 30 keeps by carrying out etch back process, and the TiN on the surface of the sacrifice layer except groove 27 26 stands etch back process or CMP technology then, forms a plurality of TiN memory nodes 29 thus.
As mentioned above, during the memory node isolation technology, when TiN removes by using etch back process or CMP process quilt, might or be attached to the inside of TiN memory node 29 through the impurity of etching particle such as grinding agent.Therefore, preferably have first photoresist layer 30 that good step covers and after the inside of filling groove 27, carry out the memory node isolation technology by use.
Shown in Fig. 2 D, first photoresist layer 30 that is retained on the top of TiN memory node 29 stands stripping technology.
Then, the second protection barrier layer 31 is deposited on the whole surface, up to being filled by removing the column type TiN memory node 29 that first photoresist layer 30 exposed.
At this moment, the second protection barrier layer 31 is introduced into preventing that the wet-chemical material is penetrated in the inside of column type TiN memory node 29 during carrying out subsequently wet to drain out technology, and therefore can utilize the amorphous carbon or second photoresist layer to form.
Shown in Fig. 2 E; if the second protection barrier layer 31 utilizes amorphous carbon to form; then the amorphous carbon as the second protection barrier layer 31 is optionally removed by descum technology, and therefore second protects barrier layer 31 to be left the type of the inside of filling TiN memory node 29.At this moment, the oxygen (O of plasmoid
2) gas be used to optionally remove second the protection barrier layer 31.
If utilize second photoresist layer to form the second protection barrier layer 31, shown in Fig. 2 E, empty exposure technology is carried out on the second protection barrier layer 31.Then, the second wet protective layer 31 that stands the sky exposure technology is developed.Thus, the second wet protective layer 31 is left the type of the inside of filling TiN memory node 29.Here, empty exposure technology is used and is immersed exposure technique.
At this moment; above-mentioned first photoresist layer 30 is identical photoresist layer with the second protection barrier layer 31; therefore and, be used for the photoresist layer of KrF, the photoresist layer that is used for ArF, the photoresist layer that is used for electron beam, the photoresist layer that is used for X ray, of photoresist layer who is used for the photoresist layer of extreme ultraviolet line (EUV) and is used for ion beam and can be used as first photoresist layer 30 and the second protection barrier layer 31 according to exposure light source.
After the second protection barrier layer 31 was optionally removed or stands aforesaid empty exposure and developing process, the top of the surface of sacrifice layer 26 and TiN memory node 29 was exposed.
Then, sacrifice layer 26 complete wet drain out technology and is removed by carrying out.At this moment, hydrogen fluoride (HF) solution is used to remove sacrifice layer 26.
Along with carry out complete wet drain out technology during employed wet-chemical material, be that HF solution removes sacrifice layer 26, HF solution can be penetrated into the TiN memory node 29 with the crystal grain structure that is weaker than described wet-chemical material.Yet according to the present invention, because the first wet barrier layer 25 of corroding is formed under the sacrifice layer 26 and the second protection barrier layer 31 is pre-formed inside at cylinder, HF solution can not penetrate TiN memory node 29.
In other words, the amorphous carbon that is used for first and second protection barrier layers 25 and 31 or second photoresist layers is to have optionally material about wet-chemical material such as HF solution, and therefore wetly is not subjected to the etching of HF solution during draining out technology carrying out.
Therefore, by introducing the first wet barrier layer 25 of corroding, might prevent that the wet-chemical material from penetrating along the TiN memory node 29 contacted surfaces on the outer wall of etch stop layer 24 and each column type TiN memory node 29.In addition, by on the inwall of column type TiN memory node 29, introducing second protective layer 31, might prevent that the wet-chemical material is penetrated into the basal surface of column type TiN memory node 29.
Shown in Fig. 2 F, remove the first wet barrier layer 25 of corroding that is exposed after the sacrifice layer 26 and be removed.At this moment, because the first wet erosion layer 25 is an amorphous carbon, amorphous carbon can be by using O
2Plasma removes.
If the second protection barrier layer 31 be an amorphous carbon, then the second protection barrier layer 31 can with remove the first wet erosion barrier layer 25 and side by side remove.And, if the second protection barrier layer 31 is second photoresist layer, then be introduced into as everyone knows to remove the O on the first protection barrier layer 25
2The plasma stripping photoresist layer.Therefore, during removing the first wet erosion barrier layer 25, the second protection barrier layer 31 can be removed simultaneously.
As mentioned above, according to the present invention, might obtain in addition the effect of technology simplicity, if because in case the second protection barrier layer 31 utilizes the amorphous carbon or second photoresist layer to form, then first wetly corrodes barrier layer 25 and the second protection barrier layer 31 can be removed.
As mentioned above, the inner and outer wall of each column type TiN memory node 29 drains out technology and exposes by wet.
Shown in Fig. 2 G, dielectric layer 32 and plate node 33 are formed on the TiN memory node 29A that is exposed successively, and the inner and outer wall of described memory node is exposed, and finishes the MIM capacitor with column type thus.At this moment, dielectric layer 32 comprises from by oxide/nitride/oxide (ONO), hafnium oxide (HfO
2), aluminium oxide (Al
2O
3) and tantalum oxide (Ta
2O
5) material selected in the group formed, and plate node 33 comprises titanium nitride (TiN), tungsten (W), platinum (Pt) or ruthenium (Ru).
According to this specific embodiment; crystal grain by TiN memory node 29 during sacrifice layer 26 wet drains out technology is penetrated in the substructure wet-chemical material or the surface portion of the TiN memory node by contact etch barrier layer 24 is penetrated in the substructure wet-chemical material to be prevented by introducing the first and second protection barrier layers 25 and 31, and therefore the infundibulate generation of defects can be prevented from.
As mentioned above; be not only limited to the situation that memory node utilizes TiN to form by introducing first and second effects that the wet-chemical material is penetrated in the substructure that prevent of protecting barrier layers 25 and 31 to be obtained, can also obtain by introducing other material such as Pt and Ru.
And, might be used to protect the amorphous carbon of the material on barrier layer by introducing, wet drain out technology during by preventing that substructure from being damaged by the wet-chemical material, obtain to improve the effect of chip yield.
The application comprises the korean patent application No.KR 2004-0113514 subject content of submitting in Korean Patent office with on December 28th, 2004 relevant with korean patent application No.KR 2004-0113515, and its full content is incorporated herein by reference.
Although described the present invention in conjunction with some specific embodiment, be apparent that for those skilled in the art, under the spirit and scope of the present invention situation that in not breaking away from, limits, can carry out various variations and remodeling as following claim.
Claims (17)
1. method that is used for producing the semiconductor devices comprises:
On substrate, form interlayer insulating film;
Formation is penetrated into a plurality of storage node contact plug in the described interlayer insulating film;
Formation is by piling up first protection barrier layer and the formed stacked structure of sacrifice layer on described interlayer insulating film;
Come etch process is carried out on described first protection barrier layer and described sacrifice layer in mode with the open groove in the top that makes described storage node contact plug;
At the inner a plurality of memory nodes that form of described groove with column type;
Forming filling agent has the second protection barrier layer of the described memory node inside of described column type;
Wet drain out technology and remove described sacrifice layer by carrying out;
Remove described first protection barrier layer and the described second protection barrier layer; And
On described memory node, form dielectric layer and plate node successively.
2. the process of claim 1 wherein that described first protection barrier layer and the described second protection barrier layer form by using amorphous carbon.
3. the method for claim 2, wherein said amorphous carbon forms to about 600 ℃ temperature from about 50 ℃ in scope.
4. the method for claim 2, the wherein said first protection barrier layer with scope from about 5nm to about 1, the thickness of 000nm forms.
5. the method for claim 2, the removing of wherein said first protection barrier layer and the described second protection barrier layer by using plasma state oxygen (O
2) gas carries out.
6. the method for claim 5, wherein said first and the described second protection barrier layer removed simultaneously.
7. the process of claim 1 wherein that the described first protection barrier layer forms by using amorphous carbon, and the described second protection barrier layer forms by using photoresist layer.
8. the method for claim 7 wherein forms to about 600 ℃ temperature from about 50 ℃ in scope as the first wet described amorphous carbon that corrodes the barrier layer and form, and have scope from about 5nm to about 1, the thickness of 000nm.
9. the method for claim 7, wherein said photoresist layer from by the photoresist layer that is used for KrF, be used for ArF photoresist layer, be used for electron beam photoresist layer, be used for X ray photoresist layer, be used for the photoresist layer of extreme ultraviolet line (EUV) and be used for the group that the photoresist layer of ion beam forms selecting.
10. the method for claim 7, the formation on wherein said first protection barrier layer and the described second protection barrier layer is by using O
2Plasma is carried out.
11. the method for claim 10, wherein said first and described second protects the barrier layer to be removed simultaneously.
12. the process of claim 1 wherein that described stacked structure further comprises etch stop layer.
13. the method for claim 12, wherein said etch stop layer is a nitride layer.
14. the process of claim 1 wherein that the formation of described a plurality of memory nodes comprises:
On the surface of the stacked structure that comprises described groove, form conductive layer;
On described conductive layer, form the passivation layer of filling described groove inside;
Optionally removing described conductive layer is retained on the described groove up to described conductive layer; And
Optionally remove described passivation layer.
15. the method for claim 14, wherein said passivation layer comprise one in photoresist layer and unadulterated silicate glass (USG) layer.
16. the method for claim 14, wherein said memory node comprise titanium nitride (TiN).
17. the process of claim 1 wherein that described memory node comprises TiN.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040113514A KR100780611B1 (en) | 2004-12-28 | 2004-12-28 | Method for manufacturing capacitor of semiconductor memory device using amorphous carbon |
| KR1020040113514 | 2004-12-28 | ||
| KR1020040113515 | 2004-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1819156A true CN1819156A (en) | 2006-08-16 |
| CN100394585C CN100394585C (en) | 2008-06-11 |
Family
ID=36919058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101375000A Expired - Fee Related CN100394585C (en) | 2004-12-28 | 2005-12-26 | Method for fabricating capacitor of semiconductor memory device using amorphous carbon |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100780611B1 (en) |
| CN (1) | CN100394585C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101367504B (en) * | 2007-08-17 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing micro-electronic mechanical system with micro-mirror |
| CN108717936A (en) * | 2018-06-27 | 2018-10-30 | 长鑫存储技术有限公司 | Double sided capacitor structure and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100869236B1 (en) * | 2006-09-14 | 2008-11-18 | 삼성전자주식회사 | Method for manufacturing a capacitor and Method of manufacturing a dynamic random access memory device by using the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980021248A (en) * | 1996-09-14 | 1998-06-25 | 김광호 | Semiconductor device fine pattern formation method |
| TW405258B (en) * | 1999-04-30 | 2000-09-11 | Taiwan Semiconductor Mfg | Manufacture method of DRAM capacitor |
| KR100382732B1 (en) * | 2001-01-10 | 2003-05-09 | 삼성전자주식회사 | Method for fabricating cylinder-type capacitor of semiconductor device |
| KR100393229B1 (en) * | 2001-08-11 | 2003-07-31 | 삼성전자주식회사 | Method of manufacturing non-volatile memory device including self-aligned gate structure and device by the same |
| KR100476936B1 (en) * | 2002-10-30 | 2005-03-17 | 삼성전자주식회사 | Semiconductor device having capacitors of Metal-Insulator-Metal structure and Method of forming the same |
| JP2004247559A (en) * | 2003-02-14 | 2004-09-02 | Elpida Memory Inc | Semiconductor device and method for manufacturing the same |
| KR100532434B1 (en) * | 2003-05-09 | 2005-11-30 | 삼성전자주식회사 | Methods for manufacturing capacitor of semiconductor memory device |
| KR100510558B1 (en) * | 2003-12-13 | 2005-08-26 | 삼성전자주식회사 | Method for forming pattern |
-
2004
- 2004-12-28 KR KR1020040113514A patent/KR100780611B1/en not_active IP Right Cessation
-
2005
- 2005-12-26 CN CNB2005101375000A patent/CN100394585C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101367504B (en) * | 2007-08-17 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing micro-electronic mechanical system with micro-mirror |
| CN108717936A (en) * | 2018-06-27 | 2018-10-30 | 长鑫存储技术有限公司 | Double sided capacitor structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100780611B1 (en) | 2007-11-29 |
| CN100394585C (en) | 2008-06-11 |
| KR20060074971A (en) | 2006-07-04 |
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Granted publication date: 20080611 Termination date: 20131226 |