CN108717936A - Double sided capacitor structure and preparation method thereof - Google Patents
Double sided capacitor structure and preparation method thereof Download PDFInfo
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- CN108717936A CN108717936A CN201810676961.2A CN201810676961A CN108717936A CN 108717936 A CN108717936 A CN 108717936A CN 201810676961 A CN201810676961 A CN 201810676961A CN 108717936 A CN108717936 A CN 108717936A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 159
- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000010276 construction Methods 0.000 claims abstract description 34
- 230000000873 masking effect Effects 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 27
- -1 phosphonium ion Chemical class 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical group [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 5
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000410 antimony oxide Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 claims description 4
- ZARVOZCHNMQIBL-UHFFFAOYSA-N oxygen(2-) titanium(4+) zirconium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4] ZARVOZCHNMQIBL-UHFFFAOYSA-N 0.000 claims description 4
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000003667 anti-reflective effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- 230000007812 deficiency Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 3
- 241000446313 Lamella Species 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018316 SbOx Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 229940085991 phosphate ion Drugs 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The present invention provides a kind of preparation method of double sided capacitor structure, and this method includes：1）Semi-conductive substrate is provided, in forming laminated construction in semiconductor substrate, 2）In forming Patterned masking layer on laminated construction, multiple capacitance holes are etched in laminated construction based on Patterned masking layer；3）Lower electrode layer is formed in the bottom in capacitance hole and side wall；4）In step 3）Mask layer is formed in obtained structure, based on mask layer in forming mask open on laminated construction, is open and exposes 20% ~ 60% internal orifice dimension area in capacitance hole, be based on mask open, remove sacrificial layer；5）Capacitor dielectric layer is formed in the inner surface of lower electrode layer and outer surface, upper electrode layer is formed in the outer surface of capacitor dielectric layer.The present invention uses different trepanning modes, and by controlling capacitance perforated area and using supporting layer etch gas source, density is closeer to being formed, and mechanical strength is stronger and the double sided capacitor of certifiable capacitance.
Description
Technical field
The present invention relates to IC manufacturing fields, more particularly to a kind of double sided capacitor structure and preparation method thereof.
Background technology
((Dynamic Random Access Memory, DRAM) is commonly used in computer to dynamic random access memory
Semiconductor storage unit, be made of the storage unit of many repetitions.Each storage unit generally includes capacitor and transistor；
The grid of transistor is connected with wordline, drain be connected with bit line, source electrode is connected with capacitor；Voltage signal in wordline can be controlled
Transistor processed opens or closes, and then reads the data information of storage in the capacitor by bit line, or will by bit line
Data information is written in capacitor and is stored.
As making technology continues evolution, DRAM integrated levels are continuously improved, and constantly micro, capacitor store component size
Charge capacity also faces test.Capacitor in existing dynamic RAM is mostly single side capacitor arrangement, serious to limit
The raising of capacitance in unit area, as shown in Figure 1, the capacitor includes 1 ˊ of lower electrode layer, 2 ˊ of capacitor dielectric layer is powered on
Pole 3 ˊ of layer.
In order to further increase the storage charge of capacitor, a kind of two-sided DRAM capacitor knot increasing electrode plate surface product
Structure is paid more and more attention.Patent publication No. is that the patent document of TWI440190B discloses a kind of stack stochastic and dynamic access note
The manufacturing method for recalling the two-sided capacitance of body, includes the following steps：Sacrificial layer is inserted in capacitor trench；The first coating of coating
With the second coating on sacrificial layer；Second coating of part on sacrificial layer is modified；It removes and is located at not
The second coating and the first coating for modifying part, to expose the sacrificial layer of part；Along the exposed portion of the sacrificial layer
Divide and be etched, to expose electrode layer；The exposed part for removing the electrode layer, to expose oxide layer；And removal is sacrificed
Layer and oxide layer, whereby, those electrode series of strata are correspondingly formed a plurality of two-sided capacitances.Patent publication No. is TWI399831B's
Patent document also discloses that a kind of manufacturing method of the capacitance structure of stack stochastic and dynamic access/memory body, including following step
Suddenly：A supporting layer is deposited on a dielectric layer；Several supporting layer openings are formed in the supporting layer；It is open in each supporting layer
One buffer oxide of middle filling；Several capacitor trench are made in the dielectric layer, and the capacitor trench system is distributed in the branch
Between support layer opening；In forming an electrode layer on the inner wall of each capacitor trench；And along these supporting layers be open into
Row etching inserts the buffer oxide of those supporting layer openings and between the electrode layer of adjacent capacitor trench with removal
Dielectric layer, whereby, those electrode series of strata height are asymmetrically formed a plurality of two-sided capacitances.
However, the manufacture craft of two-sided DRAM capacitor structure is all complex at present, electrode structure is easier to collapse, system
Structure intensity, yield etc. it is to be improved, when especially removing sacrificial layer, the property of the perforated area in capacitance hole to capacitor
There can be larger impact, when perforated area is excessive, be easy to cause capacitor and collapse and short circuit, when perforated area is too small, be easy to cause
Sacrificial layer can not completely remove, to reduce capacity area and reduce capacitance.In view of this, for how to ensure sacrificial layer
The problem of making capacitor be not easy to collapse while being completely removed, it is really necessary to change to traditional DRAM capacitor technique
It is good.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of its structure of two-sided capacitance and its
Preparation method, for solving in the prior art when removing sacrificial layer, the perforated area in capacitance hole is excessive to be easy to cause capacitor
Collapse and short circuit, the too small sacrificial layer of perforated area in capacitance hole can not completely remove, leads to capacity area reduction and capacitance drop
Low problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of double sided capacitor structure,
Include the following steps：
1) semi-conductive substrate is provided, in forming laminated construction in the semiconductor substrate, the laminated construction includes handing over
For the supporting layer and sacrificial layer of stacking；
2) in forming Patterned masking layer on the laminated construction, based on the Patterned masking layer in the laminated construction
In etch multiple capacitance holes；
3) lower electrode layer is formed in the bottom in the capacitance hole and side wall, the supporting layer connects the lower electrode layer；
4) it in forming mask layer in the structure that step 3) obtains, is covered in formation on the laminated construction based on the mask layer
Film is open, wherein the mask open exposes 20%~60% internal orifice dimension area in the capacitance hole, and is covered based on described
Film is open, and removes in the sacrificial layer and the mask open and be alternately laminated in the supporting layer on the sacrificial layer,
In, the supporting layer for being located at bottom retains on the semiconductor substrate；
5) capacitor dielectric layer is formed in the inner surface of the lower electrode layer and outer surface, wherein the capacitor dielectric layer covers
The lower electrode layer is covered, and upper electrode layer is formed in the outer surface of the capacitor dielectric layer, wherein the upper electrode layer covers institute
State capacitor dielectric layer and the supporting layer.
Preferably, the laminated construction includes the base layer support layer, the first sacrificial layer, intermediate supports being up laminated successively
Layer, the second sacrificial layer and top support layer.The material of first sacrificial layer includes the silica of boron phosphorus doping, wherein institute
It includes upper straton sacrificial layer and lower straton sacrificial layer to state the first sacrificial layer, and the phosphonium ion doping concentration of lower straton sacrificial layer is more than
The phosphonium ion doping concentration of upper straton sacrificial layer, to improve etching power of the etching to first sacrificial layer of step 2), and
The etching of step 2) is higher than the etching efficiency of the lower straton sacrificial layer etching efficiency to the upper straton sacrificial layer.
Further, the weight percent of the phosphonium ion content of the lower straton sacrificial layer is between 3%~5%, boron
The weight percent of ion concentration is between 2%~7%；The weight percent of the phosphonium ion content of the upper straton sacrificial layer
Between 3%~5%, the weight percent of boron ion content is between 5%~10%.
Further, step 4) includes the following steps：
4-1) in sequentially formed in the structure that step 3) obtains nitride mask layer, oxide mask layer, anti-reflecting layer and
Photoresist layer；
The anti-reflecting layer, the oxide mask layer and the nitride 4-2) are sequentially etched based on the photoresist layer
Mask layer, in forming the mask open on the laminated construction；
It 4-3) is based on the mask open, in forming the first support opening in the top support layer, with exposure described the
Two sacrificial layers；
It 4-4) is based on the first support opening, second sacrificial layer is removed using wet-etching technology；
4-5) in forming the second support opening in the middle support layer, with exposure first sacrificial layer；
It 4-6) is based on the second support opening, first sacrificial layer is removed using wet-etching technology.
Further, step 4-2) in, a mask open is overlapping with multiple capacitance bore portions simultaneously；Step
In 4-3), the first support opening is overlapping with multiple capacitance bore portions simultaneously；Step 4-5) in, one described
Two support openings are overlapping with multiple capacitance bore portions simultaneously.
Further, a mask open is overlapping with three capacitance bore portions simultaneously, one described first
It is overlapping with three capacitance bore portions simultaneously to strut mouth, the second support opening simultaneously with three capacitance hole portions
Divide overlapping.
Further, the diameter of the mask open is between 50nm~90nm.
Preferably, step 4-3) in, it uses top support layer described in dry etching and is open with forming first support, carved
Erosion gas source includes chlorine, oxygen and argon gas, meanwhile, the lower electrode layer is in the first support opening and described first
Height outside support opening differs 100nm~150nm.
Preferably, step 4-5) in, it uses middle support layer described in dry etching and is open with forming second support, carved
Erosion gas source includes chlorine, oxygen and argon gas, meanwhile, the lower electrode layer is in the second support opening and described second
Height outside support opening differs 110nm~180nm.
Preferably, step 4-4) in wet etching solution include 30%~60% hydrofluoric acid, step 4-6) in it is wet
Method etching solution includes 30%~60% hydrofluoric acid.
Preferably, step 2) includes the following steps：
2-1) in sequentially forming barrier in the structure that step 1) obtains；
2-2) in step 2-1) obtained structure upper edge first direction forms the first etched features using pitch multiplication process；
2-3) in step 2-2) use pitch multiplication process to form the second etched features in a second direction in obtained structure,
To obtain the double-deck etched features, wherein the first direction has angle with second direction；
The region other than the double-deck etched features overlapping region 2-4) is etched, to form the Patterned masking layer.
Further, the barrier includes polysilicon barrier layer, barrier oxide layers and carbide blocking successively
Layer；And step 2-4) include the following steps：
The region other than the overlapping region of the double-deck etched features region 2-4-1) is etched, the capacitor is formed
Multiple windows of array structure；
It 2-4-2) is sequentially etched the polysilicon barrier layer, barrier oxide layers and silicide barrier layer along the window,
To form the Patterned masking layer.
Further, the barrier oxide layers include silica barrier layer.
Preferably, the material of the supporting layer includes at least one of the group being made of silicon nitride, silicon oxynitride, institute
The material for stating capacitor dielectric layer includes by zirconium oxide, hafnium oxide, titanium Zirconium oxide, titanium oxide, ruthenium-oxide, antimony oxide, aluminium oxide
At least one of group of composition.
Preferably, include capacitor area in the semiconductor substrate, be used to form the double sided capacitor structure, it is described
Further include capacitor peripheral circuit area in semiconductor substrate, be used to form the double sided capacitor peripheral circuit, described in formation
After double sided capacitor structure, photoresist layer is formed in the capacitor area, the photoresist layer is for protecting the capacitor
Then region etches the capacitor peripheral circuit area, be etched to and be only left the semiconductor substrate and the institute positioned at bottom
State supporting layer.
The present invention also provides a kind of double sided capacitor structures, including：
Semiconductor substrate；
Lower electrode layer is formed in the semiconductor substrate, and the cross sectional shape of the lower electrode layer includes U-shaped, wherein institute
State height difference 110nm~180nm of U-shaped lower electrode layer both sides；
Capacitor dielectric layer is covered in inner surface and the outer surface of the lower electrode layer；
Upper electrode layer is covered in the outer surface of the capacitor dielectric layer.
Preferably, the double sided capacitor structure further includes top support layer, middle support layer and base layer support layer, equal shape
In semiconductor substrate described in Cheng Yu and connect the lower electrode layer, wherein the top support layer connects the lower electrode layer
Mouth periphery, the middle support layer connect the middle part of the lower electrode layer, and the base layer support layer is formed in the semiconductor
The bottom periphery of substrate surface and the connection lower electrode layer.
Further, there is the top support layer the first support to be open, 20%~60% outer diameter of the lower electrode layer
Area S portion is overlapped in the first support opening.
Further, there is the middle support layer the second support to be open, 20%~60% outer diameter of the lower electrode layer
Area S portion is overlapped in the second support opening.
Preferably, include capacitor area in the semiconductor substrate, be used to form the double sided capacitor structure, it is described
Further include capacitor peripheral circuit area in semiconductor substrate, is used to form the double sided capacitor peripheral circuit, the capacitance
Device peripheral circuit area includes the semiconductor substrate and the base layer support layer.
Preferably, the double sided capacitor structure further includes top electrode filled layer, covers the outer surface of the upper electrode layer,
And it is filled in the gap between the upper electrode layer.
As described above, the preparation method of the double sided capacitor structure of the present invention, has the advantages that：The present invention uses
Different trepanning modes, by control capacitance perforated area to ensure that sacrificial layer completely removes while again do not lose it is excessive under
Electrode layer etches gas to ensure that capacitance is not easy to collapse while effectively improving capacity area additionally by supporting layer is used
Body source ensures that lower electrode layer loses in suitable range, to be completely removed sacrificial layer while ensureing lower electrode layer area, from
And forming that density is closeer, mechanical strength is stronger and the double sided capacitor of certifiable capacitance.
Description of the drawings
Fig. 1 is shown as the structural schematic diagram of single side capacitor in the prior art.
Fig. 2 is shown as the preparation technology flow chart of the double sided capacitor structure of the present invention.
Fig. 3 is shown as forming showing for the supporting layer and sacrificial layer being alternately superimposed in the double sided capacitor structure preparation of the present invention
It is intended to.
Fig. 4 is shown as forming Patterned masking layer photoetching direction schematic diagram in the double sided capacitor structure preparation of the present invention.
Fig. 5 a~5h are shown as forming the structural representation of Patterned masking layer in the double sided capacitor structure preparation of the present invention
Figure.
Fig. 6 is shown as forming the structural schematic diagram in capacitance hole in the double sided capacitor structure preparation of the present invention.
Fig. 7 is shown as forming the structural schematic diagram of lower electrode layer in the double sided capacitor structure preparation of the present invention.
Fig. 8 a~8d are shown as forming the vertical view of mask open in the double sided capacitor structure preparation of the present invention, wherein
AA ˊ representatives are longitudinal sectional along 1 directions θ, and Fig. 8 d are the partial enlarged views of Fig. 8 c.
Fig. 9 a~Fig. 9 b are shown as in Fig. 8 c the structural schematic diagram that the section along 1 directions θ forms mask open.
Fig. 9 c~Fig. 9 d are shown as in Fig. 8 c the structural schematic diagram that the section along 1 directions θ forms the first support opening.
Figure 10 is shown as removing the structural schematic diagram after the second sacrificial layer in Fig. 8 c along the section in 1 directions θ.
Figure 11 is shown as in Fig. 8 c the structural schematic diagram that the section along 1 directions θ forms the second support opening.
Figure 12 is shown as removing the structural schematic diagram after the first sacrificial layer in Fig. 8 c along the section in 1 directions θ.
Figure 13 is shown as forming the structure of photoresist layer in the double sided capacitor structure preparation of the present invention in capacitor area
Schematic diagram.
The structure that Figure 14 is shown as being formed capacitor peripheral circuit area in the double sided capacitor structure preparation of the present invention is shown
It is intended to.
Component label instructions
1 ˊ lower electrode layers
2 ˊ capacitor dielectric layers
3 ˊ upper electrode layers
1 semiconductor substrate
11 capacitor array areas
2 supporting layers
21 base layer support layers
22 middle support layers
23 top support layers
3 sacrificial layers
31 first sacrificial layers
311 times straton sacrificial layers
Straton sacrificial layer on 312
32 second sacrificial layers
33 Non-overlapping Domains
4 Patterned masking layers
41 barriers
411 polysilicon barrier layers
412 barrier oxide layers
413 carbide barrier layers
42 multi-layer mask layers
421 first dielectric anti-reflective layers
422 carbide lamellas
423 second dielectric anti-reflective layers
424 photoresist layers
The 43 double-deck etched features
431 first etched features
432 second etched features
433 windows
5 capacitance holes
6 lower electrode layers
60 mask layers
61 nitride mask layers
62 oxide mask layers
63 carbide mask layers
64 anti-reflecting layers
65 photoresist layers
66 mask opens
661 first support openings
662 second support openings
7 capacitor dielectric layers
8 upper electrode layers
9 top electrode filled layers
91 photoresist layers
1 first directions of θ
2 second directions of θ
Angle
S capacitances hole exposed area
D opening diameters
The first differences in height of H1
The second differences in height of H2
A capacitor areas
B capacitor peripheral circuit areas
S1~S5 steps
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig.1~Figure 13.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 2, the present embodiment provides a kind of preparation method of double sided capacitor structure, the double sided capacitor structure
Preparation method include at least following steps：
1) semi-conductive substrate is provided, in forming laminated construction in the semiconductor substrate, the laminated construction includes handing over
For the supporting layer and sacrificial layer of stacking；
2) in forming Patterned masking layer on the laminated construction, based on the Patterned masking layer in the laminated construction
In etch multiple capacitance holes；
3) lower electrode layer is formed in the bottom in the capacitance hole and side wall, the supporting layer connects the lower electrode layer；
4) it in forming mask layer in the structure that step 3) obtains, is covered in formation on the laminated construction based on the mask layer
Film is open, wherein the mask open exposes 20%~60% internal orifice dimension area in the capacitance hole, is opened based on the mask
Mouthful, it removes in the sacrificial layer and the mask open and is alternately laminated in the supporting layer on the sacrificial layer, wherein position
Retain on the semiconductor substrate in the supporting layer of bottom；
5) capacitor dielectric layer is formed in the inner surface of the lower electrode layer and outer surface, wherein the capacitor dielectric layer covers
The lower electrode layer is covered, and upper electrode layer is formed in the outer surface of the capacitor dielectric layer, wherein the upper electrode layer covers institute
State capacitor dielectric layer and the supporting layer.
Below in conjunction with the preparation method of attached drawing two-sided its structure of capacitance that the present invention will be described in detail.
First, as shown in the S1 and Fig. 3 in Fig. 2, step 1) is carried out, semi-conductive substrate 1 is provided, served as a contrast in the semiconductor
Laminated construction is formed on bottom 1, the laminated construction includes alternately stacked supporting layer 2 and sacrificial layer 3.
As an example, the capacitance contact node (figure that the semiconductor substrate 1, which includes several, to be located in memory array structure
Do not show).
Specifically, in a concrete structure, the semiconductor substrate 1 further includes semiconductor base (not shown), semiconductor
Active area and wordline are set in substrate, bit line and the capacitance contact node, the capacitance contact section are set on semiconductor base
Point is electrically connected the transistor source etc. in the memory array structure.
As an example, in step 1), the quantity of the supporting layer 2 of formation is more than the quantity of the sacrificial layer 3 formed,
And underlying material layers in the laminated construction that constitutes of the sacrificial layer 3 and the supporting layer 2 and quilting material layer are the branch
Support layer 2.
In a preferable example, as shown in figure 3, the quantity of the supporting layer 2 is three layers, including top support layer 23,
Middle support layer 22 and base layer support layer 21, the quantity of the sacrificial layer 3 are two layers, including be located at the base layer support layer 21 with
The first sacrificial layer 31 between the middle support layer 22 and positioned at the top support layer 23 and the middle support layer 22
Between the second sacrificial layer 32.
Specifically, atom layer deposition process (Atomic Layer Deposition) may be used or plasma vapor is heavy
Product technique (Plasma Enhenced Chemical Vapor Deposition) forms each supporting layer 2 and each sacrificial layer 3,
Such as the base layer support layer 21, first sacrificial layer 31, the middle support layer 22, second sacrificial layer 32 and described
Top support layer 23.
As an example, the material of the supporting layer 2 includes at least one in the group being made of silicon nitride, silicon oxynitride
Kind, it is preferable that the material of the supporting layer 2 includes silicon nitride.The material of the sacrificial layer 3 includes oxide, it is preferable that described
Oxide can be silica or silicon oxynitride.It should be noted that the material of the material of the sacrificial layer 3 and the supporting layer 2
Material is different, and the corrosion rate both in same etching process (such as same corrosive liquid) is different, is embodied at same a moment
In erosion process (such as same corrosive liquid), etching (as corroded) rate of the sacrificial layer 3 is far longer than the etching of the supporting layer 2
Rate so that when the sacrificial layer 3 is completely removed, the supporting layer 2 is almost fully retained.
In a preferable example, as shown in figure 3, second sacrificial layer 32 is different from the material of the first sacrificial layer 31,
The material of second sacrificial layer 32 includes silica or silicon oxynitride.The material of first sacrificial layer 31 includes boron phosphorus doping
Silica (BPSG, boron-phosphorosilicate glass), and phosphonium ion doping concentration is different at the different-thickness of first sacrificial layer 31, table
It includes lower straton sacrificial layer 311 and upper straton sacrificial layer 312 to be now, wherein the phosphonium ion doping concentration of lower straton sacrificial layer 311
More than the phosphonium ion doping concentration of upper straton sacrificial layer 312.Since the corrosion rate of BPSG is by boron ion and phosphate ion concentration
It influencing, increases the content of boron ion, corrosion rate can decline, and increase the content of phosphonium ion, and corrosion rate can be increased significantly, and the
One sacrificial layer 31 is need to be completed in same etching process, so improving the phosphorus of the lower straton sacrificial layer 311 of the first sacrificial layer 31
Ion concentration can effectively ensure that the complete etching of the first sacrificial layer 31, and etching deficiency is avoided to lead to the reduction of capacitor performance.This
In embodiment, between 3%~5%, boron ion contains the weight percent of the phosphonium ion content of the lower straton sacrificial layer 311
Between 2%~7%, the weight percent of the phosphonium ion content of the upper straton sacrificial layer 312 is situated between the weight percent of amount
Between 3%~5%, the weight percent of boron ion content is between 5%~10%.
In addition, the sacrificial layer 3 can be removed during subsequent technique, the effect of the supporting layer 2 is described
The mechanical strength of structure when sacrificial layer 3 subsequently makes capacitor as braced frame after being removed to improve, so removing above-mentioned row
Except in the case of the three layers of supporting layer and two layers of sacrificial layer lifted, the quantity of the sacrificial layer and supporting layer can be according to subsequent capacitance device
Required height is set, and the quantity of stacking can be for 1~10 time or more, wherein are advisable with 2~5 times.
Then, as in Fig. 2 S2 and Fig. 4, Fig. 5 a to Fig. 5 h and Fig. 6 shown in, carry out step 2), on the laminated construction
Patterned masking layer 4 is formed, etches multiple capacitance holes 5 in the laminated construction based on the Patterned masking layer 4.
As preferable example, the step of forming the Patterned masking layer 4, includes：
As shown in Figure 5 a, step 2-1), in sequentially forming barrier 41 in the structure that step 1) obtains, as showing
Example, the barrier 41 are three layers, include polysilicon barrier layer 411, barrier oxide layers 412 and carbide blocking successively
Layer 413.
As shown in Fig. 4 and Fig. 5 b~5c, step 2-2), in step 2-1) between obtained 1 uses of structure upper edge first direction θ
The first etched features 431 are formed away from multiplication process.
Fig. 4 is shown as forming the photoetching direction schematic diagram of the Patterned masking layer 4 in prepared by vertical capacitor structure, is
Increase the making density of capacitor, it can be by the way that there is angle along two in capacitor array area 11First direction θ 1 and
Second direction θ 2 is performed etching, and forms the Non-overlapping Domain 33 of array distribution, etches the Non-overlapping Domain 33 to form capacitance
Hole 5, as shown in fig. 6, vertical capacitor structure can be formed based on the capacitance hole 5.
Specifically, as shown in Figure 5 b, in sequentially forming multi-layer mask layer 42 and photoresist on the carbide barrier layer 413
Layer 424, as an example, the multi-layer mask layer 42 is three layers, include the first dielectric anti-reflective layer 421, carbide lamella successively
422, the second dielectric anti-reflective layer 423.As shown in Figure 5 c, it is based on the photoresist layer 424, is used along the first direction θ 1
Pitch multiplication process forms first etched features 431.
As shown in Fig. 4 and Fig. 5 d, step 2-3), in step 2-2) θ 2 uses spacing times in a second direction in obtained structure
Increase technique and form the second etched features 432, to obtain the double-deck etched features 43.As an example, forming the second etching figure
The method of shape 432 is identical as the method for forming first etched features 431, so this will not be repeated here.
As shown in Fig. 5 e~5h, step 2-4), the region other than 43 overlapping region of the double-deck etched features is etched, with shape
At the Patterned masking layer 4.
Specifically, as depicted in fig. 5e, the area other than the overlapping region of 43 region of the double-deck etched features is first etched
Domain forms multiple windows 433 of the array of capacitors structure；As shown in Fig. 5 f~5h, then carved successively along the window 433
Lose the carbide barrier layer 413 (as shown in figure 5f), barrier oxide layers 412 (as shown in fig. 5g) and polysilicon barrier layer
411 (as shown in figure 5h), to form the Patterned masking layer 4.As an example, the barrier oxide layers 412 include oxidation
Silicon barrier layer.
As shown in fig. 6, the supporting layer 2 and the sacrificial layer 3 are etched based on the Patterned masking layer 4, to be formed
State multiple capacitance holes 5.
As an example, the specific method for forming the capacitance hole 5 is：It is carved using dry method according to the Patterned masking layer 4
The technique that etching technique, wet-etching technology or dry etch process are combined with wet-etching technology etch the supporting layer 2 and
The sacrificial layer 3, to form the capacitance hole 5 up and down in the supporting layer 2 and the sacrificial layer 3.
Continue, as shown in the S3 and Fig. 7 in Fig. 2, carries out step 3), formed down in the bottom in the capacitance hole 5 and side wall
Electrode layer 6, the supporting layer 2 connect the lower electrode layer 6.
Preferably, using atom layer deposition process in the side wall in the capacitance hole 5 and bottom and the top support layer
23 upper surface deposits lower electrode material layer, the material of the lower electrode layer 6 include by polysilicon, titanium nitride, titanium carbide and
At least one of the group of tungsten composition, in the present embodiment, the material of the preferably lower electrode layer 6 includes titanium nitride, then may be used
To be deposited on the lower electrode material layer of the upper surface of the top support layer 23 using etching technics removal, can also will go
Except the upper surface of the top support layer 23 the lower electrode material layer the step of be placed on the when of subsequently removing the sacrificial layer 3
It removes, the present embodiment is selected when subsequently removing the sacrificial layer 3, and the upper table of the top support layer 23 is removed using dry etching
The lower electrode material layer in face, etch gas source include boron chloride and argon gas.
Continue, as shown in S4 and Fig. 8 a~Figure 12 in Fig. 2, carries out step 4), formed in the structure that step 3) obtains
Mask layer 60, based on the mask layer 60 in formation mask open 66 on the laminated construction, wherein the mask open 66 is sudden and violent
Expose 20%~60% internal orifice dimension area S in the capacitance hole, referred to as capacitance hole exposed area S, be based on the mask open 66,
It removes in the sacrificial layer 3 and the mask open 66 and is alternately laminated in the supporting layer 2 on the sacrificial layer 3, wherein
The supporting layer 2 positioned at bottom is retained in the semiconductor substrate 1.When the capacitance hole exposed area S is more than above-mentioned model
It encloses, the lower electrode layer 6 can be made excessively to remove, the lower electrode layer 6 removes excessively, be easy to cause capacitance and collapses and short-circuit, together
When capacity area can also reduce to reduce capacitance；When the capacitance hole exposed area S be less than above range, be easy to cause institute
Stating sacrificial layer can not completely remove, and the sacrificial layer, which can not completely remove, to cause capacity area to reduce, to make capacitance drop
It is low.
As an example, the mask open 66 exposes 20%~25% internal orifice dimension area in the capacitance hole.
As an example, step 4) includes the following steps：
Step 4-1), as illustrated in fig. 9, in sequentially forming nitride mask layer 61, oxide in the structure that step 3) obtains
Mask layer 62, carbide mask layer 63, anti-reflecting layer 64 and photoresist layer 65.
Step 4-2), as shown in figure 9b, the anti-reflecting layer 64 is sequentially etched based on the photoresist layer 65, carbide is covered
Film layer 63, oxide mask layer 62 and nitride mask layer 61, in forming the mask open 66 on the laminated construction,
In, the mask open exposes 20%~60% internal orifice dimension area S in the capacitance hole 5.Based on the mask open 66, go
Except the lower electrode material layer of the upper surface of the top support layer 23, as is shown in fig. 9 c.
Step 4-3), as shown in figure 9d, it is based on the mask open 66, in formation first in the top support layer 23
Mouth 661 is strutted, with exposure second sacrificial layer 32.
As an example, using top support layer 23 described in dry etching to form the first support opening 661, gas is etched
Body source includes chlorine, oxygen and argon gas, and uses etching terminal detection device detection CN wavelength signals to detect etching terminal, by
In while etching top support layer 23, the lower electrode layer of both sides can also be etched, so, after the step,
Height of the lower electrode layer in the first support opening 661 and outside the first support opening 661 has difference, should
Difference need to be controlled in 100nm~150nm, can then lead to that capacitor is easy to collapse and capacity area subtracts when the difference is more than this range
It is small, capacitance is reduced, which, which is less than this range, then can cause the top support layer 23 to etch deficiency, described to make
Sacrificial layer 3 can not completely remove.
Step 4-4), based on the first support opening 661, second sacrificial layer is removed using wet-etching technology
32, wherein preferably, wet etching solution includes 30%~60% hydrofluoric acid, as shown in Figure 10.
Step 4-5), in forming the second support opening 662 in the middle support layer 22, with exposure first sacrificial layer
31, as shown in figure 11.
Specifically, middle support layer 22 described in dry etching is used to form the second support opening 662, etching gas
Source includes chlorine, oxygen and argon gas, and etching terminal detection device is used to detect CN wavelength signal to detect etching terminal, simultaneously
The nitride mask layer 61 is removed, dry etching is then used to remove the described of the upper surface of remaining top support layer 23
Lower electrode material layer.Since while etching middle support layer 22, the lower electrode layer of both sides can also be etched, the step
After rapid, height meeting of the lower electrode layer in the second support opening 662 and outside the second support opening 662
There is further difference, which need to control in 110nm~180nm, can then lead to capacitance when the height difference is more than this range
Device is easy to collapse and capacity area reduces, and reduces capacitance, which, which is less than this range, can lead to the middle support layer
22 etchings are insufficient, to make the sacrificial layer 3 that can not completely remove.
Step 4-6), based on the second support opening 662, first sacrificial layer is removed using wet-etching technology
31, wherein preferably, wet etching solution includes 30%~60% hydrofluoric acid, as shown in figure 12.
As an example, step 4-5) and step 4-6) between further include in the top support layer 23 upper surface deposit branch
The step of supportting layer material, the top support layer 23 is thickened.This is because in step 4-5) during, the top layer branch
Support layer 23 can be removed a part, and the top support layer 23 is cut through during subsequent corrosion in order to prevent, and ensures institute
State upper layer supporting layer have enough support strengths, need in step 4-5) with step 4-6) between add in the upper layer support
The step of upper surface depositing support layer material of layer 23.
As an example, step 4-2) in, a mask open 66 is overlapping with multiple 6 parts of capacitance hole simultaneously；
Step 4-3) in, the first support opening 661 is overlapping with multiple 6 parts of capacitance hole simultaneously；Step 4-5) in, one
A second support opening 662 is overlapping with multiple 6 parts of capacitance hole simultaneously.Preferably, as shown in Figure 8 a, described in one
Mask open 66 is overlapping with 86 parts of capacitance hole simultaneously, a corresponding first support opening 661 and an institute
It is overlapping with 8 capacitance bore portions simultaneously to state the second support opening 662；As shown in Figure 8 b, a mask open 66 is same
When it is overlapping with 66 parts of capacitance hole, a corresponding first support opening 661 and one described second support
Mouth 662 is overlapping with 6 capacitance bore portions simultaneously, both capacitance trepanning modes are easier to, and the sacrificial layer 3 is relatively easy to
Removal, but binding force is relatively weak between capacitance and capacitance.As a preferred embodiment, as shown in Figure 8 c, a mask is opened
Mouth 66 is overlapping with 36 parts of capacitance hole simultaneously, and corresponding one described first supports opening 661 and one described second
Support opening 662 is overlapping with 36 parts of capacitance hole simultaneously, and capacitance exposed area S is between 20%~60%, mask
Opening diameter D is between 50nm~90nm.Preferably, the mask open 66 expose the capacitance hole 6 20%~
25% internal orifice dimension area.When the capacitance hole exposed area S be more than above range, can make the lower electrode layer 6 excessively remove, institute
It states lower electrode layer 6 to remove excessively, be easy to cause capacitance and collapse and short circuit, while capacity area can also reduce to reduce capacitance
Value, when the capacitance hole exposed area S is less than above range, being easy to cause the sacrificial layer can not completely remove, the sacrifice
Layer, which can not completely remove, also results in capacity area reduction, to make capacitance reduce；In addition, above-mentioned trepanning mode is relatively held
Easily, the sacrificial layer 3 is relatively easy to completely remove, while binding force is relatively strong between capacitance and capacitance, and capacitance is not easy to collapse.
Finally, as shown in the S5 and Figure 14 in Fig. 2, step 6), the inner surface in the lower electrode layer 6 and outer surface are carried out
Form capacitor dielectric layer 7, wherein the capacitor dielectric layer 7 covers the lower electrode layer 6, in the appearance of the capacitor dielectric layer 7
Face forms upper electrode layer 8, wherein the upper electrode layer 8 covers the capacitor dielectric layer 7.As an example, the capacitor dielectric layer 7
Material can select as high K dielectric material, to improve the capacitance of unit-area capacitance device, it includes by zirconium oxide
(ZrOx), hafnium oxide (HfOx), titanium Zirconium oxide (ZrTiOx), ruthenium-oxide (RuOx), antimony oxide (SbOx), aluminium oxide (AlOx)
At least one of group of composition is formed by lamination.The material of the upper electrode layer includes by polysilicon, titanium nitride, carbonization
At least one of the group of titanium and tungsten composition is formed by lamination.
Preferably, top electrode filled layer 9 is formed in the outer surface of the upper electrode layer 8, wherein the top electrode filled layer
The gap they 9 coverings the upper electrode layer 8 and be filled between the upper electrode layer 8.
As an example, as shown in figure 13, including capacitor area A in the semiconductor substrate 1, being used to form described two-sided
Capacitor arrangement further includes capacitor peripheral circuit area B in the semiconductor substrate 1, is used to form the double sided capacitor
Peripheral circuit.As shown in figure 14, after forming the double sided capacitor structure, photoresist layer 91 is formed in the capacitor area A,
Then the photoresist layer 91 etches the capacitor peripheral circuit area B, is etched to for protecting the capacitor area A
The only remaining semiconductor substrate 1 and the supporting layer 21 positioned at bottom.
Embodiment two
Incorporated by reference to embodiment one with continued reference to Figure 13, the present invention also provides a kind of double sided capacitor structures, wherein described double
Prepared by face capacitor arrangement preparation method preferably using the present invention, certainly, it is not limited to this, the array of capacitors structure
Including：
Semiconductor substrate 1；
Lower electrode layer 6 is formed in the semiconductor substrate 1, the cross sectional shape of the lower electrode layer 6 include it is U-shaped,
In, the height of 6 both sides of U-shaped lower electrode layer differs 110nm~180nm；
Capacitor dielectric layer 7 is covered in inner surface and the outer surface of the lower electrode layer 6；
Upper electrode layer 8 is covered in the outer surface of the capacitor dielectric layer 7.
As an example, the capacitance contact node (figure that the semiconductor substrate 1, which includes several, to be located in memory array structure
Do not show).
Specifically, in a concrete structure, the semiconductor substrate 1 further includes semiconductor base (not shown), semiconductor
Active area and wordline are set in substrate, bit line and capacitance contact node, the capacitance contact node electricity are set on semiconductor base
Property connects the transistor source etc. in the memory array structure.
As an example, the double sided capacitor structure further includes top support layer 23, middle support layer 22 and base layer support
Layer 21, is both formed in the semiconductor substrate 1 and connects the lower electrode layer 6, wherein the top support layer 23 connects institute
The mouth periphery of lower electrode layer 6 is stated, the middle support layer 22 connects the middle part of the lower electrode layer 6, the base layer support layer
21 are formed in 1 surface of the semiconductor substrate and connect the bottom periphery of the lower electrode layer 6.
The effect of the top support layer 23, middle support layer 22, base layer support layer 21 is to improve the capacitor
The mechanical strength of array.
Preferably, the material of the top support layer 23, middle support layer 22 and base layer support layer 21 include by silicon nitride,
One kind in the group of silicon oxynitride composition.
Preferably, as shown in figure 9d, the top support layer 23 has the first support opening 661, the lower electrode layer 6
20%~60% outer diameter area S portion is overlapped in the first support opening 661.
Preferably, as shown in figure 11, the middle support layer 22 has the second support opening 662, the lower electrode layer
20%~60% outer diameter area S portion is overlapped in described second and supports in 662 mouthfuls.
As an example, the array of capacitors structure further includes top electrode filled layer 9, the outer of the upper electrode layer 8 is covered
Surface, and the gap being filled between the upper electrode layer 8.
As an example, the material of the lower electrode layer 6 includes the group being made of polysilicon, titanium nitride, titanium carbide and tungsten
The material of one kind in group, the upper electrode layer 8 includes in the group being made of polysilicon, titanium nitride, titanium carbide and tungsten
The material of one kind, the capacitor dielectric layer 7 includes by zirconium oxide, hafnium oxide, titanium Zirconium oxide, ruthenium-oxide, antimony oxide, aluminium oxide
One kind in the group of composition.
Double sided capacitor structure proposed by the present invention, by controlling the height difference of U-shaped lower electrode layer both sides between 110nm
Between~180nm, can while effectively improving capacity area holding capacitor mechanical strength, ensure capacitance do not collapse.
In conclusion the double sided capacitor structure and preparation method thereof of the present invention, the preparation of the double sided capacitor structure
Method includes the following steps：1) semi-conductive substrate is provided, in forming laminated construction, the lamination knot in the semiconductor substrate
Structure includes alternately stacked supporting layer and sacrificial layer；2) in forming Patterned masking layer on the laminated construction, it is based on the figure
Shape mask layer etches multiple capacitance holes in the laminated construction；3) lower electricity is formed in the bottom in the capacitance hole and side wall
Pole layer, the supporting layer connect the lower electrode layer；4) in forming mask layer in the structure that step 3) obtains, it is based on the mask
Layer on the laminated construction in forming mask open, wherein the mask open exposes the 20%~60% of the capacitance hole
Internal orifice dimension area, and be based on the mask open, remove in the sacrificial layer and the mask open and be alternately laminated in institute
State the supporting layer on sacrificial layer, wherein the supporting layer for being located at bottom retains on the semiconductor substrate；5) in institute
The inner surface and outer surface for stating lower electrode layer form capacitor dielectric layer, wherein and the capacitor dielectric layer covers the lower electrode layer,
And upper electrode layer and the supporting layer are formed in the outer surface of the capacitor dielectric layer, wherein the upper electrode layer covers the electricity
Hold dielectric layer.The present invention uses different trepanning modes, by controlling capacitance perforated area to ensure what sacrificial layer completely removed
Excessive lower electrode layer is not lost again simultaneously, to ensure that capacitance is not easy to collapse while effectively improving capacity area, in addition
By using supporting layer etch gas source, ensure lower electrode layer loss in suitable range, to ensure the same of lower electrode layer area
When be completely removed sacrificial layer, density is closeer to being formed, and mechanical strength is stronger and the double sided capacitor of certifiable capacitance.Institute
With the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (21)
1. a kind of preparation method of double sided capacitor structure, which is characterized in that the preparation method of the double sided capacitor structure is extremely
Include the following steps less：
1) semi-conductive substrate is provided, in forming laminated construction in the semiconductor substrate, the laminated construction includes alternating layer
Folded supporting layer and sacrificial layer；
2) it in forming Patterned masking layer on the laminated construction, is carved in the laminated construction based on the Patterned masking layer
Lose multiple capacitance holes；
3) lower electrode layer is formed in the bottom in the capacitance hole and side wall, the supporting layer connects the lower electrode layer；
4) it in forming mask layer in the structure that step 3) obtains, is opened in formation mask on the laminated construction based on the mask layer
Mouthful, wherein the mask open exposes 20%~60% internal orifice dimension area in the capacitance hole；And it is opened based on the mask
Mouthful, it removes in the sacrificial layer and the mask open and is alternately laminated in the supporting layer on the sacrificial layer, wherein position
Retain on the semiconductor substrate in the supporting layer of bottom；
5) capacitor dielectric layer is formed in the inner surface of the lower electrode layer and outer surface, wherein the capacitor dielectric layer covers institute
Lower electrode layer is stated, and upper electrode layer is formed in the outer surface of the capacitor dielectric layer, wherein the upper electrode layer covers the electricity
Hold dielectric layer and the supporting layer.
2. the preparation method of double sided capacitor structure according to claim 1, it is characterised in that：The laminated construction includes
Base layer support layer, the first sacrificial layer, middle support layer, the second sacrificial layer and the top support layer being up laminated successively, it is described
The material of first sacrificial layer includes the silica of boron phosphorus doping, wherein first sacrificial layer includes upper straton sacrificial layer under
Straton sacrificial layer, and the phosphonium ion doping concentration of lower straton sacrificial layer is more than the phosphonium ion doping concentration of upper straton sacrificial layer, with
The etching of step 2) is improved to the etching power of first sacrificial layer, the quarter of the etching of step 2) to the lower straton sacrificial layer
Efficiency is lost higher than the etching efficiency to the upper straton sacrificial layer.
3. the preparation method of double sided capacitor structure according to claim 2, it is characterised in that：The lower straton sacrificial layer
Phosphonium ion content weight percent between 3%~5%, the weight percent of boron ion content between 2%~7% it
Between；The weight percent of the phosphonium ion content of the upper straton sacrificial layer is between 3%~5%, the weight of boron ion content
Percentage is between 5%~10%.
4. the preparation method of double sided capacitor structure according to claim 2, it is characterised in that：Step 4) includes following step
Suddenly：
4-1) in sequentially forming nitride mask layer, oxide mask layer, anti-reflecting layer and photoetching in the structure that step 3) obtains
Glue-line；
The anti-reflecting layer, the oxide mask layer and the nitride mask 4-2) are sequentially etched based on the photoresist layer
Layer, in forming the mask open on the laminated construction；
It 4-3) is based on the mask open, is open in forming the first support in the top support layer, it is sacrificial with exposure described second
Domestic animal layer；
It 4-4) is based on the first support opening, second sacrificial layer is removed using wet-etching technology；
4-5) in forming the second support opening in the middle support layer, with exposure first sacrificial layer；
It 4-6) is based on the second support opening, first sacrificial layer is removed using wet-etching technology.
5. the preparation method of double sided capacitor structure according to claim 4, it is characterised in that：Step 4-2) in, one
The mask open is overlapping with multiple capacitance bore portions simultaneously；Step 4-3) in, the first support opening is simultaneously
It is overlapping with multiple capacitance bore portions；Step 4-5) in, one it is described second support opening simultaneously with multiple capacitance holes
Part is overlapping.
6. the preparation method of double sided capacitor structure according to claim 5, it is characterised in that：One mask open
Overlapping with three capacitance bore portions simultaneously, the first support opening is handed over three capacitance bore portions simultaneously
Folded, the second support opening is overlapping with three capacitance bore portions simultaneously.
7. the preparation method of double sided capacitor structure according to claim 6, it is characterised in that：The mask open it is straight
Diameter is between 50nm~90nm.
8. the preparation method of double sided capacitor structure according to claim 4, it is characterised in that：Step 4-3) in, it uses
Top support layer described in dry etching is open with forming first support, and etch gas source includes chlorine, oxygen and argon gas, together
When, the lower electrode layer it is described first support opening in and it is described first support opening outside height difference 100nm~
150nm。
9. the preparation method of double sided capacitor structure according to claim 8, it is characterised in that：Step 4-5) in, it uses
Middle support layer described in dry etching is open with forming second support, and etch gas source includes chlorine, oxygen and argon gas, together
When, the lower electrode layer it is described second support opening in and it is described second support opening outside height difference 110nm~
180nm。
10. the preparation method of double sided capacitor structure according to claim 4, it is characterised in that：Step 4-4) in it is wet
Method etching solution includes 30%~60% hydrofluoric acid, step 4-6) in wet etching solution include 30%~60% hydrogen fluorine
Acid.
11. the preparation method of double sided capacitor structure according to claim 1, it is characterised in that：Step 2) includes as follows
Step：
2-1) in sequentially forming barrier in the structure that step 1) obtains；
2-2) in step 2-1) obtained structure upper edge first direction forms the first etched features using pitch multiplication process；
2-3) in step 2-2) use pitch multiplication process to form the second etched features in a second direction in obtained structure, to
Obtain the double-deck etched features, wherein the first direction has angle with second direction；
The region other than the double-deck etched features overlapping region 2-4) is etched, to form the Patterned masking layer.
12. the preparation method of double sided capacitor structure according to claim 11, it is characterised in that：The barrier
Include polysilicon barrier layer, barrier oxide layers and carbide barrier layer successively；And step 2-4) include the following steps：
The region other than the overlapping region of the double-deck etched features region 2-4-1) is etched, the array of capacitors is formed
Multiple windows of structure；
It 2-4-2) is sequentially etched the polysilicon barrier layer, barrier oxide layers and silicide barrier layer along the window, with shape
At the Patterned masking layer.
13. the preparation method of double sided capacitor array structure according to claim 12, it is characterised in that：The oxide
Barrier layer includes silica barrier layer.
14. the preparation method of double sided capacitor array structure according to claim 1, it is characterised in that：The supporting layer
Material include at least one of the group that is made of silicon nitride, silicon oxynitride, the material of the capacitor dielectric layer includes oxygen
Change at least one of zirconium, hafnium oxide, titanium Zirconium oxide, titanium oxide, ruthenium-oxide, antimony oxide, aluminium oxide group.
15. the preparation method of double sided capacitor structure according to claim 1, it is characterised in that：The semiconductor substrate
Upper includes capacitor area, is used to form the double sided capacitor structure, further includes capacitor periphery in the semiconductor substrate
Circuit region is used to form the double sided capacitor peripheral circuit, after forming the double sided capacitor structure, in the capacitor
Region forms photoresist layer, then the photoresist layer etches the capacitor periphery electricity for protecting the capacitor area
Road region is etched to and is only left the semiconductor substrate and the supporting layer positioned at bottom.
16. a kind of double sided capacitor structure, which is characterized in that including：
Semiconductor substrate；
Lower electrode layer is formed in the semiconductor substrate, and the cross sectional shape of the lower electrode layer includes U-shaped, wherein the U
The height of type lower electrode layer both sides differs 110nm~180nm；
Capacitor dielectric layer is covered in inner surface and the outer surface of the lower electrode layer；
Upper electrode layer is covered in the outer surface of the capacitor dielectric layer.
17. double sided capacitor structure according to claim 16, it is characterised in that：The double sided capacitor structure further includes
Top support layer, middle support layer and base layer support layer are both formed in the semiconductor substrate and connect the lower electrode layer,
Wherein, the top support layer connects the mouth periphery of the lower electrode layer, and the middle support layer connects the lower electrode layer
Middle part, the base layer support layer is formed in the bottom periphery of the semiconductor substrate surface and the connection lower electrode layer.
18. double sided capacitor structure according to claim 17, it is characterised in that：The top support layer has first
Mouth is strutted, 20%~60% outer diameter area S portion of the lower electrode layer is overlapped in the first support opening.
19. double sided capacitor structure according to claim 18, it is characterised in that：The middle support layer has second
Mouth is strutted, 20%~60% outer diameter area S portion of the lower electrode layer is overlapped in the second support opening.
20. double sided capacitor structure according to claim 17, it is characterised in that：It include capacitance in the semiconductor substrate
Device region is used to form the double sided capacitor structure, further includes capacitor peripheral circuit area in the semiconductor substrate, uses
In forming the double sided capacitor peripheral circuit, the capacitor peripheral circuit area includes the semiconductor substrate and the bottom
Layer supporting layer.
21. double sided capacitor structure according to claim 16, it is characterised in that：The double sided capacitor structure further includes
Top electrode filled layer, the gap for covering the outer surface of the upper electrode layer, and being filled between the upper electrode layer.
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