CN108155152B - Conductor structure, capacitor array structure and preparation method - Google Patents

Abstract

The invention provides a conductor structure, a capacitor array structure and a preparation method based on a polysilicon manufacturing process. Preparation of the conductor structure includes: providing a substrate, forming a cavity structure in the substrate; forming a conductor filling structure in the cavity structure to form a conductor filling structure The material source at least includes a silicon source and a germanium source. The germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source to increase the silicon crystal grain size in the conductor filling structure. Through the above solution, the present invention proposes a method for manufacturing large-grained polysilicon. It introduces crystal nucleation elements, such as germanium, which serve as the aggregation and growth of silicon grains, to aggregate silicon atoms and thereby increase the crystal grain size. Increasing the polycrystalline silicon crystal grain size can reduce grain boundaries. The influence of traps on carriers further increases the conductivity. The present invention also prevents the influence of germanium in the conductor filling structure on the manufacturing process through the setting of a protective layer, thereby achieving an effective connection between the conductor filling structure and other structural layers, further improving the Electrical properties of conductor-filled structures.

Description

Conductor structure, capacitor array structure and preparation method

technical field

The invention belongs to the field of semiconductor devices and manufacturing, and in particular relates to a conductor structure based on a polysilicon process, a capacitor array structure and a preparation method.

Background technique

Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. At present, in the DRAM process below 20nm, the DRAM adopts a stacked capacitor structure, and its capacitor (Capacitor) is a vertical cylinder with a high aspect ratio to increase the surface area.

At present, the polysilicon process is one of the processes that have been widely used in semiconductors, wherein the grain size of polysilicon is one of the important parameters affecting device performance. Generally speaking, the crystal grain size can be directly adjusted by changing the reaction temperature and pressure. However, these process conditions may also affect the electrical properties of the components in the previous process. With the size reduction and performance enhancement, the polysilicon process must be carried out. Optimized to meet the latest process requirements. At the same time, in the current process, doped polysilicon is often used in the production of structures such as wires. The smaller the grain size of polysilicon, the higher the grain boundary density. It will be affected by the grain boundary trap (grain boundary trap) and reduce the conductivity.

Therefore, how to provide a polysilicon process-based conductor structure, capacitor array structure and their respective preparation methods to solve the limitations of improving the polysilicon crystal grain size in the prior art and the increase in electrical conductivity caused by too small polysilicon crystal grains is necessary. .

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a conductor structure based on polysilicon process, a capacitor array structure and their respective preparation methods, which are used to solve the limitations of improving polysilicon crystal grain size and polysilicon crystallization in the prior art. Problems such as increased conductivity caused by too small particle size.

In order to achieve the above object and other related objects, the present invention provides a method for preparing a conductor structure based on a polysilicon process, comprising the following steps:

1) providing a substrate in which a cavity structure is formed; and

2) A conductor filling structure is formed in the cavity structure, and the material source for forming the conductor filling structure includes at least a silicon source and a germanium source, wherein the germanium atoms in the germanium source are used as the silicon atoms in the silicon source The grown crystal nuclei are gathered to increase the silicon crystal grain size in the formed conductor filling structure.

As a preferred solution of the present invention, in step 2), the conductor filling structure includes a hole-filling conductive layer and a gap compartment, wherein the gap compartment is formed by the gap between polysilicon in the hole-filling conductive layer, and The hole-filling conductive layer covers the gap compartment.

As a preferred solution of the present invention, the hole-filling conductive layer is filled in the cavity structure and also extends to cover the upper surface of the substrate around the cavity structure, and the gap compartment is located by the cavity structure. within the hole-filling conductive layer defined by the hole structure.

As a preferred solution of the present invention, the thickness of the portion of the hole-filling conductive layer located on the upper surface of the substrate is between 120-800 angstroms.

As a preferred solution of the present invention, the upper surface of the hole-filling conductive layer corresponding to the top of the gap chamber has a high point and a low point formed by stacking polysilicon, and the high point is 80~ 300 Angstroms.

As a preferred solution of the present invention, the silicon crystal grain size in the conductor filling structure described in step 2) is between 50-1500 angstroms.

As a preferred solution of the present invention, the weight percentage of germanium in the conductor filling structure is between 10% and 80%.

As a preferred solution of the present invention, the temperature for forming the conductor filling structure is between 350-450° C., and the pressure for forming the conductor filling structure is between 250-900 millitorr.

The present invention also provides a method for preparing a capacitor structure array, comprising the following steps:

1) A semiconductor substrate is provided, the semiconductor substrate includes a plurality of capacitive contact nodes located in the memory array structure, and alternately stacked sacrificial layers and supporting layers are formed on the semiconductor substrate;

2) forming a patterned mask layer with windows arranged in an array on the structure obtained in step 1), and etching the sacrificial layer and the supporting layer based on the patterned mask layer to form a a capacitive hole corresponding to the window, the capacitive hole exposing the capacitive contact node;

3) forming a lower electrode layer on the bottom and sidewalls of the capacitor hole, and removing the sacrificial layer to expose the outer surface of the lower electrode layer;

4) forming a capacitor dielectric layer on the inner surface and exposed outer surface of the lower electrode layer, and forming an upper electrode layer on the surface of the capacitor dielectric layer;

5) forming a conductor filling structure on the surface of the upper electrode layer, the conductor filling structure fills the gap between the inner walls of the lower electrode layer and the outer surfaces of the adjacent lower electrode layers and extends to cover the The above-mentioned upper electrode layer, wherein, the material source for forming the conductor filling structure includes at least a silicon source and a germanium source, and the germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the formation of Silicon grain size in said conductor-filled structure; and

6) Forming an upper electrode covering layer on the surface of the conductor filling structure.

As a preferred solution of the present invention, in step 5), the conductor filling structure includes a hole-filling conductive layer and a gap compartment, wherein the gap compartment is defined by the capacitance hole of the hole-filling conductive layer. The gap between the polysilicon is formed, and the hole-filling conductive layer covers the gap chamber.

As a preferred solution of the present invention, the upper surface of the hole-filling conductive layer is 120-800 angstroms higher than the upper surface of the upper electrode layer above the top of the lower electrode layer.

As a preferred solution of the present invention, at least one of the upper surface of the hole-filling conductive layer corresponding to the top of the gap chamber and the upper surface of the hole-filling conductive layer has a high point formed by stacking polysilicon and the low point, and the high point is 80-300 Angstroms higher than the low point.

As a preferred solution of the present invention, in step 5), the weight percentage of germanium in the conductor filling structure is between 10% and 80%.

As a preferred solution of the present invention, in step 5), the silicon crystal grain size in the conductor filling structure is between 50 and 1500 angstroms; the temperature for forming the conductor filling structure is between 350 and 450°C, forming The pressure of the conductor filling structure is between 250-900 millitorr.

As a preferred solution of the present invention, in step 1), the number of the support layer is three layers, including the top support layer, the middle support layer and the bottom support layer, and the number of the sacrificial layer is two layers, including the The first sacrificial layer between the top supporting layer and the middle supporting layer and the second sacrificial layer between the bottom supporting layer and the middle supporting layer; in step 3), the step of removing the sacrificial layer includes :

3-1) forming a first opening in the top support layer to expose the first sacrificial layer on the lower surface thereof;

3-2) removing the first sacrificial layer by using a wet etching process based on the first opening;

3-3) forming a second opening in the intermediate support layer to expose the second sacrificial layer on the lower surface thereof;

3-4) Based on the second opening, remove the second sacrificial layer by using a wet etching process

As a preferred solution of the present invention, in step 3-1), one first opening only overlaps one capacitor hole, or one first opening overlaps multiple capacitor holes at the same time; In step 3-3), one second opening only overlaps one capacitor hole, or one second opening overlaps multiple capacitor holes at the same time.

As a preferred solution of the present invention, step 5) also includes the step of doping the conductor filling structure, and the doping element is selected from any one of boron, phosphorus and arsenic; after step 6), It also includes the step of forming an oxide layer on the surface of the upper electrode covering layer.

As a preferred solution of the present invention, step 5) and step 6) further include a step: forming a protective layer on the surface of the conductor filling structure, the protective layer is used to prevent germanium in the conductor filling structure from Influence of subsequent manufacturing process, wherein, the material of the protective layer includes boron-doped polysilicon.

As a preferred solution of the present invention, the conductor filling structure and the protective layer are prepared in the same reaction chamber _; the germanium source gas forming the conductor filling structure includes at least one of _GeH4 and _Ge2H6 , The silicon source gas for forming the conductor filling structure includes at least one of SiH ₄ , Si ₂ H ₆ and SiH ₆ Cl; the silicon source gas for forming the protective layer includes SiH ₄ , Si ₂ H ₆ and SiH ₆ Cl The boron source gas for forming the protective layer includes at least one of BCl ₃ and B ₂ H ₆ ; wherein, the temperature for forming the protective layer is between 300°C and 500°C, and the pressure is between 200 ˜900 mTorr, and the thickness of the formed protective layer is 400˜1500 angstroms.

The present invention also provides a conductor structure based on polysilicon process, including:

a substrate having a cavity structure formed therein; and

The conductor filling structure is located in the cavity structure, and the material source forming the conductor filling structure includes at least a silicon source and a germanium source, wherein the germanium atoms in the germanium source are gathered as silicon atoms in the silicon source growing crystal nuclei to increase the grain size of silicon crystals in the conductor filling structure.

As a preferred solution of the present invention, the conductor filling structure includes a hole-filling conductive layer and a gap chamber, wherein the gap chamber is formed by the gap between polysilicon in the hole-filling conductive layer, and the hole-filling conductive layer A layer wraps the interstitial chamber.

As a preferred solution of the present invention, the hole-filling conductive layer is filled in the groove structure and also extends to cover the upper surface of the substrate around the groove structure, and the gap compartment is located by the groove structure. In the hole-filling conductive layer defined by the groove structure; the thickness of the hole-filling conductive layer located on the upper surface of the substrate is between 120-800 angstroms.

As a preferred solution of the present invention, the conductor filling structure further has a doping element, and the doping element is formed from any one of boron, phosphorus and arsenic.

As a preferred solution of the present invention, the weight percentage of germanium in the conductor filling structure is between 10% and 80%; the upper surface of the hole-filling conductive layer corresponding to the top of the gap chamber is made of silicon The high point and the low point formed by grain accumulation, the high point is 80-300 angstroms higher than the low point; the silicon crystal grain size in the conductor filling structure is between 50-1500 angstroms.

The present invention also provides a capacitor array structure, including:

a semiconductor substrate comprising a plurality of capacitive contact nodes in a memory array structure;

a lower electrode layer bonded to the capacitive contact node, and the cross-sectional shape of the lower electrode layer includes a U shape;

a capacitor dielectric layer covering the inner and outer surfaces of the lower electrode layer;

an upper electrode layer covering the surface of the capacitor dielectric layer;

The conductor filling structure fills the gap between the inner side walls of the lower electrode layer and the outer surfaces of the adjacent lower electrode layers and extends to cover the upper electrode layer, wherein the material forming the conductor filling structure The source includes at least a silicon source and a germanium source, and the germanium atoms in the germanium source are used as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the silicon crystal grain size in the conductor filling structure; and

The upper electrode covering layer covers the surface of the conductor filling structure.

As a preferred solution of the present invention, the conductor filling structure includes a hole-filling conductive layer and a gap compartment, wherein the gap compartment is a gap between polysilicon of the hole-filling conductive layer defined by the capacitor hole constituted, and the hole-filling conductive layer covers the gap compartment.

As a preferred solution of the present invention, the upper surface of the hole-filling conductive layer is 120-800 angstroms higher than the upper surface of the upper electrode layer above the top of the lower electrode layer; the hole-filling conductive layer At least one of the surface exposed to the interstitial chamber and the upper surface of the hole-filled conductive layer has a high point and a low point formed by a stack of silicon grains, and the high point is higher than the low point 80-300 Angstroms.

As a preferred solution of the present invention, the weight percentage of germanium in the conductor filling structure is between 10% and 80%; the silicon crystal grain size of the conductor filling structure is between 50 and 1500 angstroms.

As a preferred solution of the present invention, the conductor filling structure also has a doping element, the doping element is selected from any one of boron, phosphorus and arsenic; the surface of the upper electrode covering layer is also formed with oxide layer.

As a preferred solution of the present invention, a protective layer is also formed between the conductor filling structure and the upper electrode covering layer, and the protection layer is used to prevent the influence of germanium in the conductor filling structure on subsequent manufacturing processes, Wherein, the material of the protection layer includes boron-doped polysilicon.

As mentioned above, the conductor structure, capacitor array structure and respective preparation methods based on the polysilicon process of the present invention have the following beneficial effects:

In the conductor structure and preparation of the present invention, a method of manufacturing large grain size doped polysilicon is proposed, and a crystal nucleus element, such as germanium element, is introduced as a silicon crystal grain to aggregate and grow, and germanium atoms are doped in polysilicon It can help the growth of polysilicon grains. Germanium atoms can achieve the effect similar to silicon crystal nuclei in doped polysilicon, so that silicon atoms can gather and then increase the crystal grain size. Increasing the crystal grain size of polysilicon can reduce the grain boundary trap (grain boundary trap) to the carrier The influence of (carrier) increases the conductivity, that is, reduces the grain boundary density and improves the conductivity. The above method can be applied to various wires made of polysilicon, such as a capacitor structure. In addition, the present invention also prevents the influence of germanium in the conductor filling structure on the process through the setting of the protective layer, and achieves the conductor filling structure. The effective connection with other structural layers, and the introduction of doping elements, etc., further improve the electrical performance of the conductor filling structure.

Description of drawings

FIG. 1 shows a flow chart of the preparation process of a conductor structure based on a polysilicon process provided by the present invention.

FIG. 2 shows a schematic structural view of a substrate provided for the preparation of the conductor structure of the present invention.

FIG. 3 is a schematic diagram of forming a cavity structure in a substrate during the preparation of the conductor structure of the present invention.

FIG. 4 is a schematic diagram of forming a conductor filling structure in the preparation of the conductor structure of the present invention.

Fig. 5 shows a flow chart of the preparation process of the capacitor array structure provided by the present invention.

FIG. 6 shows a schematic structural view of a semiconductor substrate provided for the preparation of the capacitor array structure of the present invention.

FIG. 7 is a schematic diagram of forming alternately stacked sacrificial layers and supporting layers in the preparation of the capacitor array structure of the present invention.

FIG. 8 is a schematic structural diagram of forming a patterned mask layer in the preparation of the capacitor array structure of the present invention.

FIG. 9 is a schematic diagram of the structure of capacitor holes formed in the preparation of the capacitor array structure of the present invention.

FIG. 10 is a schematic diagram showing the structure of the lower electrode layer formed in the preparation of the capacitor array structure of the present invention.

FIG. 11 is a top view of the first opening formed in the preparation of the capacitor array structure of the present invention.

FIG. 12 is a schematic cross-sectional view of the first opening formed in the preparation of the capacitor array structure of the present invention.

Fig. 13 is a schematic diagram of the structure after removing the first sacrificial layer at the section A-A' in Fig. 11 .

Fig. 14 is a schematic view of the structure after the second opening is formed on the section A-A' in Fig. 11 .

Fig. 15 is a schematic diagram of the structure after removing the second sacrificial layer at the section A-A' in Fig. 11 .

FIG. 16 is a schematic structural diagram of forming a capacitor dielectric layer in the preparation of the capacitor array structure of the present invention.

FIG. 17 is a schematic diagram showing the structure of the upper electrode layer formed in the preparation of the capacitor array structure of the present invention.

FIG. 18 is a schematic structural diagram of forming a conductor filling structure in the preparation of the capacitor array structure of the present invention.

FIG. 19 is a partially enlarged schematic diagram of a dotted box in FIG. 18 .

FIG. 20 is a partially enlarged schematic diagram of the dotted line box B in FIG. 18 .

FIG. 21 is a schematic diagram showing the structure of the protective layer formed in the preparation of the capacitor array structure of the present invention.

FIG. 22 is a schematic structural diagram of forming the upper electrode covering layer in the preparation of the capacitor array structure of the present invention.

Fig. 23 is a schematic structural view of the section A-B in Fig. 22 .

FIG. 24 is a partial enlarged view of the dotted box in FIG. 22 .

FIG. 25 is a schematic diagram showing the structure of the oxide layer formed in the preparation of the capacitor array structure of the present invention.

Component designation description

100 semiconductor substrate

101 capacitive contact node

102 Bottom support layer

103 The second sacrificial layer

104 middle support layer

105 The first sacrificial layer

106 top support layer

107 Patterned mask layer

108 windows

109 capacitor hole

110 lower electrode layer

111 opening

1111 First opening

1112 Second opening

112 capacitor dielectric layer

113 upper electrode layer

114 hole-filled conductive layer

115 Interstitial bin

116 Conductor fill structure

117 protective layer

118 Upper Electrode Covering Layer

119 oxide layer

200 basis

201 Pocket structure

202 conductor filled structure

203 hole-filled conductive layer

204 Interstitial warehouse

S1～S6 Step 1)～Step 6)

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 25. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the layout of the components may also be more complex.

Embodiment one:

As shown in Figures 1 to 4, the present invention provides a method for preparing a conductor structure based on a polysilicon process, comprising the following steps:

First, as shown in S1 in FIG. 1 and FIGS. 2-3 , step 1) is performed to provide a substrate 200 and form a cavity structure 201 in the substrate 200 .

Specifically, this step provides a structural basis for subsequent formation of a conductor filling structure, wherein the substrate 200 can be a single material layer, such as a silicon material layer, a silicon-on-insulator material layer, a germanium material layer, and an insulating dielectric layer (such as silicon oxide Layer) and the like are used to open trenches therein and form a conductor-filled structure as a metal connection line. Of course, the substrate 200 can also be any semiconductor stacked structure, and it is necessary to open a cavity therein for preparing a conductor-filled structure, so as to realize The role of conduction or connection is set according to the actual production and R&D requirements, and no specific limitation is set here.

In addition, the cavity structure 201 here is not limited to the U-shaped groove structure shown in the figure, but can also be any structure with an opening, a bottom, and a side wall, such as an inverted trapezoid, a square groove, etc., as long as it can be deposited The conductor filling structure is enough, and it can also be a through hole penetrating up and down, and its cross-sectional shape can be irregular, such as having a curved side wall, etc., which is not specifically limited here.

Next, as shown in S2 and FIG. 4 in FIG. 1, step 2) is performed to form a conductor filling structure 202 in the cavity structure 201, and the material source for forming the conductor filling structure 202 includes at least silicon source and germanium source, wherein the germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the silicon crystal grain size in the conductor filling structure.

Specifically, this step is aimed at forming a conductor filling structure 202 with high conductivity. In the present application, during the formation of the conductor filling structure, crystal nucleus elements are introduced to act as crystal nuclei for polysilicon crystal grains to aggregate and grow, thereby effectively increasing the The grain size of polysilicon, such as doping germanium (Ge) atoms in polysilicon can help the growth of polysilicon grains, germanium atoms in polysilicon can achieve the effect similar to the silicon nucleus, so that silicon atoms can gather to increase the crystal grain size, increase The crystal grain size of polysilicon can reduce the influence of grain boundary traps on carriers (carriers) and thus increase the conductivity, the process is simple and the cost is low, wherein the formed conductor filling structure 202 is located in the cavity structure 201 The inside of the cavity structure can be filled completely, located on the side wall and bottom thereof, or not completely filled in the cavity structure, and of course, the material layer around the cavity structure can also be covered at the same time. In addition, the silicon crystal grain size here is well known to those of ordinary skill in the art, for example, it may be the size of the formed silicon crystal grains, such as being characterized by the diameter of the silicon crystal grains and the like.

As an example, in step 2), the conductor filling structure 202 includes a hole-filling conductive layer 203 and a gap bin 204, wherein the gap bin 204 is formed by the gap between the polysilicon of the hole-filling conductive layer 203, and the The hole-filling conductive layer 203 covers the gap compartment 204 .

Specifically, in one example, as shown in FIG. 4, the conductor filling structure 202 includes a hole-filling conductive layer 203 and a gap chamber 204. Under the process conditions set in this embodiment, the surface of the conductor filling structure is rough. , wherein, during the deposition process of forming the conductor filling structure 202, the deposition material starts to form along the bottom and sidewall of the cavity structure, due to the large crystal grain size, the relative deposition material layer is gradually deposited close, and its relative surface surrounds Form a gap bin 204 to form a conductor filling structure 202 including a hole-filling conductive layer 204 and a gap bin 204. In addition, the existence of the gap bin 204 can also relieve the stress and strain between the material layers on the periphery of the gap bin, preventing The thermal expansion and compression of the various material layers, etc., thereby protecting the overall device structure.

As an example, the hole-filling conductive layer 203 is filled in the cavity structure 201 and extends to cover the upper surface of the substrate 200 around the cavity structure 201, and the gap chamber 204 is located by the cavity structure. 201 defined in the hole-filling conductive layer 203 .

Specifically, in another example, the conductor filling structure 202 is also formed on the upper surface of the substrate 200 around the cavity structure 201, wherein the conductor filling structure 202 includes a hole-filling conductive layer 203 and a spacer 204, and the gap compartment 204 is preferably formed in the hole-filling conductive layer defined by the groove of the cavity structure, and the gap compartment is not formed in the hole-filling conductive layer on the upper surface of the substrate.

As an example, the thickness of the hole-filling conductive layer 203 located on the upper surface of the substrate is between 120-800 angstroms.

As an example, the upper surface of the hole-filling conductive layer 203 corresponding to the top of the gap chamber 204 has a high point and a low point formed by stacking polysilicon, and the high point is 80-300 angstroms higher than the low point, as shown in D2 in Figure 4.

As an example, the surface of the hole-filling conductive layer 203 exposed on the gap chamber 204 has a high point and a low point formed by stacking silicon grains, and the high point is 80-300 angstroms higher than the low point, as shown in D1 in Figure 4.

As an example, in step 2), the grain size of silicon in the conductor filling structure 202 is between 50-1500 angstroms.

Specifically, for the thickness of the hole-filling conductive layer 203, the thickness of the upper surface portion of the substrate 200 is controlled to be 120-800 angstroms, wherein the crystal grain size in the conductor filling structure 202 can be increased as the film thickness at this position increases. increase, but if it is too thick, the flatness of the surface will become too poor, which will affect the subsequent manufacturing process. Therefore, the thickness is preferably 200 to 600 angstroms, and 500 angstroms is selected in this embodiment, so that good electrical properties can be obtained, and there is The conductor filling structure is beneficial to the subsequent process.

Further, by adopting the method in this example, the silicon crystal grain size in the formed conductor filling structure 202 is about 50-1500 angstroms, preferably 500-1000 angstroms, and about 800±10 angstroms of silicon grains are formed in this embodiment. grain.

In addition, in this example, the exposed position of the conductor filling structure 202, such as the hole-filling conductive layer 203 exposed on the surface of the part of the gap chamber 204, the hole-filling conductive layer 203 is located on the substrate 200 The surface of part of the surface, as shown in D3 in Figure 4, will form a high point and a low point of crystal grain accumulation. In this example, it is preferable that the highest point of the exposed position is the high point, and the lowest point of the exposed position is the low point, wherein the highest and lowest are relative to the structure on which it is deposited, such as the sidewall of the cavity structure, the bottom of the cavity structure and the upper surface of the substrate, wherein the high point is higher than The difference between the low points, as shown by the distances D1 to D3 in Figure 4, is preferably 100 to 200 angstroms, and is selected as 150 angstroms in this example, which can contribute to the improvement of the electrical performance of the conductor filling structure. Improve and facilitate the formation of the appropriate size of the gap compartment, and similarly, the upper surface of the hole-filling conductive layer 203 corresponding to the top of the gap compartment 204 will also form such a structure due to the large silicon crystal grain size.

As an example, the weight percentage of germanium in the conductor filling structure 202 is between 10% and 80%.

As an example, the temperature for forming the conductor filling structure 202 is between 350-450° C., and the pressure for forming the conductor filling structure 202 is between 250-900 mTorr.

Specifically, in the formation of the conductor filling structure of this embodiment, a chemical vapor deposition process can be used, and the structure obtained in step 1) is placed in the low-pressure chemical vapor deposition furnace tube; The silicon source gas and the germanium source gas are reacted to form a conductor filling structure at the bottom, the side wall of the trench structure or at the same time on the upper surface of the substrate, wherein the silicon source gas is selected from SiH ₄ , Si ₂ H ₆ , SiH At least one of ₆ Cl, the germanium source gas is selected from at least one of GeH ₄ and Ge ₂ H ₆ , and the temperature for forming the conductor filling structure 202 is preferably 380°C to 420°C, in this example, 400°C , the corresponding matching pressure range includes 250-450mT (mTorr), and in this example, 300±10mT is selected. Adjusting the reaction temperature and pressure will further adjust the size of the silicon crystal grain size and the structure of the interstitial chamber in the conductor filling structure.

In addition, it should be noted that the doping ratio of germanium should be further adjusted, preferably between 40% and 60%, so that the deposition process can be further adjusted by the ratio of germanium under the condition that only silicon source and germanium source exist. The ratio of the existing crystal nuclei provided can obtain better silicon atom deposition and the optimal ratio of germanium atoms as crystal nuclei to obtain a reasonable silicon crystal grain size. In this example, the ratio of germanium is selected as 50%.

In addition, when the conductor filling structure is formed, it also includes the step of doping it, such as feeding at least one of boron source gas, phosphorus source gas and arsenic source gas, so as to further optimize the conductor Electrical properties of filled structures.

As shown in Figure 4, the present invention also provides a conductor structure based on polysilicon process, wherein, the conductor structure is preferably prepared by the method for preparing the conductor structure provided by the present invention, of course, other embodiments can also be used The method is not limited thereto, and the conductor structure includes:

a substrate 200 in which a cavity structure 201 is formed; and

The conductor filling structure 202 is located in the cavity structure 201, and the material source forming the conductor filling structure 202 includes at least a silicon source and a germanium source, wherein the germanium atoms in the germanium source are used as the silicon in the silicon source Atoms aggregate the grown crystal nuclei to increase the silicon crystal grain size in the conductor filling structure 202 .

Specifically, the substrate 200 can be a single material layer, such as a silicon material layer, a silicon-on-insulator material layer, a germanium material layer, and an insulating dielectric layer (such as a silicon oxide layer) for opening trenches therein and forming conductor filling. The structure is used as a metal connection line. Of course, the substrate 200 can also be any semiconductor stacked structure, and it is necessary to open a groove in it to prepare a conductor filling structure to realize the function of conduction or connection, and it is set according to the actual production and development requirements. No specific limitation is made here.

In addition, the cavity structure 201 here is not limited to the U-shaped groove structure shown in the figure, and can also be any structure with an opening, a bottom, and a side wall, as long as the conductor filling structure can be deposited, and it can also be The cross-sectional shape of the through hole penetrating up and down may be irregular, such as having a curved side wall, etc., which is not specifically limited here.

Specifically, the present application introduces crystal nuclei elements in the formation process of wires to act on the nuclei of polysilicon crystal grains to gather and grow, thereby effectively increasing the polysilicon crystal grain size, such as doping germanium (Ge) atoms in polysilicon can help Polysilicon grains grow, and germanium atoms in doped polysilicon can achieve the effect similar to silicon crystal nuclei, so that silicon atoms gather and then increase the crystal grain size. Increasing the polysilicon crystal grain size can reduce the grain boundary trap (grain boundary trap) to the carrier (carrier) ) and then increase the conductivity, the process is simple and the cost is low. Wherein, the formed conductor filling structure 202 is located in the cavity structure 201, can fill the cavity structure completely, be located at its side wall and bottom, also can not completely fill the cavity structure, and of course can simultaneously A layer of material covering the surroundings of the cavity structure.

As an example, the conductor filling structure 202 includes a hole-filling conductive layer 203 and a gap chamber 204, wherein the gap chamber 204 is formed by the gap between the polysilicon of the hole-filling conductive layer 203, and the hole-filling conductive layer 203 covers the gap chamber 204 .

As an example, the hole-filling conductive layer 203 is filled in the cavity structure 201 and extends to cover the upper surface of the substrate 200 around the cavity structure 201, and the gap chamber 204 is located by the cavity structure. In the hole-filling conductive layer 203 defined by 201; the thickness of the hole-filling conductive layer 203 located on the upper surface of the substrate is between 120-800 angstroms.

Specifically, in one example, as shown in FIG. 4, the conductor filling structure 202 includes a hole-filling conductive layer 203 and a gap chamber 204. Under the process conditions set in this embodiment, the surface of the conductor filling structure is rough. , wherein, during the deposition process of forming the conductor filling structure 204, the deposition material begins to form along the bottom and sidewalls of the trench structure, due to the large crystal grain size, the relative deposition material layer is gradually deposited close, and its relative surface surrounds A gap bin 204 is formed to form a conductor filling structure 202 including a hole-filling conductive layer 204 and a gap bin 204. The existence of the gap bin 204 can also relieve the stress and strain between the material layers on the periphery of the gap bin, preventing each material The thermal expansion and extrusion of layers, etc., thereby protecting the overall device structure.

Specifically, in another example, the conductor filling structure 202 is also formed on the upper surface of the substrate 200 around the cavity structure 201, wherein the conductor filling structure 202 includes a hole-filling conductive layer 203 and a spacer 204, and the gap compartment 204 is preferably formed in the hole-filling conductive layer defined by the groove of the cavity structure, and the gap compartment is not formed in the hole-filling conductive layer on the upper surface of the substrate.

As an example, the weight percentage of germanium in the conductor filling structure 202 is between 10% and 80%.

As an example, the upper surface of the hole-filling conductive layer 203 corresponding to the top of the gap chamber 204 has a high point and a low point formed by stacking polysilicon, and the high point is 80-300 angstroms higher than the low point, as shown in D1 in Figure 4.

As an example, the surface of the hole-filling conductive layer 203 exposed on the gap chamber 204 has high points and low points formed by stacking silicon grains, and the high points are 80-300 angstroms higher than the low points, as shown in FIG. As shown in D1 in 4; the silicon crystal grain size of the conductor filling structure 202 is between 50-1500 angstroms.

As an example, the upper surface of the hole-filling conductive layer 203 corresponding to the top of the gap chamber 204 has a high point and a low point formed by stacking polysilicon, and the high point is 80-300 angstroms higher than the low point, as shown in D2 in Figure 4.

Specifically, for the thickness of the hole-filling conductive layer 203, the thickness of the upper surface portion of the substrate 200 is controlled to be 120-800 angstroms, wherein the crystal grain size in the conductor filling structure 202 can be increased as the film thickness at this position increases. increase, but if it is too thick, the flatness of the surface will become too poor, which will affect the subsequent manufacturing process. Therefore, the thickness is preferably 200 to 600 angstroms, and 500 angstroms is selected in this embodiment, so that good electrical properties can be obtained, and there is The conductor filling structure is beneficial to the subsequent process.

Further, by adopting the method in this example, the silicon crystal grain size in the formed conductor filling structure 202 is about 50-1500 angstroms, preferably 500-1000 angstroms.

In addition, in this example, the exposed position of the conductor filling structure 202, such as the hole-filling conductive layer 203 exposed on the surface of the part of the gap chamber 204, the hole-filling conductive layer 203 is located on the substrate 200 The surface of the part of the surface will form a high point and a low point of crystal grain accumulation, as shown in D3 in Figure 4, in this example, preferably the highest point of the exposed position is the high point, and the lowest point of the exposed position is the low point, wherein the highest and lowest are relative to the structure on which it is deposited, such as the sidewall of the cavity structure, the bottom of the cavity structure and the upper surface of the substrate, wherein the high point is higher than The difference between the low points, as shown in the distances D1-D3 in Figure 4, the height difference is preferably 100-200 angstroms, and in this example, 150±10 angstroms is selected, which can contribute to the electrical conductivity of the conductor filling structure. The improvement of the performance helps to form the appropriate size of the gap chamber. Similarly, the upper surface of the hole-filling conductive layer 203 corresponding to the top of the gap chamber 204 will also form such a structure due to the large silicon crystal grain size.

In addition, it should be noted that the doping ratio of germanium should be further adjusted, preferably between 40% and 60%, so that the deposition process can be further adjusted by the ratio of germanium under the condition that only silicon source and germanium source exist. The ratio of the existing crystal nuclei provided can obtain better silicon atom deposition and the optimal ratio of germanium atoms as crystal nuclei to obtain a reasonable silicon crystal grain size. In this example, the ratio of germanium is selected as 50%.

As an example, the conductor filling structure 202 further has a doping element, and the doping element is formed from any one of boron, phosphorus and arsenic.

Specifically, at least one of boron source gas, phosphorus source gas, and arsenic source gas may be injected while the conductor filling structure is being formed, so as to further optimize the electrical performance of the conductor filling structure.

Embodiment two:

As shown in Figure 5, the present invention also provides a method for preparing a capacitor structure array, wherein the preparation of the capacitor structure array in the second embodiment includes the preparation of the conductor structure based on the polysilicon process in the first embodiment, including the steps :

1) A semiconductor substrate is provided, the semiconductor substrate includes a plurality of capacitive contact nodes located in the memory array structure, and alternately stacked sacrificial layers and support layers are formed on the semiconductor substrate;

2) forming a patterned mask layer with windows arranged in an array on the structure obtained in step 1), and etching the sacrificial layer and the supporting layer based on the patterned mask layer to form a a capacitive hole corresponding to the window, the capacitive hole exposing the capacitive contact node;

3) forming a lower electrode layer on the bottom and sidewalls of the capacitor hole, and removing the sacrificial layer to expose the outer surface of the lower electrode layer;

4) forming a capacitor dielectric layer on the inner surface and exposed outer surface of the lower electrode layer, and forming an upper electrode layer on the surface of the capacitor dielectric layer;

5) forming a conductor filling structure on the surface of the upper electrode layer, the conductor filling structure fills the gap between the inner walls of the lower electrode layer and the outer surfaces of the adjacent lower electrode layers and extends to cover the The above-mentioned upper electrode layer, wherein, the material source for forming the conductor filling structure includes at least a silicon source and a germanium source, and the germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the formation of Silicon grain size in said conductor-filled structure; and

6) Forming an upper electrode covering layer on the surface of the conductor filling structure.

The method for preparing the capacitor array structure of the present invention will be described in detail below with reference to the accompanying drawings.

First, as shown in S1 in FIG. 5 and FIGS. 6-7, step 1) is performed, a semiconductor substrate 100 is provided, and alternately stacked sacrificial layers are formed on the semiconductor substrate 100, such as 103, 105, And supporting layers, such as 102, 104, 106.

As an example, in step 1), the semiconductor substrate 100 includes several capacitive contact nodes 101 located in a memory array structure.

Specifically, in a specific structure, the substrate 100 further includes a semiconductor substrate (not shown in the figure), an active region and a word line are arranged in the semiconductor substrate, and a bit line and the capacitor contact node 101 are arranged on the semiconductor substrate. , the capacitor contact node 101 is electrically connected to the source of the transistor in the memory array structure and the like.

In addition, the capacitive contact nodes 101 may be arranged in a hexagonal array, which corresponds to the arrangement of capacitors manufactured later. And the capacitor contact nodes 101 are isolated by a spacer layer, and the material of the spacer layer can be any one of silicon nitride (SiN), silicon oxide (SiO ₂ ), and aluminum oxide (Al ₂ O ₃ ). Or any combination of two or more. In this embodiment, the material of the spacer layer is selected as SiN.

As an example, in step 1), the number of the support layers formed is greater than the number of the sacrificial layers formed, and the bottom material layer and the top material layer in the laminated structure formed by the sacrificial layer and the support layer Both are the support layer.

In one example, the number of the support layer includes three layers, including the top support layer 106, the middle support layer 104 and the bottom support layer 102, and the number of the sacrificial layer includes two layers, including the top support layer 106 and the bottom support layer 102. The first sacrificial layer 105 between the middle supporting layer 104 and the second sacrificial layer 103 between the bottom supporting layer 102 and the middle supporting layer 104 .

Specifically, each support layer and each sacrificial layer can be formed by using an atomic layer deposition process (Atomic Layer Deposition) or a plasma vapor deposition process (Plasma Enhanced Chemical Vapor Deposition), such as the underlying support layer 102, the second part of the sacrificial layer 103 , the middle support layer 104 , the second partial sacrificial layer 105 and the top support layer 106 .

It should be noted that the material of the sacrificial layer includes silicon oxide or silicon oxynitride or polysilicon layer, the sacrificial layer may be doped with boron or phosphorus, and the material of the supporting layer includes silicon nitride, silicon oxynitride, Any one of alumina or a combination of any two or more. The material of the sacrificial layer is different from the material of the support layer, and the corrosion rates of the two are different in the same etching process (such as the same etching solution), which is specifically shown in the same etching process (such as the same etching solution). , the etching (eg etching) rate of the sacrificial layer is much greater than the etching rate of the supporting layer, so that when the sacrificial layer is completely removed, the supporting layer is almost completely retained. In this embodiment, the material of the sacrificial layer is SiO ₂ , the material of the support layer is SiN, and a wet etching process is adopted, and the etching solution used in the wet etching includes hydrofluoric acid solution and ammonium hydrofluoric acid One of the aqueous solutions.

In addition, except for the case of three supporting layers and two sacrificial layers listed above, the number of said sacrificial layers and supporting layers can be set according to the required height of the subsequent capacitor, and the number of stacks can be 1 to 10 times or more, among them, 2 to 5 times are appropriate.

Further, the sacrificial layer will be removed in the subsequent process, and the supporting layer is used as a supporting frame after the sacrificial layer is removed in the subsequent process. Since the supporting frame is added in this embodiment, not only It can greatly improve the mechanical strength of the structure when the capacitor is subsequently manufactured, and can avoid damage to the capacitor during the subsequent process (such as grinding, etc.). In addition, in this example, the sacrificial layer is doped with boron or phosphorus, which can ensure the uniformity of critical dimensions and increase the removal rate of the sacrificial layer.

Next, as shown in S2 in FIG. 5 and FIGS. 8-9, step 2) is performed to form a patterned mask layer 107 with windows 108 arranged in an array on the structure obtained in step 1), and based on the pattern The mask layer 107 is etched in the sacrificial layers, such as 103 , 105 , and the supporting layers, such as 102 , 104 , 106 to form capacitor holes 109 corresponding to the windows 108 .

As an example, the capacitor hole 109 formed in step 2) exposes the capacitor contact node 101 .

Specifically, through this step to realize the definition of the position of the capacitor hole 109, a layer of photoresist layer can be formed first, as the material layer of the patterned mask layer 107, of course, other examples can also be formed A mask layer of material (such as a silicon nitride hard mask layer, etc.), and then use a photolithography process to pattern this layer of material layer (such as a photoresist layer) to obtain the pattern with the window 108 The patterned mask layer 107, wherein the windows 108 may be arranged in a hexagonal array along the surface of the patterned mask layer 107, corresponding to the capacitive contact nodes 101 below.

After the patterned mask layer 107 is formed, use it as a mask to etch to form the capacitor hole 109, specifically: according to the patterned mask layer 107, use a dry etching process, a wet etching process or The dry etching process and the wet etching process are combined to etch the supporting layer and the sacrificial layer, so as to form the capacitor hole 109 penetrating up and down in the supporting layer and the sacrificial layer, so The capacitor hole 109 exposes the capacitor contact node, as shown in FIG. 9 .

As an example, in step 2), the aspect ratio of the capacitor hole is between 5-20, and the height of the capacitor hole is in the range of 0.5-5 μm.

Specifically, the aspect ratio of the capacitor holes 109 is 5-20, preferably 6-10, and is selected as 8±0.5 in this example. In this embodiment, by designing the stacked structure of the sacrificial layer and the supporting layer, a capacitor hole 109 with a larger aspect ratio can be obtained, thereby greatly increasing the capacitance value per unit area, and improving the integration and performance of the storage device. In this example, the The depth of the capacitor hole 109 is 0.5-5 μm, preferably 1-4 μm, and in this example, it is selected as 3±0.5 μm.

Continue, as shown in S3 in FIG. 5 and FIGS. 10-15, perform step 3), form a lower electrode layer 110 on the bottom and side walls of the capacitor hole 109, and remove the sacrificial layer, such as 103, 105, to expose the outer surface of the lower electrode layer 110 .

Specifically, use atomic layer deposition (Atomic Layer Deposition) or plasma vapor deposition (Chemical Vapor Deposition) on the sidewall and bottom of the capacitor hole 109, and the laminated structure formed by the sacrificial layer and the support layer A lower electrode material layer is deposited on the upper surface of the upper surface, and the lower electrode material layer includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide) , nickel silicide (Titanium Silicide), titanium silicon nitride (TiSixNy), preferably, in this embodiment, the material of the lower electrode material layer is titanium nitride; then, chemical mechanical grinding or etching and other processes are used to remove The lower electrode material layer located on the upper surface of the laminated structure, the remaining lower electrode material layer located on the sidewall and bottom of the capacitance hole 109 is the lower electrode layer 110, and the supporting layer It is connected with the outer surface of the lower electrode layer.

As an example, a method for removing the sacrificial layer is provided, taking the following situation as an example: the number of the support layer is three layers, including a top support layer, an intermediate support layer and a bottom support layer, and the number of the sacrifice layer is Two layers, including a first sacrificial layer between the top supporting layer and the middle supporting layer and a second sacrificial layer between the bottom supporting layer and the middle supporting layer, in step 3), remove all The steps for describing the sacrificial layer include:

3-1) forming a first opening 1111 in the top support layer 106, as shown in FIGS. 11 and 12, to expose the first sacrificial layer 105 located on its lower surface;

3-2) Based on the first opening 1111, wet etching is used to remove the first sacrificial layer 105, as shown in FIG. 13 ;

3-3) Forming a second opening 1112 in the middle support layer 104, the second opening and the first opening constitute the opening 111 in this process, so as to expose the second sacrificial material located on its lower surface. Layer 103, as shown in Figure 14;

3-4) Based on the second opening 1112, wet etching is used to remove the second sacrificial layer 103, as shown in FIG. 15 .

Specifically, when the sacrificial layer and the support layer are other number or more material layers, by analogy, they are removed by opening and wet etching processes. In addition, as an example, steps 3-2) and The step 3-3) further includes a step of depositing a support layer material on the upper surface of the top support layer 106 to thicken the top support layer 106 . This is because in the process of step 3-2), a part of the top support layer 106 will be removed, in order to prevent the top support layer 106 from being cut through in the subsequent corrosion process, and to ensure that the upper support has sufficient support strength , it is necessary to add a step of depositing a support layer material on the upper surface of the top support layer 106 between step 3-2) and step 3-3).

As an example, in step 3-1), one first opening 111 overlaps only one capacitor hole 109, or one first opening 111 overlaps multiple capacitor holes 109 at the same time (as shown in FIG. 11, taking one first opening 1111 overlapping with three capacitance holes 109 as an example); in step 3-3), one second opening overlaps only one capacitance hole 109, Or one of the second openings overlaps with a plurality of capacitor holes 109 at the same time, wherein the setting of the second opening 1112 is similar to that of the first opening 1111. As an example, preferably the second opening 1112 and The first openings 1111 are arranged correspondingly up and down, and the opening method in FIG. 11 can be referred to.

Continue, as shown in S4 in FIG. 5 and FIGS. 16-17, perform step 4), form a capacitor dielectric layer 112 on the inner surface and the exposed outer surface of the lower electrode layer 110, and form a capacitor dielectric layer 112 on the capacitor dielectric layer 112 The upper electrode lining layer 113 is formed on the surface.

Specifically, the material of the capacitor dielectric layer 112 can be selected as a high-K dielectric material to increase the capacitance value of the capacitor per unit area, which includes one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or a combination of the above materials A stack formed by more than two types in a group.

In addition, the upper electrode lining layer 113 covering the outer surface of the capacitor medium 112 is formed by using an atomic layer deposition process (Atomic Layer Deposition) or a plasma vapor deposition process (Chemical Vapor Deposition), and the material of the upper electrode lining layer 113 can be Including tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon or a stack formed by two or more of the above-mentioned materials, and may also include metal nitrides And one or two compounds formed by metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride titanium (TiSixNy).

Continue, as shown in S5 in Fig. 5 and Figs. The gap between the inner walls of the lower electrode layers 110 and the outer surfaces of the adjacent lower electrode layers 110 extends to cover the upper electrode layer 113, wherein the material source for forming the conductor filling structure 116 includes at least silicon A source and a germanium source, the germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the silicon crystal grain size in the conductor filling structure.

Specifically, the purpose of this step is to prepare the metal connection structure between the capacitor and the upper electrode covering layer, that is, the conductor filling structure, and facilitate the implementation of the subsequent BEOL process after the capacitor array is completed, wherein, after the array is completed, The BEOL metal interconnection structure is started by covering the entire upper electrode with silicon oxide. Applying the preparation process of the conductor filling structure in the first embodiment to the capacitor in the second embodiment is beneficial to improve the performance of the capacitor.

In addition, after the upper electrode layer 113 is formed, there is still a certain unfilled space in the area inside the capacitor hole 109 and the area outside the capacitor hole 109 between the supporting layers. The conductor filling structure 116 first fills this part of the space, and then continues to deposit until covering the entire upper electrode layer 113, that is to say, at least a part of the conductor filling structure 116 is filled in the lower electrode layer 110 (such as a U-shaped structure) ) is also a gap surrounded by part of the capacitive dielectric layer and part of the upper electrode layer located on the inner wall surface of the lower electrode layer. In addition, the conductor filling structure 116 is partially filled Between the adjacent lower electrode layers, there is also a gap surrounded by a part of the capacitive dielectric layer and a part of the upper electrode layer on the outer surface of the adjacent lower electrode layer, and then continue to deposit until the entire upper electrode layer is covered. electrode layer 113 .

It should also be noted that this step is aimed at forming a conductor-filled structure 116 with high conductivity. In the present application, crystal nuclei elements are introduced during the formation of wires to act as crystal nuclei for polysilicon crystal grains to aggregate and grow, thereby effectively Increase the grain size of polysilicon. For example, doping germanium (Ge) atoms in polysilicon can help the growth of polysilicon grains. Ge atoms in polysilicon can achieve the effect similar to silicon crystal nuclei, so that silicon atoms can gather and then increase the grain size. Increasing the crystal grain size of polysilicon can reduce the influence of grain boundary traps on carriers, thereby increasing the electrical conductivity. The process is simple and the cost is low.

As an example, in step 5), the conductor filling structure includes a hole-filling conductive layer 114 and a gap bin 115, wherein the gap bin 115 is defined by the capacitance hole 109 between the polysilicon of the hole-filling conductive layer 114 The gap between them is formed, and the hole-filling conductive layer 114 covers the gap compartment 115 , as shown in FIG. 18 .

Specifically, in an example, the conductor filling structure 116 includes a hole-filling conductive layer 114 and a gap chamber 115, and under the process conditions set in this embodiment, a rough surface of the conductor filling structure is formed, wherein, during deposition and formation During the process of the conductor filling structure 116, the deposition material begins to form along the bottom and sidewall of the groove-like structure formed on the surface of the upper electrode layer in the capacitor hole. Due to the large crystal grain size, the relative deposition material layer is gradually deposited close, Its opposite surface encloses a gap compartment 115, forming a conductor filling structure 116 including a hole-filling conductive layer 114 and a gap compartment 115. The existence of the gap compartment 116 can also relieve the stress between the material layers on the periphery of the gap compartment. Strain, preventing thermal expansion and extrusion of individual material layers, etc., thereby protecting the overall device structure.

In addition, the conductor filling structure 116 is also formed on the upper surface of the semiconductor substrate 100 (the upper surface of the upper electrode layer) around the capacitor hole 109, wherein the conductor filling structure 116 includes a hole-filling conductive layer 114 and a gap The chamber 115, and the gap chamber 116 is preferably formed in the hole-filling conductive layer defined by the grooves of the trench structure, and the gap chamber is not formed in the hole-filling conductive layer on the upper surface of the substrate.

As an example, the upper surface of the hole-filling conductive layer 114 is higher than the upper surface of the upper electrode layer 113 above the top of the lower electrode layer 110 by 120˜800 angstroms.

As an example, at least one of the upper surface of the hole-filling conductive layer 114 corresponding to the top of the gap chamber 115 and the upper surface of the hole-filling conductive layer 114 has a high point and a low point formed by stacking silicon grains. , and the high point is 80-300 angstroms higher than the low point. In addition, the surface of the hole-filling conductive layer 114 exposed on the gap chamber 115 also has the high point and the low point, as shown in FIG. 19 And as shown in Figure 20.

As an example, the silicon crystal grain size in the conductor filling structure 116 is between 50˜1500 angstroms.

Specifically, for the thickness of the hole-filling conductive layer 114, the thickness of the upper surface of the semiconductor substrate 100 around the capacitor hole 109 is controlled to be 120-800 angstroms, wherein the crystal grain size in the conductor filling structure 116 can vary with As the film thickness at this position increases, it will increase, but if it is too thick, the flatness of the surface will become too poor, which will affect the subsequent manufacturing process. Therefore, the preferred thickness is 200 to 600 angstroms. In this embodiment, it is selected as 500 angstroms, so that it can be A conductor filling structure 116 with good electrical properties and beneficial to subsequent processes is obtained. Further, by adopting the method in this example, the silicon crystal grain size in the formed conductor filling structure 116 is about 50-1500 angstroms, preferably 500-1000 angstroms.

In addition, in this example, the exposed position of the conductor filling structure 116, such as the hole-filling conductive layer 114 exposed on the surface of the part of the gap chamber 115, as shown in FIG. 19, the hole-filling conductive layer 114 is located The surface of the part of the upper surface of the semiconductor substrate 100 around the capacitor hole 109, as shown in FIG. The upper surface will form a high point and a low point of grain accumulation. In this example, the highest point of the exposed position is preferably the high point, and the lowest point of the exposed position is the low point, wherein the highest and the lowest are With respect to the structure of its deposition, such as the sidewall of the capacitor hole, the bottom of the capacitor hole and the upper surface of the semiconductor substrate, wherein the high point is higher than the difference between the low point, as shown in Figure 19 and As described in the distances D1 and D2 in FIG. 20 , the height difference is preferably 100-200 angstroms, which can help to improve the electrical performance of the conductor filling structure and help form the appropriate size of the gap chamber.

As an example, in step 5), the weight percentage of germanium in the conductor filling structure 116 is between 10% and 80%.

As an example, in step 5), the temperature for forming the conductor filling structure is between 350-450° C., and the pressure for forming the conductor filling structure is between 250-900 mTorr.

Specifically, in the formation of the conductor filling structure of this embodiment, a chemical vapor deposition process can be used, and the structure obtained in step 1) is placed in the low-pressure chemical vapor deposition furnace tube; The silicon source gas and the germanium source gas are reacted to form a conductor filling structure at the bottom, the side wall of the trench structure or at the same time on the upper surface of the substrate, wherein the silicon source gas is selected from SiH ₄ , Si ₂ H ₆ , SiH At least one of ₆ Cl, the germanium source gas is selected from at least one of GeH ₄ and Ge ₂ H ₆ , the temperature for forming the conductor filling structure 202 is preferably 380°C-420°C, and in this example, it is selected as 400± 10°C, the corresponding matching pressure range includes 250-450mT, in this example, 300±10mT is selected, adjusting the reaction temperature and pressure will further adjust the size of the silicon crystal grain size and the structure of the interstitial chamber in the conductor filling structure.

In addition, it should be noted that the doping ratio of germanium should be further adjusted, preferably between 40% and 60%, so that the deposition process can be further adjusted by the ratio of germanium under the condition that only silicon source and germanium source exist. The ratio of the existing crystal nuclei provided can obtain better silicon atom deposition and the optimal ratio of germanium atoms as crystal nuclei to obtain a reasonable silicon crystal grain size. In this example, the ratio of germanium is selected as 50%.

As an example, the conductor filling structure 116 further has a doping element, and the doping element is formed from any one of boron, phosphorus and arsenic.

Specifically, at least one of boron source gas, phosphorus source gas, and arsenic source gas may be injected while the conductor filling structure is being formed, so as to further optimize the electrical performance of the conductor filling structure.

Finally, as shown in S6 in FIG. 5 and FIG. 22 , step 6) is performed to form an upper electrode covering layer 118 on the surface of the conductor filling structure 116 .

Specifically, the upper electrode covering layer 118 is formed on the surface of the conductor filling structure 116, and its material includes but not limited to tungsten metal, and the upper electrode covering layer 118 can be used as a contact point of a tungsten plug (W plug).

As shown in FIG. 21 , as an example, a further step is included between step 5) and step 6): forming a protective layer 117 on the surface of the conductor filling structure 116, and the protective layer 117 is used to prevent the conductor filling structure 116 from Influence of germanium in the subsequent manufacturing process, wherein, the material of the protection layer 117 includes boron-doped polysilicon.

Specifically, the protection layer 117 is formed between the conductor filling structure 116 and the upper electrode covering layer 118. On the one hand, the protection layer 117 can prevent germanium in the conductor filling structure 116 from affecting the subsequent process. In addition, the protection layer 117 can also increase the adhesion between the conductor filling structure 116 and the upper electrode covering layer 118, and the material of the protection layer 117 is preferably boron-doped polysilicon, It is also beneficial to improve the conductivity between the conductor filling structure 116 and the upper electrode covering layer 118 .

As an example, the conductor filling structure 116 and the protective layer 117 are prepared in the same reaction chamber; the germanium source gas for forming the conductor filling structure 116 includes at least one of GeH ₄ and Ge ₂ H ₆ , forming the The silicon source gas for the conductor filling structure 116 includes at least one of SiH ₄ , Si ₂ H ₆ and SiH ₆ Cl; the silicon source gas for forming the protective layer 117 includes SiH ₄ , Si ₂ H ₆ and SiH ₆ Cl At least one, the boron source gas for forming the protective layer 117 includes at least one of BCl ₃ and B ₂ H ₆ ; wherein, the temperature for forming the protective layer 117 is between 300°C and 500°C, and the pressure is between Between 200-900 mTorr, the thickness of the formed protective layer is between 400-1500 angstroms.

Specifically, the temperature for forming the protective layer 117 is preferably 350-450°C, the pressure range for forming the protective layer 117 is between 250-800mT, in this example, 600±20mT is selected, and the thickness range is preferably 600-1000mT. eh.

As an example, step 5) also includes the step of doping the conductor filling structure 116, and the doping element is selected from any one of boron, phosphorus and arsenic; after step 6), it also includes The step of forming an oxide layer 119 on the surface of the electrode covering layer 118 is shown in FIG. 25 .

Specifically, at least one of boron source gas, phosphorus source gas, and arsenic source gas may be introduced while the conductor filling structure 116 is being formed, so as to further optimize the electrical performance of the conductor filling structure.

In addition, it also includes the step of continuing to form an oxide layer after the formation of the upper electrode covering layer 118 , such as forming a silicon oxide layer, and covering the entire upper electrode with silicon oxide before starting to fabricate the BEOL metal interconnection structure.

As shown in Figures 18-25, the present invention also provides a capacitor array structure, wherein the capacitor array structure is preferably prepared by the preparation method of the present invention, of course, it is not limited thereto, and the capacitor array structure includes:

A semiconductor substrate 100 comprising a plurality of capacitive contact nodes 101 located in a memory array structure;

The lower electrode layer 110 is connected to the capacitive contact node 101, and the cross-sectional shape of the lower electrode layer includes a U shape;

a capacitor dielectric layer 112 covering the inner and outer surfaces of the lower electrode layer 110;

an upper electrode layer 113 covering the surface of the capacitor dielectric layer 112;

The conductor filling structure 116 fills the gap between the inner walls of the lower electrode layers 110 and the outer surfaces of the adjacent lower electrode layers 110 and extends to cover the upper electrode layer 113, wherein the conductor filling structure 116 is formed. The material source of the structure 116 includes at least a silicon source and a germanium source, and the germanium atoms in the germanium source are used as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase the silicon crystal grain size in the conductor filling structure ;as well as

The upper electrode covering layer 118 covers the surface of the upper conductor filling structure 116 .

Specifically, in a specific structure, the substrate 100 further includes a semiconductor substrate (not shown in the figure), an active region and a word line are arranged in the semiconductor substrate, and a bit line and the capacitor contact node 101 are arranged on the semiconductor substrate. , the capacitor contact node 101 is electrically connected to the source of the transistor in the memory array structure and the like.

In addition, the capacitive contact nodes 101 may be arranged in a hexagonal array, which corresponds to the arrangement of capacitors manufactured later. And the capacitor contact nodes 101 are isolated by a spacer layer, and the material of the spacer layer can be any one of silicon nitride (SiN), silicon oxide (SiO ₂ ), and aluminum oxide (Al ₂ O ₃ ). Or any combination of two or more. In this embodiment, the material of the spacer layer is selected as SiN.

Specifically, the conductor filling structure 116 serves as a metal connection structure between the capacitor and the upper electrode covering layer, and facilitates the implementation of the subsequent BEOL process after the capacitor array is completed, wherein, after the array is completed, the entire array is covered with silicon oxide The BEOL metal interconnection structure starts to be fabricated on the upper electrode, and the fabrication process of the conductor filling structure in the first embodiment is used in the capacitor of the second embodiment, which is beneficial to improve the performance of the capacitor.

In addition, after the upper electrode layer 113 is formed, there is still a certain unfilled space in the area inside the capacitor hole 109 and the area outside the capacitor hole 109 between the supporting layers. The conductor filling structure 116 firstly fills this part of the space, and then continues to deposit until it covers the entire upper electrode layer 113 .

It should also be noted that this step is aimed at forming a conductor-filled structure 116 with high conductivity. In the present application, crystal nuclei elements are introduced during the formation of wires to act as crystal nuclei for polysilicon crystal grains to aggregate and grow, thereby effectively Increase the grain size of polysilicon. For example, doping germanium (Ge) atoms in polysilicon can help the growth of polysilicon grains. Ge atoms in polysilicon can achieve the effect similar to silicon crystal nuclei, so that silicon atoms can gather and then increase the grain size. Increasing the crystal grain size of polysilicon can reduce the influence of grain boundary traps on carriers, thereby increasing the electrical conductivity. The process is simple and the cost is low.

As an example, the conductor filling structure 116 includes a hole-filling conductive layer 114 and a gap bin 115, wherein the gap bin 115 is formed by the gap between the polysilicon of the hole-filling conductive layer 114 defined by the capacitance hole 109 , and the hole-filling conductive layer 114 covers the gap compartment 115 .

Specifically, in an example, the conductor filling structure 116 includes a hole-filling conductive layer 114 and a gap chamber 115, and under the process conditions set in this embodiment, a rough surface of the conductor filling structure is formed, wherein, during deposition and formation During the process of the conductor filling structure 116, the deposition material begins to form along the bottom and sidewall of the groove-like structure formed on the surface of the upper electrode layer in the capacitor hole. Due to the large crystal grain size, the relative deposition material layer is gradually deposited close, Its opposite surface encloses a gap compartment 115, forming a conductor filling structure 116 including a hole-filling conductive layer 114 and a gap compartment 115. The existence of the gap compartment 116 can also relieve the stress between the material layers on the periphery of the gap compartment. Strain, preventing thermal expansion and extrusion of individual material layers, etc., thereby protecting the overall device structure.

In addition, the conductor filling structure 116 is also formed on the upper surface of the semiconductor substrate 100 (the upper surface of the upper electrode layer) around the capacitor hole 109, wherein the conductor filling structure 116 includes a hole-filling conductive layer 114 and a gap The chamber 115, and the gap chamber 116 is preferably formed in the hole-filling conductive layer defined by the grooves of the trench structure, and the gap chamber is not formed in the hole-filling conductive layer on the upper surface of the substrate.

As an example, the upper surface of the hole-filling conductive layer 114 is higher than the upper surface of the upper electrode layer 113 above the top of the lower electrode layer 110 by 120-800 angstroms; the hole-filling conductive layer 114 corresponds to At least one of the upper surface of the top of the gap chamber 115 and the upper surface of the hole-filling conductive layer 114 has a high point and a low point formed by polysilicon stacking, and the high point is 80~ In addition, the surface of the hole-filling conductive layer 114 exposed on the gap chamber 115 also has the high point and the low point.

As an example, the weight percentage of germanium in the conductor filling structure 116 is between 10%-80%; the silicon crystal grain size of the conductor filling structure 116 is between 50-1500 angstroms.

Specifically, for the thickness of the hole-filling conductive layer 114, the thickness of the upper surface of the semiconductor substrate 100 around the capacitor hole 109 is controlled to be 120-800 angstroms, wherein the crystal grain size in the conductor filling structure 116 can vary with As the film thickness increases at this position, it will increase, but if it is too thick, the flatness of the surface will become too poor, which will affect the subsequent manufacturing process. Therefore, the thickness is preferably 200-600 angstroms, and it is selected as 500 ± 20 angstroms in this embodiment. In this way, the conductor filling structure 116 with good electrical performance and beneficial to subsequent processes can be obtained. Further, by adopting the method in this example, the silicon crystal grain size in the formed conductor filling structure 116 is about 50-1500 angstroms, preferably 500-1000 angstroms.

In addition, in this example, the exposed position of the conductor filling structure 116, such as the hole-filling conductive layer 114 exposed on the surface of the part of the gap chamber 115, as shown in FIG. 19, the hole-filling conductive layer 114 is located The surface of the part of the upper surface of the semiconductor substrate 100 around the capacitor hole 109, as shown in FIG. The upper surface will form a high point and a low point of grain accumulation. In this example, the highest point of the exposed position is preferably the high point, and the lowest point of the exposed position is the low point, wherein the highest and the lowest are With respect to the structure deposited therein, such as the sidewall of the capacitor hole, the bottom of the capacitor hole and the upper surface of the semiconductor substrate, the upper surface of the conductor filling structure 116 corresponding to the top of the gap chamber 115 has polysilicon The high point and low point formed by accumulation, and the high point is 80-300 angstroms higher than the low point, wherein the difference between the high point and the low point is as shown in the spacing in Figure 19 and Figure 20 As described in D1 and D2, the height difference is preferably 100 to 200 angstroms, and in this example, it is selected as 150±10 angstroms, which can help improve the electrical performance of the conductor filling structure and help the formation of the gap chamber. size.

In addition, it should be noted that the doping ratio of germanium should be further adjusted, preferably between 40% and 60%, so that the deposition process can be further adjusted by the ratio of germanium under the condition that only silicon source and germanium source exist. The ratio of the existing crystal nuclei provided can obtain better silicon atom deposition and the optimal ratio of germanium atoms as crystal nuclei to obtain a reasonable silicon crystal grain size. In this example, the ratio of germanium is selected to be 50±5%.

As an example, the conductor filling structure 116 further has a doping element, and the doping element is formed from any one of boron, phosphorus and arsenic.

Specifically, at least one of boron source gas, phosphorus source gas, and arsenic source gas may be injected while the conductor filling structure is being formed, so as to further optimize the electrical performance of the conductor filling structure.

As an example, a protection layer 117 is formed between the conductor filling structure 116 and the upper electrode covering layer 118, and the protection layer 117 is used to prevent germanium in the conductor filling structure 116 from affecting subsequent manufacturing processes, wherein , the material of the protection layer 117 includes boron-doped polysilicon.

Specifically, the protection layer 117 is formed between the conductor filling structure 116 and the upper electrode covering layer 118. On the one hand, the protection layer 117 can prevent germanium in the conductor filling structure 116 from affecting the subsequent process. In addition, the protection layer 117 can also increase the adhesion between the conductor filling structure 116 and the upper electrode covering layer 118, and the material of the protection layer 117 is preferably boron-doped polysilicon, It is also beneficial to improve the conductivity between the conductor filling structure 116 and the upper electrode covering layer 118 .

As an example, the conductor filling structure 116 further has a doping element selected from any one of boron, phosphorus and arsenic; an oxide layer 119 is formed on the surface of the upper electrode covering layer 118 .

Specifically, at least one of boron source gas, phosphorus source gas, and arsenic source gas may be introduced while the conductor filling structure 116 is being formed, so as to further optimize the electrical performance of the conductor filling structure. In addition, it also includes the step of continuing to form an oxide layer after the formation of the upper electrode covering layer 118 , such as forming a silicon oxide layer, and covering the entire upper electrode with silicon oxide before starting to fabricate the BEOL metal interconnection structure.

In summary, the present invention provides a polysilicon-based conductor structure, capacitor array structure and preparation method. The preparation of the conductor structure includes: providing a substrate, forming a cavity structure in the substrate; A conductor filling structure is formed inside, and the material source for forming the conductor filling structure includes at least a silicon source and a germanium source, wherein the germanium atoms in the germanium source serve as crystal nuclei for the aggregation and growth of silicon atoms in the silicon source, so as to increase The silicon crystal grain size in the conductor-filled structure is large. Through the above-mentioned scheme, in the conductor filling structure and preparation of the present invention, a method of manufacturing large grain size doped polysilicon is proposed, and a crystal nucleus element, such as germanium element, is introduced as a silicon grain aggregation growth in polysilicon Doping germanium atoms can help the growth of polysilicon grains. Germanium atoms in doping polysilicon can achieve a similar effect as silicon nuclei, making silicon atoms aggregate and increase the crystal grain size. Increasing the polysilicon crystal grain size can reduce grain boundary traps (grainboundary trap) The influence on the carrier increases the conductivity, that is, reduces the grain boundary density and improves the conductivity. The above method can be applied to various wires made of polysilicon, such as a capacitor structure. In addition, the present invention also prevents the influence of germanium in the conductor filling structure on the process through the setting of the protective layer, and achieves the conductor filling structure. The effective connection with other structural layers, and the introduction of doping elements, etc., further improve the electrical performance of the conductor filling structure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (24)

1. a kind of preparation method of the conductor structure based on polysilicon processing procedure, which comprises the steps of:

1) substrate is provided, forms cave structure in Yu Suoshu substrate；And

2) it is passed through silicon source gas simultaneously and ge source gas is reacted in forming conductor filled structure in the cave structure, instead Answering temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆At least one of Cl, the ge source gas Body is selected from GeH4 and Ge₂H₆At least one of, wherein the germanium atom in the ge source is assembled as silicon atom in the silicon source The nucleus of growth, to increase silicon grain size number in the conductor filled structure formed, the silicon grain size number is 500~1000 Angstrom；The conductor filled structure includes filling perforation conductive layer and gap storehouse, the gap storehouse by the filling perforation conductive layer polysilicon Between gap constitute, and the filling perforation conductive layer coats the gap storehouse, the weight hundred of the germanium in the conductor filled structure Divide ratio between 40%~60%.

2. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that described to fill out Hole conductive layer is filled in the cave structure and also extends over the upper surface of the substrate around the cave structure, institute Gap position in storehouse is stated in the filling perforation conductive layer as defined by the cave structure.

3. the preparation method of the conductor structure according to claim 2 based on polysilicon processing procedure, which is characterized in that described to fill out Hole conductive layer is located at the thickness of the upper surface of substrate part between 120~800 angstroms.

4. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that described to fill out The upper surface that hole conductive layer corresponds to gap silo roof end has the high point formed by polycrystalline and low spot, and the height Point is higher by 80~300 angstroms of the low spot.

5. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that step 2) In, silicon grain size number is between 50~1500 angstroms in the conductor filled structure.

6. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that form institute The pressure of conductor filled structure is stated between 250~900 millitorrs.

7. a kind of preparation method of capacitor arrangement array, which comprises the steps of:

1) semi-conductive substrate is provided, the semiconductor substrate includes that several are located at the capacitance contact section in memory array structure Point, and in forming the sacrificial layer and supporting layer being alternately superimposed in the semiconductor substrate；

2) in the Patterned masking layer for forming the window with array arrangement in the structure that step 1) obtains, and based on the figure Change mask layer and etch the sacrificial layer and the supporting layer, to form capacitor corresponding with window hole, the capacitor hole is aobvious Reveal the capacitance contact node；

3) bottom in Yu Suoshu capacitor hole and side wall form lower electrode layer, and remove the sacrificial layer, to appear the lower electrode The outer surface of layer；

4) inner surface of Yu Suoshu lower electrode layer and the outer surface appeared form capacitor dielectric layer, and in the capacitor dielectric layer Surface formed upper electrode layer；

5) it is passed through silicon source gas simultaneously and ge source gas is reacted and forms conductor filled knot with the surface in the upper electrode layer Structure, the conductor filled structure filling is between the inner wall of the lower electrode layer and between the outer surface of the adjacent lower electrode layer Gap and extend over the upper electrode layer, reaction temperature be 380 DEG C~420 DEG C, the silicon source gas be selected from SiH₄、Si₂H₆ And SiH₆At least one of Cl, the ge source gas are selected from GeH₄And Ge₂H₆At least one of, the germanium in the ge source is former Nucleus of the son as silicon atom aggregation growth in the silicon source, to increase silicon crystal grain in the conductor filled structure formed Degree, the silicon grain size number are 500~1000 angstroms；The conductor filled structure includes filling perforation conductive layer and gap storehouse, between described Gap storehouse is made of the gap between the polysilicon of the filling perforation conductive layer of capacitor hole institute characterizing portion, and the filling perforation is led Electric layer coats the gap storehouse, and the weight percent of the germanium in the conductor filled structure is between 40%~60%；And

6) top electrode coating is formed in the conductor filled body structure surface.

8. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that the filling perforation conductive layer Upper surface is higher by 120~800 angstroms compared to the upper surface of the upper electrode layer of the lower electrode layer over top.

9. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that the filling perforation conductive layer pair At least one of both the upper surface at gap silo roof end and the upper surface of the filling perforation conductive layer described in Ying Yu have by more Crystal silicon accumulates the high point to be formed and low spot, and the high point is higher by 80~300 angstroms of the low spot.

10. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that described to lead in step 5) Silicon grain size number is between 50~1500 angstroms in body interstitital texture；Formed the pressure of the conductor filled structure between 250~ Between 900 millitorrs.

11. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that in step 1), the branch The quantity for supportting layer is three layers, including top support layer, middle support layer and base layer support layer, and the quantity of the sacrificial layer is two Layer, including the first sacrificial layer and positioned at the base layer support layer positioned at the top support layer and the middle support layer between The second sacrificial layer between the middle support layer；In step 3), the step of removing the sacrificial layer, includes:

The first opening is formed in Yu Suoshu top support layer, 3-1) to expose first sacrificial layer for being located at its lower surface；

3-2) based on first opening, first sacrificial layer is removed using wet-etching technology；

The second opening is formed in Yu Suoshu middle support layer, 3-3) to expose second sacrificial layer for being located at its lower surface；

3-4) based on second opening, second sacrificial layer is removed using wet-etching technology.

12. the preparation method of capacitor arrangement array according to claim 11, which is characterized in that step 3-1) in, one A first opening only with a capacitor hole is overlapping or first opening simultaneously with multiple capacitor holes It is overlapping；Step 3-3) in, second opening is only overlapped with a capacitor hole or second opening is same When it is overlapping with multiple capacitor holes.

13. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that in step 5), further include The step of conductor filled structure is doped, any one of doped chemical in boron, phosphorus and arsenic；Step 6) it Afterwards, further include the steps that forming oxide layer in the top electrode cover surface.

14. the preparation method of capacitor arrangement array according to any one of claim 7~13, which is characterized in that It is further comprised the steps of: between step 5) and step 6) and forms a protective layer in the conductor filled body structure surface, it is described protective layer used In preventing influence of the germanium in the conductor filled structure to follow-up process, wherein the material of the protective layer includes boron doping Polysilicon.

15. the preparation method of capacitor arrangement array according to claim 14, which is characterized in that the conductor filled knot Structure is prepared in same reaction chamber with the protective layer；The silicon source gas for forming the protective layer includes SiH₄、Si₂H₆And SiH₆At least one of Cl, the boron source gas for forming the protective layer includes BCl₃And B₂H₆At least one of；Wherein, shape At the temperature of the protective layer between 300~500 DEG C, pressure is between 200~900 millitorrs, the protection of formation The thickness of layer is between 400~1500 angstroms.

16. a kind of conductor structure based on polysilicon processing procedure characterized by comprising

Substrate is formed with cave structure in the substrate；And

Conductor filled structure is located in the cave structure, and the conductor filled structure is by the silicon source gas and germanium that are passed through simultaneously Source gas precursor reactant is formed, and reaction temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆In Cl extremely Few one kind, the ge source gas are selected from GeH₄And Ge₂H₆At least one of, wherein described in the germanium atom in the ge source is used as The nucleus of silicon atom aggregation growth in silicon source, to increase silicon grain size number in the conductor filled structure, the silicon grain size number It is 500~1000 angstroms；The conductor filled structure includes filling perforation conductive layer and gap storehouse, and the gap storehouse is conductive by the filling perforation Gap between the polysilicon of layer is constituted, and the filling perforation conductive layer cladding gap storehouse, in the conductor filled structure The weight percent of germanium is between 40%~60%.

17. the conductor structure according to claim 16 based on polysilicon processing procedure, which is characterized in that the filling perforation conductive layer It is filled in the cave structure and also extends over the upper surface of the substrate around the cave structure, the gap storehouse In the filling perforation conductive layer as defined by the cave structure；The filling perforation conductive layer is located at the upper surface of substrate portion The thickness divided is between 120~800 angstroms.

18. the conductor structure according to claim 16 based on polysilicon processing procedure, which is characterized in that the conductor filled knot Also there is doped chemical, any one formation of the doped chemical in boron, phosphorus and arsenic in structure.

19. the conductor structure based on polysilicon processing procedure described in any one of 6~18 according to claim 1, which is characterized in that The filling perforation conductive layer corresponds to the upper surface at gap silo roof end with the high point and low spot formed by polycrystalline, institute It states high point and is higher by 80~300 angstroms of the low spot；Silicon grain size number is between 50~1500 angstroms in the conductor filled structure.

20. a kind of array of capacitors structure characterized by comprising

Semiconductor substrate, the semiconductor substrate include that several are located at the capacitance contact node in memory array structure；

Lower electrode layer is engaged on the capacitance contact node, and the cross sectional shape of the lower electrode layer includes U-shaped；

Capacitor dielectric layer is covered in inner surface and the outer surface of the lower electrode layer；

Upper electrode layer is covered in the surface of the capacitor dielectric layer；

Conductor filled structure is filled between the inner wall of the lower electrode layer and between the outer surface of the adjacent lower electrode layer Gap simultaneously extends over the upper electrode layer, and the conductor filled structure is by the silicon source gas being passed through simultaneously and ge source gas reaction It is formed, reaction temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆At least one of Cl, institute It states ge source gas and is selected from GeH₄And Ge₂H₆At least one of, the germanium atom in the ge source is used for former as silicon in the silicon source The nucleus of son aggregation growth, to increase silicon grain size number in the conductor filled structure, the silicon grain size number is 500~1000 Angstrom；The conductor filled structure includes filling perforation conductive layer and gap storehouse, and the gap storehouse is by capacitor hole institute characterizing portion Gap between the polysilicon of the filling perforation conductive layer is constituted, and the filling perforation conductive layer coats the gap storehouse, the conductor The weight percent of germanium in interstitital texture is between 40%~60%；And

Top electrode coating is covered in the surface of the conductor filled structure.

21. array of capacitors structure according to claim 20, which is characterized in that the upper surface phase of the filling perforation conductive layer Upper surface compared with the upper electrode layer of the lower electrode layer over top is higher by 120~800 angstroms；The filling perforation conductive layer pair At least one of both the upper surface at gap silo roof end and the upper surface of the filling perforation conductive layer described in Ying Yu have by more Crystal silicon accumulates the high point to be formed and low spot, and the high point is higher by 80~300 angstroms of the low spot.

22. array of capacitors structure according to claim 20, which is characterized in that the silicon of the conductor filled structure crystallizes Granularity is between 50~1500 angstroms.

23. array of capacitors structure according to claim 20, which is characterized in that also have in the conductor filled structure Doped chemical, any one of the doped chemical in boron, phosphorus and arsenic；The top electrode cover surface is also formed with oxygen Change layer.

24. the array of capacitors structure according to any one of claim 20~23, which is characterized in that the conductor is filled out It fills between structure and the top electrode coating and is also formed with protective layer, it is described protective layer used in preventing the conductor filled structure In influence of the germanium to follow-up process, wherein the material of the protective layer includes boron doped polysilicon.