CN111769117B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN111769117B CN111769117B CN202010601483.6A CN202010601483A CN111769117B CN 111769117 B CN111769117 B CN 111769117B CN 202010601483 A CN202010601483 A CN 202010601483A CN 111769117 B CN111769117 B CN 111769117B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The embodiment of the application discloses a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, a sacrificial layer positioned on the semiconductor substrate, a laminated structure positioned on the sacrificial layer and a channel hole penetrating through the laminated structure and the sacrificial layer; a channel layer is formed in the channel hole, and the channel layer is provided with a part corresponding to the sacrificial layer along the direction parallel to the semiconductor substrate; forming a gate line slot penetrating through the laminated structure to reach the sacrificial layer; removing the sacrificial layer through the gate wire slot to expose the side wall of the portion of the channel layer and the upper surface of the semiconductor substrate; and forming a germanium-silicon epitaxial layer on the exposed side wall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process.
Description
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, with integration density being increased by three-dimensionally arranging memory cells over a substrate. The technical development of such a three-dimensional memory device is one of the mainstream of international development.
In the process of the three-dimensional memory device, in order to realize the electrical connection between the channel and the gate wire groove (i.e. common source channel), a silicon epitaxial layer is laterally grown on the side wall of the channel layer. However, in the conventional process, it is difficult to control the growth thickness of the silicon epitaxial layer during the formation of the silicon epitaxial layer, thereby affecting the uniformity of the grown silicon epitaxial layer. In addition, the carrier mobility of the silicon epitaxial layer is relatively low, which makes it difficult to meet the requirements of the three-dimensional memory devices which are being developed increasingly.
Disclosure of Invention
In view of the above, embodiments of the present application provide a three-dimensional memory and a method for manufacturing the same to solve at least one problem in the prior art.
In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional memory, where the method includes:
providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, a sacrificial layer positioned on the semiconductor substrate, a laminated structure positioned on the sacrificial layer and a channel hole penetrating through the laminated structure and the sacrificial layer; a channel layer is formed in the channel hole, and the channel layer is provided with a part corresponding to the sacrificial layer along the direction parallel to the semiconductor substrate;
forming a gate line slot penetrating through the laminated structure to reach the sacrificial layer;
removing the sacrificial layer through the gate wire slot to expose the side wall of the portion of the channel layer and the upper surface of the semiconductor substrate;
and forming a germanium-silicon epitaxial layer on the exposed side wall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process.
In an alternative embodiment, the side walls of the channel hole are formed with a functional layer that wraps the channel layer;
after removing the sacrificial layer through the gate wire trenches, the method further comprises:
removing a portion of the functional layer through the gate line trench to expose the portion of the channel layer.
In an alternative embodiment, the functional layer of the channel hole sidewall includes an oxide layer-nitride layer-oxide layer radially inward of the channel hole.
In an optional embodiment, after forming the gate line trench and before forming the silicon germanium epitaxial layer, the method further comprises:
forming a side wall structure on the side wall of the grid wire groove;
and removing part of the side wall structure to expose the oxide layer in the side wall structure.
In an alternative embodiment, the sidewall structure of the gate runner includes a nitride layer-oxide layer-nitride layer radially inward of the gate runner.
In an alternative embodiment, the side walls of the channel hole are formed with a functional layer that wraps the channel layer;
the thickness of the side wall structure of the grid line groove is larger than that of the functional layer of the side wall of the channel hole.
In an alternative embodiment, the thickness of the sidewall structure of the gate line trench is in the range of 20nm to 50 nm.
In an alternative embodiment, a silicon source gas and a germanium source gas are used as deposition gases in the selective epitaxial growth process.
In an alternative embodiment, the selective epitaxial growth process is carried out at a temperature of 400 ℃ to 800 ℃ and a pressure of 1 mTorr to 20 Torr.
In an alternative embodiment, the silicon germanium epitaxial layer is formed to extend from the sidewall of the channel layer along the upper surface of the semiconductor substrate at least to a position corresponding to the gate line trench.
In an optional embodiment, the method further comprises:
and forming a source electrode in the grid wire groove, wherein the source electrode is in conductive contact with the germanium-silicon epitaxial layer.
In a second aspect, an embodiment of the present application provides a three-dimensional memory, including:
a semiconductor substrate;
a stacked structure on the semiconductor substrate;
a channel hole and a grid line groove penetrating through the laminated structure; a channel layer is arranged in the channel hole, and a source electrode is arranged in the grid wire slot;
and the germanium-silicon epitaxial layer is connected with the channel layer and the source electrode.
In an optional embodiment, the silicon germanium epitaxial layer is located on the semiconductor substrate, and the silicon germanium epitaxial layer is in contact with the semiconductor substrate.
In an alternative embodiment, the upper surface of the semiconductor substrate has a first spacing from the stacked structure;
the channel layer penetrates through the laminated structure and extends into the semiconductor substrate, and the channel layer is provided with a part corresponding to the first interval along the direction parallel to the semiconductor substrate;
the silicon germanium epitaxial layer is in contact with a sidewall of the portion of the channel layer.
In an alternative embodiment, the silicon germanium epitaxial layer extends along the upper surface of the semiconductor substrate from the sidewall of the channel layer at least to below the source.
In an alternative embodiment, a sidewall structure is formed within the gate line trench, the sidewall structure including an oxide layer.
The embodiment of the application provides a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, a sacrificial layer positioned on the semiconductor substrate, a laminated structure positioned on the sacrificial layer and a channel hole penetrating through the laminated structure and the sacrificial layer; a channel layer is formed in the channel hole, and the channel layer is provided with a part corresponding to the sacrificial layer along the direction parallel to the semiconductor substrate; forming a gate line slot penetrating through the laminated structure to reach the sacrificial layer; removing the sacrificial layer through the gate wire slot to expose the side wall of the portion of the channel layer and the upper surface of the semiconductor substrate; and forming a germanium-silicon epitaxial layer on the exposed side wall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process. According to the embodiment of the application, the exposed side wall of the part of the channel layer and the semiconductor substrate form the germanium-silicon epitaxial layer on the upper surface so as to lead out the side wall of the channel layer in a conductive manner, and the germanium-silicon epitaxial layer has higher carrier mobility, so that the channel current can be greatly improved.
Drawings
Fig. 1 is a schematic flow chart illustrating an implementation of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 2 a-2 f are schematic structural diagrams of a method for manufacturing a three-dimensional memory according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
In the process of a three-dimensional memory device, a silicon epitaxial layer is generally required to be formed at the bottom of a channel hole, and the process comprises the following steps: firstly, forming a channel hole; secondly, forming a grid wire slot; thirdly, removing the sacrificial layer; fourthly, removing the ONO structure of the channel hole in the sacrificial layer to expose the channel layer of the channel hole; fifth, a silicon epitaxial layer is selectively epitaxially grown to connect the channel layer and the substrate. However, during the selective epitaxial growth of the silicon epitaxial layer, an etching gas HCL exists, and the existence of the etching gas HCL may cause non-uniform thickness of the silicon epitaxial layer formed on the side wall of the channel hole and even cause the channel layer to be thinned, thereby affecting the yield of the device. Although the thickness of the silicon epitaxial layer can be improved to a certain extent by reducing the proportion of the etching gas HCL, the selectivity can be reduced due to the fact that the etching gas HCL is less, so that an unnecessary silicon epitaxial layer is formed on the side wall of the grid wire groove, and even the inside of the grid wire groove can be filled with the silicon epitaxial layer.
Therefore, the following technical scheme of the embodiment of the application is provided.
Fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure, and the method mainly includes the following steps:
In an embodiment of the present application, a semiconductor structure is provided that includes a semiconductor substrate, a sacrificial layer on the semiconductor substrate, a stack structure on the sacrificial layer, and a channel hole through the stack structure and the sacrificial layer. The semiconductor substrate may be a simple substance semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The material of the sacrificial layer may be polysilicon. In some embodiments, before forming the sacrificial layer, an oxide layer may be further formed on the semiconductor substrate to protect the semiconductor substrate from being damaged (damage) in a subsequent step of removing the functional layer of the channel hole. The laminated structure specifically comprises: the nitride layer is formed between adjacent oxide layers. Preferably, the nitride layer is silicon nitride and the oxide layer is silicon oxide. In practical applications, the oxide Layer and the nitride Layer may be formed by a Deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering (sputtering), Metal-Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD). It should be noted that the semiconductor structure includes a plurality of channel holes.
In the embodiment of the present application, a channel layer is formed in the channel hole, the channel layer having a portion corresponding to the sacrificial layer in a direction parallel to the semiconductor substrate. And the side wall of the channel hole is provided with a functional layer for coating the channel layer. Wherein, the material of the channel layer can be monocrystalline silicon or polycrystalline silicon. The functional layer of the channel hole sidewall includes an oxide layer-nitride layer-oxide layer radially inward of the channel hole. Preferably, the nitride layer is silicon nitride and the oxide layer is silicon oxide. The channel hole may be a cylindrical hole in the embodiments of the present application, but is not limited to a cylindrical hole.
In the embodiment of the application, the laminated structure is etched to form a gate line slot which penetrates through the laminated structure and reaches the sacrificial layer. And forming a side wall structure on the side wall of the grid wire groove, wherein the side wall structure of the grid wire groove comprises a nitride layer-an oxide layer-a nitride layer which is inward along the radial direction of the grid wire groove. The thickness of the innermost nitride layer ranges from 5 nm to 10nm, the thickness of the intermediate oxide layer ranges from 5 nm to 20nm, and the thickness of the outermost nitride layer ranges from 5 nm to 20 nm. The thickness range of the side wall structure of the grid line groove is 20nm-50 nm.
In the embodiment of the application, the sacrificial layer is removed through the gate line slot, and a gap is formed between the laminated structure and the semiconductor substrate. At this time, the side wall of the channel hole at the portion of the sacrifice layer is exposed in the gap, and the upper surface of the semiconductor substrate is also exposed in the gap. In practical applications, the sacrificial layer is removed by wet etching, for example. When the sacrificial layer is removed by wet etching, the oxide layer at the bottommost layer of the stacked structure and the oxide layer of the outer side wall of the portion of the channel hole in the sacrificial layer can be used as a stop layer for the wet etching. In some embodiments, an oxide layer may be further included between the semiconductor substrate and the sacrificial layer, and the oxide layer may also serve as a stop layer for wet etching when the sacrificial layer is removed by wet etching.
And 104, forming a germanium-silicon epitaxial layer on the exposed side wall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process.
In a specific embodiment of the present application, before step 104, the method may further include: removing a portion of the functional layer through the gate line trench to expose the portion of the channel layer. Specifically, the method comprises the following steps: and sequentially removing parts of the functional layer in the gap between the laminated structure and the semiconductor substrate through the grid wire slot, wherein the functional layer comprises an oxide layer, a nitride layer and an oxide layer, so that the channel layer is exposed. In practical application, the oxide layer, the nitride layer and the oxide layer in the functional layer can be removed sequentially through multiple wet etching. In this process, the portions of the outermost nitride layer and the intermediate oxide layer in the sidewall structure of the gate line trench are also removed, thereby exposing the oxide layer in the sidewall structure. In some embodiments, an oxide layer may be further included between the semiconductor substrate and the sacrificial layer, and in this process, the oxide layer on the semiconductor substrate is also removed, thereby exposing the upper surface of the semiconductor substrate. It should be noted that the thickness of the sidewall structure of the gate line trench is greater than the thickness of the functional layer of the sidewall of the channel hole. Therefore, when the functional layer on the side wall of the channel hole is removed, the side wall structure of the grid line groove cannot be completely removed.
In the embodiment of the application, a germanium-silicon epitaxial layer is formed on the exposed side wall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process, and the formed germanium-silicon epitaxial layer at least extends to the position corresponding to the grid wire groove from the side wall of the channel layer along the upper surface of the semiconductor substrate. In the selective epitaxial growth process, silicon source gas and germanium source gas are used as deposition gases. The temperature of the selective epitaxial growth process is 400-800 ℃, and the air pressure is 1 mTorr-20 Torr. Wherein the silicon source gas may be SiH4The germanium source gas may be GeH4。
In the embodiment of the present invention, after the sige epitaxial layer is formed, a high-k material is deposited in the gap to form a high-k material layer on the sige epitaxial layer and fill the gap. And etching the high-dielectric-constant material layer through the grid wire slot to expose the germanium-silicon epitaxial layer, forming a source electrode contact region on the germanium-silicon epitaxial layer, filling a conductive material in the grid wire slot to form a source electrode in the grid wire slot, and enabling the source electrode to be in conductive contact with the germanium-silicon epitaxial layer through the source electrode contact region. The high-dielectric-constant material may be aluminum oxide, the source contact region may be titanium nitride, and the conductive material may be metal tungsten.
According to the embodiment of the application, the channel layer is exposed through a selective epitaxial growth process, the side wall of the channel layer and the semiconductor substrate are provided with the germanium-silicon epitaxial layer on the upper surface so that the side wall of the channel layer is led out in a conductive mode, and compared with a silicon epitaxial layer, the germanium-silicon epitaxial layer has higher carrier mobility, so that channel current can be greatly improved. And this application embodiment utilizes germanium silicon material to nucleate the characteristics that need certain time on the oxide layer surface, and this application embodiment remains the oxide layer of certain thickness at the lateral wall structure of grid wire casing to germanium silicon epitaxial layer only forms on the part that the channel hole and semiconductor substrate expose, and can not form in the grid wire casing.
An embodiment of the present invention will be described in detail with reference to fig. 2a to 2f, where fig. 2a to 2f are schematic structural diagrams of a three-dimensional memory and a method for fabricating the same according to a specific example of the present invention, and as shown in fig. 2a, a semiconductor structure is provided, where the semiconductor structure includes: a semiconductor substrate 210, a stop layer 221 and a sacrificial layer 222 on the semiconductor substrate, a stacked structure 230 on the sacrificial layer 222, and a channel hole 240 penetrating the stacked structure 230 and the sacrificial layer 222; a channel layer 241 is formed in the channel hole 240, the channel layer 241 having a portion corresponding to the sacrificial layer in a direction parallel to the semiconductor substrate 210. A functional layer 242 covering the channel layer 241 is formed on the sidewall of the channel hole 240. Wherein the functional layer 242 of the sidewall of the channel hole 240 includes an oxide layer 2421, a nitride layer 2422 and an oxide layer 2423 radially inward of the channel hole 240. The stop layer 221 may be an oxide layer. The semiconductor structure has a plurality of channel holes therein.
As shown in fig. 2b, the stacked structure 230 is etched to form a gate line trench 250 that penetrates the stacked structure 230 to reach the sacrificial layer 222. A sidewall structure 251 is formed on a sidewall of the gate line trench 250, and the sidewall structure 251 of the gate line trench 250 includes a nitride layer 2511, an oxide layer 2512 and a nitride layer 2513 radially inward of the gate line trench 250.
As shown in fig. 2c, the bottom of the gate line groove 250 is etched to expose the sacrificial layer 222, and the sacrificial layer 222 is removed through the gate line groove 250, so as to form a gap 260 between the stacked structure 230 and the semiconductor substrate 210. At this time, the sidewall of the channel hole 240 at the portion of the sacrificial layer 222 is exposed in the gap 260, and the upper surface of the semiconductor substrate 210 is also exposed in the gap 260. In practical applications, the sacrificial layer is removed by wet etching, for example.
As shown in fig. 2d, a portion of the functional layer 242, including the oxide layer 2421, the nitride layer 2422 and the oxide layer 2423, in the gap 260 between the stacked-layer structure 230 and the semiconductor substrate 210 is sequentially removed through the gate line groove 250, so that the portion of the channel layer 241 is exposed. In this process, portions of the outermost nitride layer 2511 and the intermediate oxide layer 2512 in the sidewall structures 251 of the gate line trenches 250 are also removed, thereby exposing the oxide layer 2512 in the sidewall structures 251. In this process, the stop layer 221 on the semiconductor substrate 210 is also removed, thereby exposing the upper surface of the semiconductor substrate 210. Note that, the thickness of the sidewall structure 251 of the gate line groove 250 is greater than the thickness of the functional layer 242 on the sidewall of the channel hole 240. So that the sidewall structure 251 of the gate line groove 250 is not completely removed when the functional layer 242 on the sidewall of the channel hole 240 is removed.
As shown in fig. 2e, a silicon germanium epitaxial layer 270 is formed on the exposed sidewall of the channel layer 241 and the upper surface of the semiconductor substrate 210 through a selective epitaxial growth process, and the formed silicon germanium epitaxial layer 270 extends from the sidewall of the channel layer 241 to at least a position corresponding to the gate line trench 250 along the upper surface of the semiconductor substrate 210. As shown in fig. 2e, the silicon germanium epitaxial layer 270 is formed to extend from the sidewall of the channel layer 241 of one channel hole 240 to the sidewall of the channel layer 241 of the other channel hole 240 along the upper surface of the semiconductor substrate 210. It should be noted that the shape of the sige epitaxial layer 270 illustrated in fig. 2e in this embodiment is only an exemplary shape, and when the sige epitaxial layer 270 is formed in this embodiment, the sige epitaxial layer 270 only needs to cover the upper surface of the semiconductor substrate 210 and connect the channel layer 241 and the semiconductor substrate 210, and the sige epitaxial layer 270 is not required to cover all of the sidewall of the channel layer 241. According to the embodiment of the application, the characteristic that nucleation of a germanium-silicon material on the surface of an oxide layer needs a certain time is utilized, the embodiment of the application enables removal of the side wall structure and the thickness of the functional layer, the oxide layer in the side wall structure is exposed, and therefore a germanium-silicon epitaxial layer is only formed on the channel hole and the exposed part of the semiconductor substrate and cannot be formed in the grid wire slot. Compared with a silicon epitaxial layer, the germanium-silicon epitaxial layer has higher carrier mobility, so that channel current can be greatly improved.
As shown in fig. 2f, after the sige epitaxial layer 270 is formed, a high-k material is deposited in the gap 260 to form a high-k material layer 280 on the sige epitaxial layer 270 and fill the gap 260. And etching the high-dielectric constant material layer 280 through the gate line groove 250 to expose the germanium-silicon epitaxial layer 270, forming a source contact region 291 on the germanium-silicon epitaxial layer 270, and filling a conductive material 292 in the gate line groove 250 to form a source 290 in the gate line groove 250, wherein the source 290 is in conductive contact with the germanium-silicon epitaxial layer 270 through the source contact region 291.
The embodiment of the application also provides a three-dimensional memory prepared by adopting the method in any one of the embodiments. Fig. 3 is a schematic diagram of a three-dimensional memory manufactured, and as shown in fig. 3, the three-dimensional memory includes: a semiconductor substrate 310;
a stacked structure 330 on the semiconductor substrate 310;
a channel hole 340 and a gate line groove 350 penetrating the stacked structure 330; a channel layer 341 is disposed in the channel hole 340, and a source 351 is disposed in the gate line groove 350;
and a silicon germanium epitaxial layer 320 connecting the channel layer 341 and the source 351.
In the embodiment of the present application, the silicon germanium epitaxial layer 320 is located on the semiconductor substrate 310, and the silicon germanium epitaxial layer 320 is in contact with the semiconductor substrate 310.
In the embodiment of the present application, a first space 360 is provided between the upper surface of the semiconductor substrate 310 and the stacked structure 330; the channel layer 341 penetrates the stacked-layer structure 330 and extends into the semiconductor substrate 310, the channel layer 341 having a portion corresponding to the first space 360 in a direction parallel to the semiconductor substrate 310; the silicon germanium epitaxial layer 320 contacts sidewalls of the portion of the channel layer 341. Note that the first space 360 corresponds to a structure formed in a gap between the stacked structure and the semiconductor substrate, which is left after the sacrificial layer is removed.
In the present embodiment, the channel hole 340 vertically penetrates the stacked structure 330 and extends into the semiconductor substrate 310. A portion of the channel layer 341 between the stacked-layer structure 330 and the semiconductor substrate 310 is exposed from a side surface of the channel hole 340 to be in contact with the silicon germanium epitaxial layer 320. And the silicon germanium epitaxial layer 320 is in contact with the semiconductor substrate 310, such that the silicon germanium epitaxial layer 320 conductively connects the channel layer 341 and the semiconductor substrate 310.
In the embodiment of the present invention, a source 351 is disposed in the gate line trench 350, the source 351 is in contact with a source contact region 352, and the source contact region 352 is in contact with the sige epitaxial layer 320. Thus, when the gate is turned on, a current path from the channel layer 341, the silicon germanium epitaxial layer 320, the semiconductor substrate 310, and the source contact region 352 to the source 351 is formed. It should be noted that the shape of the sige epitaxial layer 320 illustrated in fig. 3 in this embodiment is only an exemplary shape, and when the sige epitaxial layer 320 is formed in this embodiment, the sige epitaxial layer 320 only needs to cover the upper surface of the semiconductor substrate 310 and connect the channel layer 341 and the semiconductor substrate 310, and the sige epitaxial layer 320 is not required to cover the whole portion of the channel layer 341.
In the present embodiment, a high-k material layer 370 is deposited in the first space 360 to fill the first space 360.
In the embodiment of the present application, the silicon germanium epitaxial layer 320 extends from the sidewall of the channel layer 341 to at least below the source 351 along the upper surface of the semiconductor substrate 310.
In the embodiment of the present application, a sidewall structure 353 is formed in the gate line trench 350, and the sidewall structure 353 includes an oxide layer.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. A method of fabricating a three-dimensional memory, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, a sacrificial layer positioned on the semiconductor substrate, a laminated structure positioned on the sacrificial layer and a channel hole penetrating through the laminated structure and the sacrificial layer; a channel layer is formed in the channel hole, and the channel layer is provided with a part corresponding to the sacrificial layer along the direction parallel to the semiconductor substrate;
forming a gate line slot penetrating through the laminated structure to reach the sacrificial layer;
removing the sacrificial layer through the gate wire slot to expose the side wall of the portion of the channel layer and the upper surface of the semiconductor substrate;
forming a germanium-silicon epitaxial layer on the exposed sidewall of the channel layer and the upper surface of the semiconductor substrate through a selective epitaxial growth process;
and forming a source electrode in the grid wire groove, wherein the source electrode is in conductive contact with the germanium-silicon epitaxial layer.
2. The method of manufacturing a three-dimensional memory according to claim 1, wherein the channel hole side wall is formed with a functional layer that wraps the channel layer;
after removing the sacrificial layer through the gate wire trenches, the method further comprises:
removing a portion of the functional layer through the gate line trench to expose the portion of the channel layer.
3. The method of manufacturing a three-dimensional memory according to claim 2,
the functional layer of the channel hole sidewall includes an oxide layer-nitride layer-oxide layer radially inward of the channel hole.
4. The method of manufacturing a three-dimensional memory according to claim 1,
after forming the gate line trenches and before forming the germanium-silicon epitaxial layer, the method further comprises:
forming a side wall structure on the side wall of the grid wire groove;
and removing part of the side wall structure to expose the oxide layer in the side wall structure.
5. The method of manufacturing a three-dimensional memory according to claim 4,
the sidewall structure of the gate wire trench includes a nitride layer-oxide layer-nitride layer radially inward along the gate wire trench.
6. The method of manufacturing a three-dimensional memory according to claim 4, wherein the channel hole side wall is formed with a functional layer that wraps the channel layer;
the thickness of the side wall structure of the grid line groove is larger than that of the functional layer of the side wall of the channel hole.
7. The method of manufacturing a three-dimensional memory according to claim 4,
the thickness range of the side wall structure of the grid line groove is 20nm-50 nm.
8. The method of manufacturing a three-dimensional memory according to claim 1,
in the selective epitaxial growth process, silicon source gas and germanium source gas are used as deposition gases.
9. The method of manufacturing a three-dimensional memory according to claim 1,
the temperature of the selective epitaxial growth process is 400-800 ℃, and the air pressure is 1 mTorr-20 Torr.
10. The method of manufacturing a three-dimensional memory according to claim 1,
and the formed germanium-silicon epitaxial layer extends from the side wall of the channel layer to at least the position corresponding to the grid wire groove along the upper surface of the semiconductor substrate.
11. A three-dimensional memory, comprising:
a semiconductor substrate;
a stacked structure on the semiconductor substrate;
a channel hole and a grid line groove penetrating through the laminated structure; a channel layer is arranged in the channel hole, and a source electrode is arranged in the grid wire slot;
and the germanium-silicon epitaxial layer is connected with the channel layer and the source electrode.
12. The three-dimensional memory according to claim 11,
the germanium-silicon epitaxial layer is located on the semiconductor substrate and is in contact with the semiconductor substrate.
13. The three-dimensional memory according to claim 11,
a first interval is arranged between the upper surface of the semiconductor substrate and the laminated structure;
the channel layer penetrates through the laminated structure and extends into the semiconductor substrate, and the channel layer is provided with a part corresponding to the first interval along the direction parallel to the semiconductor substrate;
the silicon germanium epitaxial layer is in contact with a sidewall of the portion of the channel layer.
14. The three-dimensional memory according to claim 11,
the silicon germanium epitaxial layer extends from the side wall of the channel layer to at least below the source electrode along the upper surface of the semiconductor substrate.
15. The three-dimensional memory according to claim 11,
a side wall structure is formed in the grid wire groove and comprises an oxide layer.
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| US20200194416A1 (en) * | 2015-09-21 | 2020-06-18 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
| CN111326518A (en) * | 2018-12-14 | 2020-06-23 | 三星电子株式会社 | Semiconductor memory device with a memory cell having a plurality of memory cells |
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| CN111326518A (en) * | 2018-12-14 | 2020-06-23 | 三星电子株式会社 | Semiconductor memory device with a memory cell having a plurality of memory cells |
| CN110112134A (en) * | 2019-06-17 | 2019-08-09 | 长江存储科技有限责任公司 | 3D nand memory and forming method thereof |
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