CN207517677U - Array of capacitors structure - Google Patents
Array of capacitors structure Download PDFInfo
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- CN207517677U CN207517677U CN201721676396.7U CN201721676396U CN207517677U CN 207517677 U CN207517677 U CN 207517677U CN 201721676396 U CN201721676396 U CN 201721676396U CN 207517677 U CN207517677 U CN 207517677U
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- capacitor dielectric
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- 239000003990 capacitor Substances 0.000 title claims abstract description 146
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000010276 construction Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 150000001450 anions Chemical class 0.000 claims description 12
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 10
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 10
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 10
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 9
- 238000003491 array Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 473
- 238000000034 method Methods 0.000 description 31
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000000151 deposition Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 238000007254 oxidation reaction Methods 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 12
- 238000005137 deposition process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000000873 masking effect Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910017107 AlOx Inorganic materials 0.000 description 2
- 229910019897 RuOx Inorganic materials 0.000 description 2
- 229910018316 SbOx Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001768 cations Chemical class 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a kind of array of capacitors structure, and for array of capacitors structure setting in Semiconductor substrate, array of capacitors structure includes lower electrode layer, adhesion layer, capacitor dielectric layer and top electrode, and lower electrode layer is located in Semiconductor substrate；Adhesion layer is covered in inner surface and the outer surface of lower electrode layer, for improving the adhesion strength between lower electrode layer and capacitor dielectric layer, to prevent lower electrode layer from mutually being removed with capacitor dielectric layer；Capacitor dielectric layer is covered in inner surface and the outer surface of adhesion layer；Upper electrode layer is covered in the outer surface of capacitor dielectric layer.The array of capacitors structure of the utility model between lower electrode layer and capacitor dielectric layer by setting adhesion layer, the tackness between capacitor dielectric layer and lower electrode layer can be improved, so as to effectively avoid capacitor dielectric layer from lower electrode layer sur-face peeling, the reliability of capacitor dielectric layer is improved, the abnormal of leakage current is avoided to increase.
Description
Technical field
The utility model belongs to semiconductor devices and manufacturing field, more particularly to a kind of array of capacitors structure.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made of the storage unit of many repetitions.In the DRAM processing procedures of below 20nm, DRAM uses heap
The capacitor structure of stack, capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio to increase surface area, existing
Some capacitors include lower electrode layer, capacitor dielectric layer and upper electrode layer.In existing DRAM capacitor, used lower electricity
The material of pole layer is generally titanium nitride (TiN), and the material of capacitor dielectric layer is generally zirconium oxide (ZrOx), and titanium oxide capacitance is situated between
Tackness between matter layer and the smooth lower electrode layer of nitridation is poor, and capacitor dielectric layer easily occurs and is shelled from lower electrode layer surface
Fall the abnormal phenomenon of (peeling).And when capacitor dielectric layer is peeled off from lower electrode layer, then condenser leakage current is be easy to cause
Increase, and then device power consumption is caused to increase, even results in component failure.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of array of capacitors knots
Structure, for solving in capacitor of the prior art capacitor dielectric layer easily from leakage current caused by lower electrode layer sur-face peeling
The problem of increase, power consumption increase and lead to component failure.
In order to achieve the above objects and other related objects, the utility model provides a kind of array of capacitors structure, the electricity
For vessel array structure setting in Semiconductor substrate, the array of capacitors structure includes lower electrode layer, adhesion layer, capacitor dielectric
Layer and top electrode, wherein,
The lower electrode layer is located in the Semiconductor substrate；
The adhesion layer is covered in inner surface and the outer surface of the lower electrode layer, for improving the lower electrode layer and institute
The adhesion strength between capacitor dielectric layer is stated, to prevent the lower electrode layer from mutually being removed with the capacitor dielectric layer；
The capacitor dielectric layer is covered in inner surface and the outer surface of the adhesion layer；And
The upper electrode layer is covered in the outer surface of the capacitor dielectric layer.
Preferably, the lower electrode layer, the capacitor dielectric layer and the upper electrode layer include metal compound layer, institute
It states adhesion layer and includes metal oxide layer.
Preferably, the material of the lower electrode layer includes titanium nitride (TiN), and the material of the capacitor dielectric layer includes oxidation
Zirconium, the material of the adhesion layer include titanium oxide (TiOx).
Preferably, the ratio between the thickness of the adhesion layer and the thickness of the lower electrode layer are less than 2:3.
Preferably, the cross sectional shape of the lower electrode layer is U-shaped.
Preferably, multiple pads in memory structure of arrays, the lower electrode layer are formed in the Semiconductor substrate
Bottom lower surface be incorporated into the pad.
Preferably, the array of capacitors further includes support construction, is formed in the Semiconductor substrate and described in connecting
Lower electrode layer；The support construction includes top support layer, middle support layer and base layer support layer, the top support layer connection
The mouth periphery of the lower electrode layer, the middle support layer connect the intermediate position of the lower electrode layer, the base layer support
Layer connects the bottom periphery of the lower electrode layer.
Preferably, the edge of the support construction is heavy curtain waveform, and the corner of the support construction is arc-shaped.
Preferably, the cation element of the adhesion layer is taken from the surface metal element of the lower electrode layer and spontaneous
Into, the anion element of the adhesion layer differs the anion element of the lower electrode layer, make the adhesion layer with it is described under
It is combined between electrode layer for imporosity.
Preferably, the anion element of the adhesion layer is identical to the anion element of the capacitor dielectric layer.
The utility model also provides a kind of manufacturing method of array of capacitors structure, the manufacture of the array of capacitors structure
Method includes the following steps：
1) semi-conductive substrate is provided；
2) sacrificial layer being alternately superimposed on and support construction are formed in the upper surface of the Semiconductor substrate；
3) Patterned masking layer is formed in the upper surface of the sacrificial layer being alternately superimposed on and support construction, it is described graphical
Mask layer has multiple trepannings, for defining the position in capacitance hole and shape；
4) support construction and the sacrificial layer are etched according to the Patterned masking layer, in the support construction and
Capacitance hole is formed in the sacrificial layer；
5) in forming lower electrode layer in the capacitance hole, the support construction connects the lower electrode layer；
6) sacrificial layer is removed, wherein, the support construction retains on the semiconductor substrate；
7) adhesion layer is formed in the inner surface of the lower electrode layer and outer surface, wherein, under the adhesion layer covering is described
Electrode layer for the adhesion strength between the capacitor dielectric layer that improves the lower electrode layer and be subsequently formed, prevents the lower electrode
Layer is mutually removed with capacitor dielectric layer；
8) capacitor dielectric layer is formed in the inner surface of the adhesion layer and outer surface, wherein, the capacitor dielectric layer covering
The adhesion layer；And
9) upper electrode layer is formed in the outer surface of the capacitor dielectric layer, wherein, the upper electrode layer covers the capacitance
Dielectric layer.
Preferably, in step 1), multiple pads in memory structure of arrays are formed in the Semiconductor substrate；Step
2) support construction formed in includes top support layer, middle support layer and base layer support layer, the top support layer, institute
It states middle support layer and the base layer support layer is mutually separated with spacing, and be respectively positioned in the sacrificial layer up and down；In step 4), formed
The capacitance hole expose the pad.
Preferably, step 6) includes the following steps：
6-1) in forming the first opening in the top support layer, first opening exposes the sacrificial layer and is located at institute
State the first part between top support layer and the middle support layer；
6-2) according to the described first opening, the sacrificial layer is removed using wet-etching technology and is located at the top support layer
With the first part between the middle support layer；
6-3) in forming the second opening in the middle support layer, second opening exposes the sacrificial layer and is located at institute
State the second part between middle support layer and the Semiconductor substrate；And
6-4) according to the described second opening, the sacrificial layer is removed using wet-etching technology and is located at the middle support layer
Second part and the base layer support layer between the Semiconductor substrate corresponding part with the described second opening, in institute
It states and third opening is formed in base layer support layer.
Preferably, step 6-2) in, first opening only overlaps or with a capacitance hole described in one
First opening overlaps simultaneously with multiple capacitance holes；Step 6-4) in, one it is described second opening only with a capacitance
Hole overlaps or first opening overlaps simultaneously with multiple capacitance holes.
Preferably, in step 5), in formation titanium nitride layer in the electrode hole as the lower electrode layer；In step 7),
Titanium oxide layer is formed as the adhesion layer in the inner surface of the lower electrode layer and outer surface；In step 8), in the adherency
The inner surface of layer and outer surface form zirconium oxide layer as the capacitor dielectric layer.
Preferably, in step 7), during forming the adhesion layer, the thickness of the lower electrode layer of consumption is less than step
The 40% of the original depth of rapid 5) the middle lower electrode layer formed.
Preferably, in step 7), using O3Oxidation technology carries out oxidation processes to the lower electrode layer, in the lower electricity
The inner surface of pole layer and outer surface form the adhesion layer, and so that the adhesion layer is combined with the lower electrode layer imporosity.
Preferably, using O3During oxidation technology carries out oxidation processes to the lower electrode layer, processing pressure 0.1
~2 supports are held in the palm, treatment temperature is 200 DEG C~400 DEG C.
Preferably, in step 7), using low-pressure chemical vapor deposition process or atom layer deposition process in the lower electrode
The inner surface and outer surface of layer form the adhesion layer, and so that the adhesion layer is combined with the lower electrode layer imporosity.
Preferably, the oxygen source presoma used in low-pressure chemical vapor deposition process or atom layer deposition process includes O2Deng
Gas ions, H2O、O2、N2O or H2O2。
Preferably, the deposition pressure in low-pressure chemical vapor deposition process or atom layer deposition process is the support of 0.1 support~2,
Depositing temperature is 200 DEG C~400 DEG C.
The utility model also provides a kind of semiconductor memory device junction structure, and the semiconductor memory device junction structure is included as above
State the array of capacitors structure described in either a program.
As described above, the array of capacitors structure of the utility model, has the advantages that：
The array of capacitors structure of the utility model, can by setting adhesion layer between lower electrode layer and capacitor dielectric layer
To improve the tackness between capacitor dielectric layer and lower electrode layer, so as to which capacitor dielectric layer effectively be avoided to be shelled from lower electrode layer surface
From the reliability of raising capacitor dielectric layer avoids the abnormal of leakage current from increasing；
The manufacturing method of the array of capacitors structure of the utility model is by using low-pressure chemical vapor deposition process, atom
Layer depositing operation or O3Oxidation technology forms adhesion layer on lower electrode layer surface, compared to other techniques, on lower electrode layer surface
The compactness higher of the adhesion layer of formation, adhesion layer can be bonded with lower electrode layer with imporosity, and the tackness of the two is more preferable, so as to
Capacitor dielectric layer is further substantially reduced from the risk of lower electrode layer sur-face peeling, the reliability of capacitor dielectric layer is improved, avoids
The abnormal of leakage current increases.
Description of the drawings
Fig. 1 is shown as the flow chart for preparing array of capacitors structure provided in the utility model embodiment one.
Fig. 2 is shown as step 1) institute in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
The partial cross section structure diagram of presentation
Fig. 3 is shown as step 2) institute in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram of presentation.
Fig. 4 is shown as step 3) institute in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram of presentation.
Fig. 5 is shown as step 4) institute in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram of presentation.
Fig. 6 is shown as step 5) institute in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram of presentation.
Fig. 7 to Fig. 9 is shown as walking in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
The rapid structure diagram 6) presented, wherein, Fig. 9 is the vertical view of structure that step 6) obtains, and Fig. 8 is the AA ' directions along Fig. 9
Partial cross section's structure diagram.
Figure 10 to Figure 12 is shown as in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram that step 7) is presented.
Figure 13 to Figure 15 is shown as in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
Partial cross section's structure diagram that step 8) is presented.
Figure 16 is shown as step 9) in the manufacturing method of array of capacitors structure provided in the utility model embodiment one
The partial cross section's structure diagram presented.
Reference numerals explanation
21 Semiconductor substrates
211 pads
22 sacrificial layers
231 top support layers
232 middle support layers
233 base layer support layers
24 Patterned masking layers
241 trepannings
25 capacitance holes
26 lower electrode layers
261 adhesion layers
262 holes
27 capacitor dielectric layers
28 upper electrode layers
Specific embodiment
Illustrate the embodiment of the utility model below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Figure 16.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides provide a kind of manufacturing method of array of capacitors structure, the array of capacitors
The manufacturing method of structure includes the following steps：
1) semi-conductive substrate is provided；
2) sacrificial layer being alternately superimposed on and support construction are formed in the upper surface of the Semiconductor substrate；
3) Patterned masking layer is formed in the upper surface of the sacrificial layer being alternately superimposed on and support construction, it is described graphical
Mask layer has multiple trepannings, for defining the position in capacitance hole and shape；
4) support construction and the sacrificial layer are etched according to the Patterned masking layer, in the support construction and
Capacitance hole is formed in the sacrificial layer；
5) in forming lower electrode layer in the capacitance hole, the support construction connects the lower electrode layer；
6) sacrificial layer is removed, wherein, the support construction retains on the semiconductor substrate；
7) adhesion layer is formed in the inner surface of the lower electrode layer and outer surface, wherein, under the adhesion layer covering is described
Electrode layer for the adhesion strength between the capacitor dielectric layer that improves the lower electrode layer and be subsequently formed, prevents the lower electrode
Layer is mutually removed with capacitor dielectric layer；
8) capacitor dielectric layer is formed in the inner surface of the adhesion layer and outer surface, wherein, the capacitor dielectric layer covering
The adhesion layer；And
9) upper electrode layer is formed in the outer surface of the capacitor dielectric layer, wherein, the upper electrode layer covers the capacitance
Dielectric layer.
In step 1), S1 steps and Fig. 2 in please referring to Fig.1 provide semi-conductive substrate 21.
As an example, memory array structure is formed in the Semiconductor substrate 21, the memory array structure includes
Multiple pads 211.The memory array structure has further included transistor character line (Word line) and bit line
(Bitline), the pad 211 is electrically connected the transistor source in the memory array structure.
As an example, the pad 211 can with but be not limited only in six square arrays arrange, with the capacitor battle array subsequently made
The arrangement of array structure is corresponding.
Be isolated between the pad 211 by wall, the material of the wall can be silicon nitride (SiN),
Silica (SiO2), aluminium oxide (Al2O3) in any one or any two or more combinations, in the present embodiment, between described
The material selection of interlayer is SiN.
In step 2), S2 steps and Fig. 3 in please referring to Fig.1 are formed in the upper surface of the Semiconductor substrate 21 and are handed over
For stacked sacrificial layer 22 and support construction.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
Technique (Chemical Vapor Deposition) forms the sacrificial layer 22 and support construction.
As an example, the sacrificial layer 22 is different from the material of the support construction, and described in same etching processing procedure
The etch rate of sacrificial layer 22 is different from the etch rate of the support construction, is embodied in same etching processing procedure, described
The etch rate of sacrificial layer 22 is far longer than the etch rate of the support construction so that when the sacrificial layer 22 is completely removed
When, the support construction is almost fully retained.
Preferably, in the present embodiment, the sacrificial layer 22 can be polysilicon layer, and the material of the support construction can wrap
It includes but is not limited only to silicon nitride.
As an example, the support construction includes top support layer 231, the middle support layer 232 and base layer support layer
233, the top support layer 231, the middle support layer 232 and the base layer support layer are mutually separated with spacing about 233, and
In the sacrificial layer 22.
In step 3), S3 steps and Fig. 4 in please referring to Fig.1, in the sacrificial layer 22 being alternately superimposed on and support knot
The upper surface of structure forms Patterned masking layer 24, and the Patterned masking layer 24 has multiple trepannings 241, for defining capacitance hole
Position and shape.
As an example, it first, forms photoresist in the upper surface of the sacrificial layer 22 being alternately superimposed on and support construction and makees
For mask layer, certainly, mask layer (for example, silicon nitride hard mask layer etc. of other materials can also be formed in other examples
Deng)；Then, it is using photoetching process that the mask layer is graphical, to obtain that there is the pattern mask of the trepanning 241
Layer 24.
As an example, the opening 241 can be arranged along the surface of the Patterned masking layer 24 in six square arrays.
In step 4), S4 steps and Fig. 5 in please referring to Fig.1 etch the branch according to the Patterned masking layer 24
Support structure and the sacrificial layer 22, to form capacitance hole 25 in the support construction and the sacrificial layer 22.
As an example, the specific method of step 4) is：According to the Patterned masking layer 24 using dry etch process, wet
Method etching technics or dry etch process etch the support construction and the sacrifice with the technique that wet-etching technology is combined
Layer 22, to form the capacitance hole 25 of up/down perforation, the capacitance hole 25 in the support construction and the sacrificial layer 22
The pad 211 is exposed, as shown in figure 11；
In step 5), S5 steps and Fig. 6 in please referring to Fig.1, in formation lower electrode layer 26, institute in the capacitance hole 25
It states support construction and connects the lower electrode layer 26.
As an example, first, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor
Depositing operation (Chemical Vapor Deposition) is in the side wall in the capacitance hole 25 and bottom and the sacrificial layer
22 upper surface deposition lower electrode material layer, the material of the lower electrode material layer are included in metal nitride and metal silicide
The compound that is formed of one or two, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium
Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy), it is preferable that described in the present embodiment
The material of lower electrode material layer is titanium nitride；Then, then using etching technics removal positioned at the institute of 22 upper surface of sacrificial layer
State lower electrode material layer, reservation under the side wall in the capacitance hole 25 and the lower electrode material layer of bottom are described
Electrode layer 26.
As an example, the bottom lower surface of the lower electrode layer 26 is incorporated into the pad 211.
In step 6), S6 steps and Fig. 7 to Fig. 9 in please referring to Fig.1 remove the sacrificial layer 22, wherein, the branch
Support structure is retained in the Semiconductor substrate 21.
As an example, step 6) includes the following steps：
6-1) in forming the first opening in the top support layer 231, first opening exposes the sacrificial layer 22
First part between the top support layer 231 and the middle support layer 232；
6-2) according to the described first opening, the sacrificial layer 22 is removed using wet-etching technology and is located at top layer support
The first part between layer 231 and the middle support layer 232, as shown in Figure 7；
6-3) in forming the second opening in the middle support layer 232, second opening exposes the sacrificial layer 22
Second part between the middle support layer 232 and the Semiconductor substrate 21；
6-4) according to the described second opening, the sacrificial layer 22 is removed using wet-etching technology and is located at the intermediate supports
The second part between layer 232 and the Semiconductor substrate 21, as can be seen from figures 8 and 9.
As an example, step 6-2) and step 6-3) between further include in the upper surface of the top support layer 231 deposit
The step of support layer material, thickens the top support layer 231.This is because in step 6-2) during, the top
Layer supporting layer 231 can be removed a part, in order to prevent during subsequent corrosion the top support layer 231 cut through and
Ensuring at the upper strata support 31 has enough support strengths, needs in step 6-2) and step 6-3) between add in described
At the support of upper strata the step of 231 upper surface depositing support layer material.
As an example, step 6-1) in, first opening is only overlapping or one with a capacitance hole 25
First opening is overlapping with multiple capacitance holes 25 simultaneously (as shown in figure 9, Fig. 9 is with first opening and three
The capacitance hole 25 is overlapping as example)；Step 6-2) in, second opening is only handed over a capacitance hole 25
Folded or first opening is overlapping with multiple capacitance holes 25 simultaneously.
In step 7), S7 steps and Figure 10 to Figure 12 in please referring to Fig.1, in the inner surface of the lower electrode layer 26 and outer
Surface forms adhesion layer 261, wherein, the adhesion layer 261 covers the lower electrode layer 26, for improving the lower electrode layer 26
Adhesion strength between the capacitor dielectric layer that is subsequently formed, prevents the lower electrode layer 26 from being shelled with 27 phase of capacitor dielectric layer
From.
As an example, the adhesion layer 261 can be the metal oxide layer of contained metal in the lower electrode layer 26, example
Such as, when the material of the lower electrode layer 26 is titanium nitride, the material of the adhesion layer 261 is titanium oxide layer.
In one example, physical vaporous deposition may be used to be formed in the inner surface of the lower electrode layer 26 and outer surface
The adhesion layer 261；Specifically, the structure that step 6) obtains can be placed in physical gas-phase deposition reaction chamber, lead to
It crosses the techniques such as sputtering and forms the adhesion layer 261 in the inner surface of the lower electrode layer 26 and outer surface.
In another example, chemical vapour deposition technique may be used in the inner surface of the lower electrode layer 26 and outer surface shape
Into the adhesion layer 261；Specifically, the structure that step 6) obtains can be placed in chemical vapor deposition method reaction chamber,
Source metal presoma and oxygen source presoma, the source metal presoma and the oxygen source presoma are passed through into the reaction chamber
It reacts to each other under the conditions of certain pressure and temperature, it is described viscous to be formed in the inner surface of the lower electrode layer 26 and outer surface
Attached layer 261.
Using above-mentioned physical gas-phase deposition or chemical vapor deposition method in the inner surface of the lower electrode layer 26 and
Outer surface is formed after the adhesion layer 261, partial enlarged view such as Figure 11 of the lower electrode layer 26 and 261 faying face of adhesion layer
It is shown, using above-mentioned physical gas-phase deposition or chemical vapor deposition method in the inner surface and appearance of the lower electrode layer 26
During face forms the adhesion layer 261, due to the lower electrode layer 26 and it is not involved in forming the anti-of the adhesion layer 261
Should, and the surface of the lower electrode layer 26 cannot accomplish absolutely smooth, the adhesion layer 261 of formation and the lower electrode layer 26
Between have hole 262 and exist, the adhesion strength of the lower electrode layer 26 and the adhesion layer 261 is limited, can not reach best
The effect for increasing adhesion strength therebetween.But using above-mentioned physical gas-phase deposition or chemical vapor deposition method in institute
It states the inner surface of lower electrode layer 26 and outer surface forms the adhesion layer 261 and performs subsequent step again later, it still can be certain
Improve the tackness between capacitor dielectric layer 27 and lower electrode layer 26 in degree, so as to effectively avoid capacitor dielectric layer from lower electrode
26 sur-face peeling of layer improve the reliability of capacitor dielectric layer 27, and the abnormal of leakage current is avoided to increase.
In another example, low-pressure chemical vapor deposition process or atom layer deposition process may be used in the lower electrode
The inner surface of layer 26 and outer surface form the adhesion layer 261；Specifically, the structure that step 6) obtains can be placed in low pressure
Gas-phase deposition reaction chamber or atom layer deposition process reaction chamber are learned, to reaction chamber under preset pressure and temperature condition
Interior is passed through oxygen source presoma so that the lower electrode layer 26 is with the oxygen source forerunner precursor reactant in the lower electrode layer 26
Outer surface and inner surface form the adhesion layer 261, and the adhesion layer 261 is tied with 26 imporosity of lower electrode layer
It closes.
As an example, the oxygen source presoma includes O2Plasma, H2O、O2、N2O or H2O2；Deposition in deposition process
Pressure is the support of 0.1 support~2, and depositing temperature is 200 DEG C~400 DEG C.
In another example, O may be used3Oxidation technology carries out oxidation processes to the lower electrode layer 26, in described
The inner surface of lower electrode layer 26 and outer surface form the adhesion layer 261, and cause the adhesion layer 261 and the lower electrode layer
26 imporosities combine.Specifically, the structure that step 6) obtains can be placed in O3In environment, so that institute under the conditions of certain temperature
State lower electrode layer 26 and O3It reacts, to form the adhesion layer 261 in the outer surface of the lower electrode layer 26 and inner surface.
By taking the lower electrode layer 26 is titanium nitride as an example, in O3It can occur to react as follows in oxidation technology：
TiN(s)+O3(g)→TiO2(s)+NO(s)
Specifically, a reaction chamber can will be placed in structure that step 6) obtains, O has been passed through in the reaction chamber3,
The indoor pressure of reaction chamber is set as the support of 0.1 support~2, so that the titanium nitride under 200 DEG C~400 DEG C for the treatment of temperature
Lower electrode layer and the O3React using the outer surface of the titanium nitride lower electrode layer and inner surface formed titanium oxide as
The adhesion layer 261.
As an example, due to above-mentioned using low-pressure chemical vapor deposition process, atom layer deposition process or O3Oxidation technology
The conduct of lower electrode layer 26 during the inner surface of the lower electrode layer 26 and outer surface form the adhesion layer 261
The source metal for forming the adhesion layer 261 participates in reaction, during the adhesion layer 261 is formed, the lower electrode layer 26
It can be consumed, in order to ensure not influencing the performance of the lower electrode layer 26, during the adhesion layer 261 is formed, disappear
The thickness of the lower electrode layer 26 consumed is less than the 40% of the original depth of the lower electrode layer 26 formed in step 5)；More
For preferably, the thickness of the lower electrode layer 26 consumed is the initial thickness of the lower electrode layer 26 formed in step 5)
10%, 20% or 30% etc. of degree.
Using low-pressure chemical vapor deposition process, atom layer deposition process or O3Oxidation technology is in the lower electrode layer 26
Inner surface and outer surface are formed after the adhesion layer 261, the partial enlargement of the lower electrode layer 26 and 261 faying face of adhesion layer
Figure is as shown in figure 12, although the surface of the lower electrode layer 26 cannot accomplish it is absolutely smooth, due to using low pressure chemical phase
Depositing operation, atom layer deposition process or O3Oxidation technology forms described viscous in the inner surface of the lower electrode layer 26 and outer surface
During attached layer 261, the lower electrode layer 26 participates in reaction, the institute of formation as the source metal for forming the adhesion layer 261
261 compactness higher of adhesion layer is stated, imporosity is combined between the adhesion layer 261 and the lower electrode layer 26, the fitting of the two
Closer, tackness is more preferable, so as to further substantially reduce the capacitor dielectric layer 27 being subsequently formed from 26 table of lower electrode layer
Face is removed, and improves the reliability of capacitor dielectric layer 27, and the abnormal of leakage current is avoided to increase.
In step 8), S8 steps and Figure 13 to Figure 15 in please referring to Fig.1, in the adhesion layer 261 inner surface and
Outer surface forms capacitor dielectric layer 27, wherein, the capacitor dielectric layer 27 covers the adhesion layer 261.
As an example, the material of the capacitor dielectric layer 27 can be selected as high K dielectric material, to improve unit area electricity
The capacitance of container, including one kind or above-mentioned material in ZrOx (zirconium oxide), HfOx, ZrTiOx, RuOx, SbOx, AlOx
Two or more formed laminations in formed group, it is preferable that in the present embodiment, the material of the capacitor dielectric layer 27 is
ZrOx。
It is formed after the capacitor dielectric layer 27, the lower electrode layer 26, the adhesion layer 261 and the capacitor dielectric layer
The partial enlarged view of 27 faying faces is as shown in Figure 14 and Figure 15.
In step 9), S9 steps and Figure 16 in please referring to Fig.1 are formed in the outer surface of the capacitor dielectric layer 27
Electrode layer 28, wherein, the upper electrode layer 28 covers the capacitor dielectric layer 27.
As an example, the material of the upper electrode layer 28 can include tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon,
One kind or above-mentioned material in p-type polysilicon form two or more the formed laminations in group；Preferably, the present embodiment
In, the material of the upper electrode layer 28 is titanium nitride.
Embodiment two
Incorporated by reference to embodiment one with continued reference to Figure 16, the present embodiment also provides a kind of array of capacitors structure, the capacitance
Device array structure may be used but be not limited only to the manufacturing method manufacture of the array of capacitors structure described in embodiment one and obtain
It arriving, the array of capacitors structure includes lower electrode layer 26, adhesion layer 261, capacitor dielectric layer 27 and top electrode 28, wherein, institute
Lower electrode layer 26 is stated to be located in the Semiconductor substrate 21；The adhesion layer 261 is covered in the inner surface of the lower electrode layer 26
And outer surface, for improving the adhesion strength between the lower electrode layer 26 and the capacitor dielectric layer 27, to prevent the lower electricity
Pole layer 26 is removed with 27 phase of capacitor dielectric layer；The capacitor dielectric layer 27 be covered in the adhesion layer 261 inner surface and
Outer surface；And the upper electrode layer 28 is covered in the outer surface of the capacitor dielectric layer 27.
As an example, being formed with memory array structure in the Semiconductor substrate 21, the memory array structure includes
Multiple pads 211, the upper surface of the pad 211 are engaged in the lower surface of the lower electrode layer 26.The memory array structure
Transistor character line (Word line) and bit line (Bitline) are further included, the pad 211 is electrically connected the memory number
Transistor source in group structure.
As an example, the pad 211 can with but be not limited only in six square arrays arrange, with the capacitor battle array subsequently made
The arrangement of array structure is corresponding.
Be isolated between the pad 211 by wall, the material of the wall can be silicon nitride (SiN),
Silica (SiO2), aluminium oxide (Al2O3) in any one or any two or more combinations, in the present embodiment, between described
The material selection of interlayer is SiN.
As an example, the material of the lower electrode layer 26 includes one or both of metal nitride and metal silicide
The compound formed, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide
(Titanium Silicide), silicon titanium nitride (TiSixNy)；Preferably, in the present embodiment, the material of the lower electrode layer 26
For titanium nitride.
As an example, the adhesion layer 261 can be but be not limited only to titanium oxide.The thickness of the adhesion layer 261 and institute
The ratio between thickness of lower electrode layer 26 is stated less than 2:3.
As an example, the array of capacitors structure further includes support construction, the support construction, which is formed in, described partly to be led
In body substrate 21 and connect the lower electrode layer 26；The support construction includes top support layer 231, the middle support layer
232 and base layer support layer 233, the top support layer 231, the middle support layer 232 and the base layer support layer are about 233
Spacing is mutually separated with, is respectively positioned in the sacrificial layer 22.Specifically, the top supporting layer 231 connects the lower electrode layer 26
Mouth periphery, and perpendicular to the U-shaped side wall extending direction of the lower electrode layer 26, the middle support layer 232 connect it is described under
The intermediate position of electrode layer 26, the base layer support layer 233 connect the bottom periphery of the lower electrode layer 26.
As an example, the material of the top support layer 231, the middle support layer 232 and the base layer support layer 233
It all can be silicon nitride layer.
As an example, the material of the capacitor dielectric layer 27 includes high K medium material, to improve unit-area capacitance device
Capacitance is formed including one kind in ZrOx (zirconium oxide), HfOx, ZrTiOx, RuOx, SbOx, AlOx or above-mentioned material
It is two or more in group, it is preferable that in the present embodiment, the material of the capacitor dielectric layer 27 is ZrOx；The capacitor battle array
The thickness of row is 1 μm~1.5 μm.
As an example, the cation element of the adhesion layer 261 is taken from the surface metal element of the lower electrode layer 26
And self-generating, the anion element of the adhesion layer 261 differ the anion element of the lower electrode layer 26, make the adherency
It is combined between layer 261 and the lower electrode layer 26 for imporosity.
As an example, the anion element of the adhesion layer 261 is identical to the anion element of the capacitor dielectric layer 27.
Partial enlarged view such as Figure 15 institutes of the lower electrode layer 26, adhesion layer 261 and 27 faying face of capacitor dielectric layer
Show, although the surface of the lower electrode layer 26 cannot accomplish absolutely it is smooth, due to using low-pressure chemical vapor deposition process, original
Sublayer depositing operation or O3Oxidation technology forms the mistake of the adhesion layer 261 in the inner surface of the lower electrode layer 26 and outer surface
Cheng Zhong, the lower electrode layer 26 participate in reaction, the adhesion layer 261 of formation as the source metal for forming the adhesion layer 261
Compactness higher, imporosity is combined between the adhesion layer 261 and the lower electrode layer 26, and the fitting of the two is closer, sticks together
Property it is more preferable, so as to further substantially reduce the capacitor dielectric layer 27 that is subsequently formed from 26 sur-face peeling of lower electrode layer, improve
The reliability of capacitor dielectric layer 27 avoids the abnormal of leakage current from increasing.
As an example, the material of the upper electrode layer 28 can include tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon,
One kind or above-mentioned material in p-type polysilicon form two or more the formed laminations in group；Preferably, the present embodiment
In, the material of the upper electrode layer 28 is titanium nitride.
As an example, the edge of the support construction is heavy curtain waveform, and the corner of the support construction is arc-shaped；
Specifically, the edge that can be only the top support layer 231 is heavy curtain waveform, and the corner of the top support layer 231
To be arc-shaped, can also the top support layer 231, the middle support layer 232 and the base layer support layer 233 edge it is equal
For heavy curtain waveform, and corner is arc-shaped.The edge of the support construction is set as heavy curtain waveform, can be improved not
With the stress problem that material layer stacks, the reliability of device can be improved.
Embodiment three
The present embodiment also provides a kind of semiconductor memory device junction structure, and the semiconductor memory device junction structure is included as implemented
Array of capacitors structure described in example two, the concrete structure of the array of capacitors structure please refer to embodiment two, herein not
Tire out again and state.
As an example, the semiconductor memory device junction structure can be but be not limited only to dynamic RAM (DRAM).
In conclusion the array of capacitors structure of the utility model, the array of capacitors structure setting is served as a contrast in semiconductor
On bottom, the array of capacitors structure includes lower electrode layer, adhesion layer, capacitor dielectric layer and top electrode, wherein, the lower electrode
Layer is located in the Semiconductor substrate；The adhesion layer is covered in inner surface and the outer surface of the lower electrode layer, for improving
Adhesion strength between the lower electrode layer and the capacitor dielectric layer prevents the lower electrode layer from mutually being shelled with the capacitor dielectric layer
From；The capacitor dielectric layer is covered in inner surface and the outer surface of the adhesion layer；And the upper electrode layer is covered in the electricity
Hold the outer surface of dielectric layer.The array of capacitors structure of the utility model between lower electrode layer and capacitor dielectric layer by setting
Adhesion layer can improve the tackness between capacitor dielectric layer and lower electrode layer, so as to effectively avoid capacitor dielectric layer from lower electricity
Pole layer surface stripping improves the reliability of capacitor dielectric layer, the abnormal of leakage current is avoided to increase；The capacitor battle array of the utility model
The manufacturing method of array structure is by using low-pressure chemical vapor deposition process, atom layer deposition process or O3Oxidation technology is in lower electricity
Pole layer surface forms adhesion layer, compared to other techniques, in the compactness higher for the adhesion layer that lower electrode layer surface is formed, adherency
Layer can be bonded with lower electrode layer with imporosity, and the tackness of the two is more preferable, so as to further substantially reduce capacitor dielectric layer under
The risk of electrode layer surface stripping improves the reliability of capacitor dielectric layer, and the abnormal of leakage current is avoided to increase.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (11)
1. a kind of array of capacitors structure, which is characterized in that the array of capacitors structure setting is described in Semiconductor substrate
Array of capacitors structure includes lower electrode layer, adhesion layer, capacitor dielectric layer and top electrode, wherein,
The lower electrode layer is located in the Semiconductor substrate；
The adhesion layer is covered in inner surface and the outer surface of the lower electrode layer, for improving the lower electrode layer and the electricity
Hold the adhesion strength between dielectric layer, to prevent the lower electrode layer from mutually being removed with the capacitor dielectric layer；
The capacitor dielectric layer is covered in inner surface and the outer surface of the adhesion layer；And
The upper electrode layer is covered in the outer surface of the capacitor dielectric layer.
2. array of capacitors structure according to claim 1, it is characterised in that：The lower electrode layer, the capacitor dielectric
Layer and the upper electrode layer include metal compound layer, the adhesion layer includes metal oxide layer.
3. array of capacitors structure according to claim 2, it is characterised in that：The material of the lower electrode layer includes nitridation
Titanium (TiN), the material of the capacitor dielectric layer include zirconium oxide, and the material of the adhesion layer includes titanium oxide (TiOx).
4. array of capacitors structure according to claim 1, it is characterised in that：The thickness of the adhesion layer and the lower electricity
The ratio between thickness of pole layer is less than 2:3.
5. array of capacitors structure according to claim 1, it is characterised in that：The cross sectional shape of the lower electrode layer is U
Type.
6. array of capacitors structure according to claim 1, it is characterised in that：It is formed in the Semiconductor substrate multiple
Pad in memory structure of arrays, the bottom lower surface of the lower electrode layer are engaged in the pad.
7. array of capacitors structure according to claim 1, it is characterised in that：The array of capacitors further includes support knot
Structure is formed in the Semiconductor substrate and connects the lower electrode layer；The support construction includes top support layer, intermediate branch
Layer and base layer support layer are supportted, the top support layer connects the mouth periphery of the lower electrode layer, the middle support layer connection
The intermediate position of the lower electrode layer, the base layer support layer connect the bottom periphery of the lower electrode layer.
8. array of capacitors structure according to claim 7, it is characterised in that：The edge of the support construction is heavy curtain wave
Shape wave, and the corner of the support construction is arc-shaped.
9. array of capacitors structure according to any one of claim 1 to 8, it is characterised in that：The sun of the adhesion layer
Ion elements are taken from the surface metal element of the lower electrode layer and self-generating, the anion element of the adhesion layer differ
The anion element of the lower electrode layer makes to be combined for imporosity between the adhesion layer and the lower electrode layer.
10. array of capacitors structure according to claim 9, it is characterised in that：The anion element phase of the adhesion layer
It is same as the anion element of the capacitor dielectric layer.
11. a kind of semiconductor memory device junction structure, which is characterized in that the semiconductor memory device junction structure includes such as claim
Array of capacitors structure described in 1.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336068A (en) * | 2017-12-06 | 2018-07-27 | 睿力集成电路有限公司 | Array of capacitors structure and its manufacturing method |
| CN113394162A (en) * | 2020-03-12 | 2021-09-14 | 长鑫存储技术有限公司 | Capacitor array structure and forming method thereof |
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2017
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336068A (en) * | 2017-12-06 | 2018-07-27 | 睿力集成电路有限公司 | Array of capacitors structure and its manufacturing method |
| CN113394162A (en) * | 2020-03-12 | 2021-09-14 | 长鑫存储技术有限公司 | Capacitor array structure and forming method thereof |
| WO2021179926A1 (en) * | 2020-03-12 | 2021-09-16 | 长鑫存储技术有限公司 | Capacitor array structure and forming method therefor |
| US11925012B2 (en) | 2020-03-12 | 2024-03-05 | Changxin Memory Technologies, Inc. | Capacitor array structure and method for forming the same |
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