CN108538835B - Capacitor array structure and preparation method thereof - Google Patents
Capacitor array structure and preparation method thereof Download PDFInfo
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- CN108538835B CN108538835B CN201810466991.0A CN201810466991A CN108538835B CN 108538835 B CN108538835 B CN 108538835B CN 201810466991 A CN201810466991 A CN 201810466991A CN 108538835 B CN108538835 B CN 108538835B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 156
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- -1 nitrogen ion Chemical class 0.000 claims abstract description 89
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 43
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 34
- 239000012535 impurity Substances 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 30
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- 239000010937 tungsten Substances 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 12
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- 239000002243 precursor Substances 0.000 claims description 7
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 7
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910000410 antimony oxide Inorganic materials 0.000 claims description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 6
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 claims description 6
- ZARVOZCHNMQIBL-UHFFFAOYSA-N oxygen(2-) titanium(4+) zirconium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4] ZARVOZCHNMQIBL-UHFFFAOYSA-N 0.000 claims description 6
- 230000009471 action Effects 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 229910001510 metal chloride Inorganic materials 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 7
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000006227 byproduct Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910018316 SbOx Inorganic materials 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
Abstract
The invention provides a capacitor array structure and a preparation method thereof, wherein the method comprises the following steps: 1) Providing a semiconductor substrate, and forming a laminated structure on the semiconductor substrate; 2) Forming a patterned mask layer on the laminated structure, and etching a plurality of capacitor holes in the laminated structure based on the patterned mask layer; 3) Forming a lower electrode layer at the bottom and the side wall of the capacitor hole, wherein the support layer is connected with the lower electrode layer; 4) Removing the sacrificial layer; 5) Performing a nitrogen ion plasma diffusion process on the lower electrode layer, wherein nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer; 6) And forming a capacitance medium layer on the inner surface and the outer surface of the lower electrode layer, and forming an upper electrode layer on the outer surface of the capacitance medium layer. The lower electrode layer is subjected to nitrogen ion plasma diffusion process treatment, so that the electric connection stability and the charge storage capacity of the capacitor are effectively improved, and the leakage rate of the capacitor is reduced.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a preparation method of a capacitor array.
Background
Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory device commonly used in computers and is composed of a number of repeated memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, and the source electrode of the transistor is connected with the capacitor; the voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line or writing the data information into the capacitor through the bit line for storage. With the continuous evolution of the DRAM process, the integration level is continuously improved, the device size is continuously reduced, in the current DRAM process below 20nm, the DRAM adopts a stacked Capacitor structure, and the Capacitor (Capacitor) is in a vertical cylindrical shape with high aspect ratio so as to increase the surface area, and comprises a lower electrode layer connected with the substrate, a Capacitor dielectric layer deposited on the lower electrode layer and an upper electrode layer deposited on the Capacitor dielectric layer.
However, in the fabrication process of the existing DRAM capacitor structure, the byproduct chloride ions are generated at the same time when the lower electrode layer of the capacitor is formed by deposition. For example, as shown in fig. 1, the most commonly used deposition method of the bottom electrode layer is to introduce titanium chloride and ammonia gas into the reaction chamber, wherein the titanium chloride gas is adsorbed on the surface of the substrate, and then the ammonia gas reacts with the titanium chloride gas to form a titanium nitride bottom electrode layer on the substrate, and meanwhile, byproduct chloride ions are also generated. The impurity chloride ions are doped into the lower electrode layer of the capacitor, so that the lower electrode layer is easily peeled off from the substrate, and the electrical connection stability of the capacitor is reduced; on the other hand, the chlorine ions and the hydrogen ions are combined to generate strong acid which can corrode the lower electrode layer, so that the leakage rate of the capacitor is improved; and finally, the purity of the lower electrode material is seriously reduced, so that the resistance of the lower electrode is increased, and when the capacitance dielectric layer is deposited, oxygen element in the capacitance dielectric layer is easy to dip into the lower electrode layer, so that the K (dielectric constant) value of the capacitance dielectric layer is reduced, and the capacity of the capacitance for storing charges is reduced.
Therefore, it is necessary to provide a method for manufacturing a capacitor array to solve the problems of the prior art that the stability of electrical connection of the capacitor is reduced, the leakage rate of the capacitor is increased, and the capacity of the capacitor to store charges is reduced due to the incorporation of byproduct chloride ions into the lower electrode layer when the lower electrode layer of the capacitor is formed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a capacitor array structure and a method for manufacturing the same, which are used for solving the problems of the prior art that when a lower electrode layer of a capacitor is formed, chloride ions, which are by-products formed, are doped into the lower electrode layer, resulting in a decrease in the stability of electrical connection of the capacitor, an increase in the leakage rate of the capacitor, and a decrease in the capacity of the capacitor to store charges.
To achieve the above and other related objects, the present invention provides a method for manufacturing a capacitor array structure, comprising the steps of:
1) Providing a semiconductor substrate, and forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a supporting layer and a sacrificial layer which are alternately laminated;
2) Forming a patterned mask layer on the laminated structure, and etching a plurality of capacitor holes in the laminated structure based on the patterned mask layer;
3) Forming a lower electrode layer at the bottom and the side wall of the capacitor hole, wherein the support layer is connected with the lower electrode layer;
4) Removing the sacrificial layer, wherein the supporting layer remains on the semiconductor substrate;
5) Performing a nitrogen ion plasma diffusion process on the lower electrode layer, wherein nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer;
6) And forming a capacitance medium layer on the inner surface and the outer surface of the lower electrode layer, wherein the capacitance medium layer covers the lower electrode layer, and forming an upper electrode layer on the outer surface of the capacitance medium layer, and the upper electrode layer covers the capacitance medium layer.
Preferably, the lower electrode layer formed in step 3) contains impurity chloride ions, the nitrogen ions diffuse into the inner and outer surfaces of the lower electrode layer in step 5), and the impurity chloride ions are extruded to remove the impurity chloride ions.
Preferably, the bottom electrode layer is formed on the bottom and the side wall of the capacitor hole by adopting a chemical vapor deposition method, wherein a precursor of the chemical vapor deposition method comprises metal chloride.
Further, the material of the lower electrode layer includes at least one of the group consisting of titanium nitride, titanium oxide, titanium carbide, and tungsten.
Further, the bottom electrode layer comprises a titanium nitride layer, the titanium nitride layer is formed at the bottom and the side wall of the capacitor hole by adopting a chemical vapor deposition method, and the chemical vapor deposition method comprises the following steps: TICl 4 +NH 3 →TIN+HCl+N 2 Wherein the precursor TICl 4 The lower electrode layer is made to contain the impurity chloride ions.
Preferably, the laminated structure includes a bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer, and a top supporting layer laminated in this order.
Further, the material of the first sacrificial layer comprises boron-phosphorus doped silicon oxide (BPSG), and the material of the second sacrificial layer comprises an oxide, wherein the first sacrificial layer comprises an upper first sacrificial layer and a lower first sacrificial layer, and the phosphorus ion doping concentration of the lower first sacrificial layer is greater than the phosphorus ion doping concentration of the upper first sacrificial layer.
Further, the weight percentage of the phosphorus ion content of the lower layer first sacrificial layer is between 3 and 5 percent, the weight percentage of the boron ion content is between 2 and 7 percent, the weight percentage of the phosphorus ion content of the upper layer first sacrificial layer is between 3 and 5 percent, and the weight percentage of the boron ion content is between 5 and 10 percent.
Preferably, step 2) comprises the steps of:
2-1) sequentially forming a plurality of barrier layers on the structure obtained in the step 1);
2-2) forming a first etching pattern on the structure obtained in the step 2-1) along the first direction by using a pitch multiplication process;
2-3) forming a second etching pattern on the structure obtained in the step 2-2) along a second direction by using a space multiplication process, so as to obtain a double-layer etching pattern, wherein the first direction and the second direction have included angles;
2-4) etching the area outside the overlapping area of the double-layer etching pattern to form the patterned mask layer.
Further, the multi-layer barrier layer sequentially comprises a polysilicon barrier layer, an oxide barrier layer and a carbide barrier layer; and, the step 2-4) comprises the following steps:
2-4-1) etching the area except the overlapping area of the area where the double-layer etching pattern is positioned to form a plurality of openings of the capacitor array structure;
2-4-2) etching the polysilicon barrier layer, the oxide barrier layer and the silicide barrier layer along the opening in sequence to form the patterned mask layer.
Further, the oxide barrier layer includes a silicon oxide barrier layer.
Preferably, step 4) comprises the steps of:
4-1) forming a first opening in the top support layer to expose the second sacrificial layer;
4-2) removing the second sacrificial layer by adopting a wet etching process based on the first opening;
4-3) forming a second opening in the intermediate support layer to expose the first sacrificial layer;
4-4) removing the first sacrificial layer by adopting a wet etching process based on the second opening.
Further, the wet etching solution in step 4-2) contains 30% -60% hydrofluoric acid, and the wet etching solution in step 4-4) contains 30% -60% hydrofluoric acid.
Further, in step 4-1), one of the first openings overlaps only one of the capacitor holes, or one of the first openings overlaps a plurality of the capacitor holes at the same time; in step 4-3), one of the second openings overlaps only one of the capacitor holes, or one of the second openings overlaps a plurality of the capacitor holes at the same time.
Further, one of the first openings overlaps three of the capacitor holes at the same time, and one of the second openings overlaps three of the capacitor holes at the same time.
Preferably, the material of the support layer comprises at least one of the group consisting of silicon nitride and silicon oxynitride, the material of the upper electrode layer comprises at least one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide and tungsten, and the material of the capacitance medium layer comprises at least one of the group consisting of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.
Further, step 5) comprises the steps of:
5-1) placing the structure obtained in the step 4) in a nitrogen ion generating device;
5-2) introducing a nitrogen ion gas source into the nitrogen ion generating device, generating nitrogen ions through the action of microwaves, and enabling the nitrogen ions to enter the lower electrode layer in a diffusion mode.
Further, the working power of the nitrogen ion generating device is between 1.5KW and 2.5KW, the diffusion time is between 50s and 60s, the diffusion pressure is between 0.1TORR and 0.5TORR, and the heating temperature is between 350 ℃ and 500 ℃.
Preferably, the source of nitrogen ion gas introduced comprises at least one of the group consisting of nitrogen and ammonia.
The present invention also provides a capacitor array structure including:
a semiconductor substrate;
the cross section of the lower electrode layer comprises a U shape, and nitrogen ions are diffused and implanted on the inner surface and the outer surface of the lower electrode layer;
the capacitor dielectric layer covers the inner surface and the outer surface of the lower electrode layer;
and the upper electrode layer is covered on the outer surface of the capacitance medium layer.
Preferably, the material of the lower electrode layer comprises titanium nitride.
Preferably, the material of the lower electrode layer includes one of the group consisting of titanium oxide, titanium carbide, and tungsten.
Preferably, the capacitor array structure further includes a top supporting layer, a middle supporting layer and a bottom supporting layer, all formed on the semiconductor substrate and connected to the lower electrode layer, wherein the top supporting layer is connected to the periphery of the opening of the lower electrode layer, the middle supporting layer is connected to the middle of the lower electrode layer, and the bottom supporting layer is formed on the surface of the semiconductor substrate and connected to the periphery of the bottom of the lower electrode layer.
Further, the materials of the top support layer, the middle support layer and the bottom support layer comprise one of the group consisting of silicon nitride and silicon oxynitride.
Preferably, the capacitor array structure further includes an upper electrode filling layer covering an outer surface of the upper electrode layer and filling up a gap between the upper electrode layers.
Preferably, the material of the upper electrode layer includes one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide and tungsten, and the material of the capacitance dielectric layer includes one of the group consisting of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.
As described above, the capacitor array structure and the method for manufacturing the same of the present invention have the following beneficial effects: according to the invention, the nitrogen ion plasma diffusion process is adopted to treat the lower electrode layer, nitrogen ions enter the lower electrode layer to extrude impurities therein, especially impurity chloride ions are extruded, and the impurity chloride ions are combined with hydrogen ions to generate hydrogen chloride gas to be discharged, so that the content of the impurity chloride ions in the lower electrode layer is reduced, the connection between the lower electrode layer and a substrate is stable, and the electrical connection stability of a capacitor is improved; in addition, chloride ions and hydrogen ions are combined to generate hydrogen chloride gas to be discharged, so that corrosion of impurity chloride ions to a lower electrode layer can be effectively reduced, and the leakage rate of the capacitor is reduced; and finally, when the capacitance dielectric layer is formed, oxygen element in the capacitance dielectric layer is not easy to dip into the lower electrode layer, so that the charge storage capacity of the capacitor is effectively ensured.
Drawings
Fig. 1 is a schematic diagram showing a process of preparing a lower electrode layer of a capacitor array structure in the prior art.
Fig. 2 is a flow chart of a process for fabricating a capacitor array structure according to the present invention.
FIG. 3 is a schematic diagram showing the formation of alternating stacked support layers and sacrificial layers in the fabrication of a capacitor array structure according to the present invention.
FIG. 4 is a schematic diagram illustrating the direction of lithography for forming a patterned mask layer in the fabrication of a capacitor array structure according to the present invention.
Fig. 5a to 5h are schematic structural diagrams of a patterned mask layer formed in the preparation of a capacitor array structure according to the present invention.
Fig. 6 is a schematic diagram showing a structure of forming a capacitor hole in the fabrication of a capacitor array structure according to the present invention.
Fig. 7 is a schematic diagram showing a structure of forming a lower electrode layer in the fabrication of a capacitor array structure according to the present invention.
Fig. 8 is a top view showing the formation of a first opening in the fabrication of the capacitor array structure of the present invention, wherein AA' represents a longitudinal cut along the θ1 direction.
Fig. 9a to 9d are schematic views showing a structure in which a first opening is formed in a cross section along the θ1 direction in fig. 8.
Fig. 10 is a schematic view showing a structure of fig. 8 after removing the second sacrificial layer at a section along the θ1 direction.
Fig. 11 is a schematic view showing a structure after the second opening is formed in the cross section along the θ1 direction in fig. 8.
Fig. 12 is a schematic view showing a structure of fig. 8 after removing the first sacrificial layer at a section along the θ1 direction.
Fig. 13 is a schematic structural diagram showing a high-temperature plasma diffusion process performed on a lower electrode layer in the preparation of a capacitor array structure according to the present invention.
Fig. 14 is a schematic diagram showing a structure of forming a capacitor dielectric layer and an upper electrode layer in the fabrication of a capacitor array structure according to the present invention.
Description of element reference numerals
1. Semiconductor substrate
11. Capacitor array area
2. Support layer
21. Bottom support layer
22. Intermediate support layer
221. A second opening
23. Top layer supporting layer
231. A first opening
3. Sacrificial layer
31. First sacrificial layer
311. Lower first sacrificial layer
312. Upper first sacrificial layer
32. Second sacrificial layer
33. Non-overlapping region
4. Patterning mask layer
41. Window
42. Multilayer barrier layer
421. Polysilicon barrier layer
422. Oxide barrier layer
423. Carbide barrier layer
43. Multilayer mask layer
431. First dielectric antireflective layer
432. Carbide layer
433. Second dielectric anti-reflection layer
44. Double-layer etching pattern
441. First etched pattern
442. Second etching pattern
45. An opening
5. Capacitor hole
6. Lower electrode layer
61. Nitride mask layer
62. Oxide mask layer
63. Carbide mask layer
64. Antireflection layer
65. Photoresist layer
7. Capacitor dielectric layer
8. Upper electrode layer
9. Upper electrode filling layer
θ1 first direction
Second direction of theta 2
Included angle
S1-S6 Steps 1) through 6)
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 14. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
Referring to fig. 2, the present embodiment provides a method for manufacturing a capacitor array structure, which includes the following steps:
1) Providing a semiconductor substrate, and forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a supporting layer and a sacrificial layer which are alternately laminated;
2) Forming a patterned mask layer on the laminated structure, and etching a plurality of capacitor holes in the laminated structure based on the patterned mask layer;
3) Forming a lower electrode layer at the bottom and the side wall of the capacitor hole, wherein the support layer is connected with the lower electrode layer;
4) Removing the sacrificial layer, wherein the supporting layer remains on the semiconductor substrate;
5) Performing a nitrogen ion plasma diffusion process on the lower electrode layer, wherein nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer;
6) And forming a capacitance medium layer on the inner surface and the outer surface of the lower electrode layer, wherein the capacitance medium layer covers the lower electrode layer, and forming an upper electrode layer on the outer surface of the capacitance medium layer, and the upper electrode layer covers the capacitance medium layer.
The method for manufacturing the capacitor array structure of the present invention will be described in detail with reference to the accompanying drawings.
First, as shown in S1 and fig. 3 in fig. 2, step 1) is performed to provide a semiconductor substrate 1, and a stacked structure including a support layer 2 and a sacrificial layer 3 alternately stacked is formed on the semiconductor substrate 1.
By way of example, the semiconductor substrate 1 includes a plurality of capacitive contact nodes (not shown) in a memory array structure.
Specifically, in one specific structure, the semiconductor substrate 1 further includes a semiconductor substrate (not shown), in which an active region and a word line are disposed, and a bit line and the capacitor contact node are disposed on the semiconductor substrate, and the capacitor contact node is electrically connected to a source of a transistor in the memory array structure.
As an example, in step 1), the number of the formed supporting layers 2 is greater than the number of the formed sacrificial layers 3, and the bottom material layer and the top material layer in the stacked structure formed by the sacrificial layers 3 and the supporting layers 2 are both the supporting layers 2.
In a preferred example, as shown in fig. 3, the number of the supporting layers 2 is three, including a top supporting layer 23, a middle supporting layer 22 and a bottom supporting layer 21, and the number of the sacrificial layers 3 is two, including a first sacrificial layer 31 between the bottom supporting layer 21 and the middle supporting layer 22 and a second sacrificial layer 32 between the top supporting layer 23 and the middle supporting layer 22.
Specifically, the support layers 2 and the sacrificial layers 3, such as the bottom support layer 21, the first sacrificial layer 31, the intermediate support layer 22, the second sacrificial layer 32, and the top support layer 23, may be formed using an atomic layer deposition process (Atomic Layer Deposition) or a plasma vapor deposition process (Plasma Enhenced Chemical Vapor Deposition).
As an example, the material of the support layer 2 contains at least one of the group consisting of silicon nitride and silicon oxynitride, and preferably, the material of the support layer 2 contains silicon nitride. The material of the sacrificial layer 3 comprises an oxide, which may preferably be silicon oxide or silicon oxynitride. It should be noted that the material of the sacrificial layer 3 is different from the material of the supporting layer 2, and the etching rates of the sacrificial layer 3 and the supporting layer 2 are different in the same etching process (such as the same etching solution), which is embodied in that the etching (such as etching) rate of the sacrificial layer 3 is far greater than the etching rate of the supporting layer 2 in the same etching process (such as the same etching solution), so that the supporting layer 2 is almost completely preserved when the sacrificial layer 3 is completely removed.
In a preferred example, as shown in fig. 3, the second sacrificial layer 32 is made of a material different from that of the first sacrificial layer 31, and the material of the second sacrificial layer 32 includes silicon oxide or silicon oxynitride. The material of the first sacrificial layer 31 includes boron-phosphorus doped silicon oxide (BPSG, borophosphosilicate glass), and the phosphorus ion doping concentration of the first sacrificial layer 31 is different at different thicknesses, which is represented by including a lower first sacrificial layer 311 and an upper first sacrificial layer 312, wherein the phosphorus ion doping concentration of the lower first sacrificial layer 311 is greater than that of the upper first sacrificial layer 312. Since the corrosion rate of BPSG is affected by the concentrations of boron ions and phosphorus ions, increasing the content of boron ions decreases the corrosion rate, increasing the content of phosphorus ions increases the corrosion rate significantly, and the first sacrificial layer 31 needs to be completed in the same etching process, so that the concentration of phosphorus ions in the underlying first sacrificial layer 311 of the first sacrificial layer 31 is increased, thereby effectively ensuring complete etching of the first sacrificial layer 31 and avoiding the decrease in capacitor performance due to insufficient etching. In this embodiment, the weight percentage of the phosphorous ion content of the lower layer first sacrificial layer 311 is between 3% and 5%, the weight percentage of the boron ion content is between 2% and 7%, the weight percentage of the phosphorous ion content of the upper layer first sacrificial layer 312 is between 3% and 5%, and the weight percentage of the boron ion content is between 5% and 10%.
In addition, the sacrificial layer 3 is removed during the subsequent process, and the supporting layer 2 serves as a supporting frame after the sacrificial layer 3 is removed to improve the mechanical strength of the structure when the capacitor is fabricated subsequently, so that the number of the sacrificial layer and the supporting layer can be set according to the height required by the capacitor to be fabricated subsequently, except for the three supporting layers and the two sacrificial layers listed above, and the number of the layers can be 1-10 times or more, wherein 2-5 times are preferable.
Next, as shown in S2 and fig. 4 of fig. 2, and fig. 5a to 5h and fig. 6, step 2) is performed to form a patterned mask layer 4 on the stacked structure, and a plurality of capacitor holes 5 are etched in the stacked structure based on the patterned mask layer 4.
As a preferred example, the step of forming the patterned mask layer 4 includes:
as shown in fig. 5a, in step 2-1), a multi-layer barrier layer 42 is sequentially formed on the structure obtained in step 1), and the multi-layer barrier layer 42 includes, for example, three layers including a polysilicon barrier layer 421, an oxide barrier layer 422, and a carbide barrier layer 423.
As shown in fig. 4 and 5b to 5c, in step 2-2), a first etching pattern 441 is formed on the structure obtained in step 2-1) along the first direction θ1 using a pitch multiplication process.
FIG. 4 is a schematic diagram showing the direction of photolithography used to form the patterned mask layer 4 in the fabrication of a capacitor array structure, wherein the capacitor array region 11 is formed along two lines with an included angle to increase the density of the capacitorThe first direction θ1 and the second direction θ2 of the array distribution are etched to form non-overlapping regions 33, and the non-overlapping regions 33 are etched to form capacitor holes 5, as shown in fig. 6, based on the capacitor holes 5, capacitors having the array distribution can be formed.
Specifically, as shown in fig. 5b, a plurality of mask layers 43 and a photoresist layer 434 are sequentially formed on the carbide blocking layer 423, and the plurality of mask layers 43 are three layers, and sequentially include a first dielectric anti-reflection layer 431, a carbide layer 432, and a second dielectric anti-reflection layer 433, for example. As shown in fig. 5c, the first etching pattern 441 is formed using a pitch multiplication process along the first direction θ1 based on the photoresist layer 434.
As shown in fig. 4 and 5d, in step 2-3), a second etching pattern 442 is formed on the structure obtained in step 2-2) along the second direction θ2 by using a pitch multiplication process, so as to obtain a double-layer etching pattern 44. As an example, the method of forming the second etching pattern 442 is the same as the method of forming the first etching pattern 441, so that a detailed description thereof will be omitted.
As shown in fig. 5e to 5h, step 2-4), etching the area outside the overlapping area of the double-layer etching pattern 44 to form the patterned mask layer 4 with the windows 41 arranged in an array.
Specifically, as shown in fig. 5e, the area except the overlapping area of the area where the double-layer etching pattern 44 is located is etched first to form a plurality of openings 45 of the capacitor array structure; as shown in fig. 5f to 5h, the carbide barrier layer 423 (as shown in fig. 5 f), the oxide barrier layer 422 (as shown in fig. 5 g), and the polysilicon barrier layer 421 (as shown in fig. 5 h) are then etched sequentially along the opening 45 to form the patterned mask layer 4 having the windows 41 arranged in an array. By way of example, the oxide barrier 422 includes a silicon oxide barrier.
As shown in fig. 6, the support layer 2 and the sacrificial layer 3 are etched based on the patterned mask layer 4 to form a capacitor hole 5 corresponding to the window 41.
As an example, the specific method for forming the capacitor hole is as follows: and etching the supporting layer 2 and the sacrificial layer 3 by adopting a dry etching process, a wet etching process or a process combining the dry etching process and the wet etching process according to the patterned mask layer 4 so as to form the capacitor holes 5 which are vertically penetrated in the supporting layer 2 and the sacrificial layer 3.
Continuing, as shown in S3 and fig. 7 in fig. 2, step 3) is performed to form a lower electrode layer 6 on the bottom and the side wall of the capacitor hole 5, and the support layer 2 is connected to the lower electrode layer 6.
Preferably, chemical vapor deposition is used on the sidewall and bottom of the capacitor hole 5, andand depositing a lower electrode material layer on the upper surface of the top supporting layer 23, wherein the material of the lower electrode layer 6 comprises at least one of the group consisting of titanium nitride, titanium oxide, titanium carbide and tungsten, then removing the lower electrode material layer on the upper surface of the top supporting layer 23 by adopting an etching process, and reserving the lower electrode material layer on the side wall and the bottom of the capacitor hole 5 to obtain the lower electrode layer 6, wherein the precursor of the chemical vapor deposition method comprises metal chloride. Since the precursor contains a metal chloride, chloride ions are generated during deposition to form the lower electrode layer 6, and the incorporation of chloride ions into the lower electrode layer 6 results in the lower electrode layer 6 containing impurity chloride ions. The material of the lower electrode layer 6 in this embodiment includes titanium nitride, and the chemical reaction included in the chemical vapor deposition method is as follows: TICl 4 +NH 3 →TIN+HCl+N 2 So during the deposition process, the precursor TICl is reacted 4 Impurity chloride ions are introduced into the lower electrode layer 6.
Continuing, as shown in S4 of fig. 2 and fig. 8 to 12, step 4) is performed to remove the sacrificial layer 3, wherein the support layer 2 remains on the semiconductor substrate 1.
As an example, step 4) comprises the steps of:
step 4-1), a first opening 231 is formed in the top supporting layer 23 to expose the second sacrificial layer 32 on the lower surface thereof. Specifically, as shown in fig. 9a, a nitride mask layer 61, an oxide mask layer 62, a carbide mask layer 63, an anti-reflection layer 64, and a photoresist layer 65 are formed in this order on the top support layer 23; then, as shown in fig. 9b, the anti-reflection layer 64, the carbide mask layer 63, the oxide mask layer 62 and the nitride mask layer 61 are exposed and etched based on the photoresist layer 65 to form a first opening 231; finally, as shown in fig. 9c to 9d, the oxide mask layer 62 (shown in fig. 9 c) and the nitride mask layer 61 (shown in fig. 9 d) are etched in sequence.
Step 4-2), removing the second sacrificial layer 32 by using a wet etching process based on the first opening 231, wherein the wet etching solution preferably contains 30% -60% hydrofluoric acid, as shown in fig. 10.
Step 4-3), forming a second opening 221 in the intermediate support layer 22 to expose the first sacrificial layer 31 on the lower surface thereof, as shown in fig. 11.
Step 4-4), removing the first sacrificial layer 31 by using a wet etching process based on the second opening 221, wherein the wet etching solution preferably contains 30% -60% hydrofluoric acid, as shown in fig. 12.
As an example, a step of depositing a support layer material on the upper surface of the top support layer 23 is further included between the step 4-2) and the step 4-3) to thicken the top support layer 23. This is because a portion of the top support layer 23 is removed during step 4-2), and a step of depositing a support layer material on the upper surface of the upper support layer 23 is added between step 4-2) and step 4-3) in order to prevent the top support layer 23 from being etched through during the subsequent etching process and to ensure sufficient support strength at the upper support.
As an example, in step 4-1), one of the first openings 231 overlaps only one of the capacitor holes 5, or one of the first openings 231 overlaps a plurality of the capacitor holes 5 at the same time (as shown in fig. 8, fig. 8 illustrates one of the first openings 231 overlapping three of the capacitor holes 5); in step 4-2), one of the second openings 221 overlaps only one of the capacitor holes 5, or one of the second openings 221 overlaps a plurality of the capacitor holes 5 at the same time. In this embodiment, one of the first openings 231 overlaps three of the capacitor holes 5 at the same time, and one of the second openings 221 overlaps three of the capacitor holes 5 at the same time.
Continuing, as shown in S5 and 13 in fig. 2, step 5) is performed to perform a nitrogen ion plasma diffusion process on the lower electrode layer 6, and the nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer 6.
As an example, step 5) comprises the steps of:
step 5-1), placing the structure obtained in the step 4) in a nitrogen ion generating device.
And 5-2), introducing a nitrogen ion gas source into the nitrogen ion generating device, generating nitrogen ions through the action of microwaves, and enabling the nitrogen ions to enter the lower electrode layer 6 through a diffusion mode.
Specifically, the working power of the nitrogen ion generating device is between 1.5KW and 2.5KW, the diffusion time is between 50s and 60s, the diffusion pressure is between 0.1TORR and 0.5TORR, the heating temperature is between 350 ℃ and 500 ℃, and the introduced nitrogen ion gas source comprises at least one of the group consisting of nitrogen and ammonia. After the gas source enters the nitrogen ion generating device, nitrogen ions are generated under the action of microwaves, the nitrogen ions diffuse into the inner surface and the outer surface of the lower electrode layer 6 and extrude impurities in the lower electrode layer 6, especially impurity chloride ions, and the impurity chloride ions are combined with hydrogen ions to generate hydrogen chloride gas to be discharged, so that the impurity chloride ions in the lower electrode layer 6 are removed. The use of microwaves to generate nitrogen ions can also effectively reduce the damage of nitrogen ions to the lower electrode layer 6. In this embodiment, ammonia gas is preferably used as a nitrogen ion gas source, and the ammonia gas can generate nitrogen ions and hydrogen ions under the action of microwaves, so that the nitrogen ions can remove impurity chloride ions in the lower electrode layer 6, and meanwhile, the hydrogen ions can also combine with a few impurity oxygen ions on the surface of the lower electrode layer 6 to generate water vapor for discharge, so as to realize removal of impurity oxygen ions on the surface of the lower electrode layer 6.
Finally, as shown in S6 and 14 in fig. 2, step 6) is performed to form a capacitor dielectric layer 7 on the inner surface and the outer surface of the lower electrode layer 6, wherein the capacitor dielectric layer 7 covers the lower electrode layer 6, and an upper electrode layer 8 is formed on the outer surface of the capacitor dielectric layer 7, wherein the upper electrode layer 8 covers the capacitor dielectric layer 7.
As an example, the material of the capacitor dielectric layer 7 may be selected to be a high K dielectric material to increase the capacitance value of a capacitor per unit area, and it includes a stack formed of at least one of the group consisting of zirconia (ZrOx), hafnium oxide (HfOx), titanium zirconium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx). The material of the upper electrode layer 8 includes a laminate formed of at least one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide, and tungsten.
Preferably, an upper electrode filling layer 9 is formed on an outer surface of the upper electrode layer 8, wherein the upper electrode filling layer 9 covers the upper electrode layer 8 and fills a gap between the upper electrode layers 8.
According to the invention, the nitrogen ion plasma diffusion process is used for removing chloride ion impurities in the lower electrode layer 6, and experiments show that the resistivity of the lower electrode layer 6 can be effectively reduced. When titanium nitride is used as the lower electrode layer 6, the resistivity thereof can be reduced from 160. Mu. Ω. Cm to 180. Mu. Ω. Cm to 40. Mu. Ω. Cm to 160. Mu. Ω. Cm; when tungsten, titanium silicide and cobalt silicide are used as the lower electrode layer 6, the resistivity thereof is reduced to 8. Mu. Ω. Cm-15. Mu. Ω. Cm, 40. Mu. Ω. Cm-70. Mu. Ω. Cm, 13. Mu. Ω. Cm-16. Mu. Ω. Cm, 15. Mu. Ω. Cm-20. Mu. Ω. Cm, respectively.
Example two
With reference to fig. 14 in combination with the embodiment, the present invention further provides a capacitor array structure, where the capacitor array structure is preferably manufactured by the manufacturing method of the present invention, and of course, but not limited thereto, the capacitor array structure includes:
a semiconductor substrate 1;
a lower electrode layer 6 formed on the semiconductor substrate 1, wherein the cross-sectional shape of the lower electrode layer 6 includes a U shape, and nitrogen ions are diffusion-implanted into the inner surface and the outer surface of the lower electrode layer 6;
a capacitance dielectric layer 7 covering the inner surface and the outer surface of the lower electrode layer 6;
and an upper electrode layer 8 covering the outer surface of the capacitance medium layer 7.
Wherein, the nitrogen ions diffusion-implanted on the inner surface and the outer surface of the lower electrode layer 6 can extrude the impurity ions in the lower electrode layer, especially the impurity chloride ions in the lower electrode layer, so as to reduce the impurity content in the lower electrode layer, especially the impurity chloride ions.
By way of example, the semiconductor substrate 1 includes a plurality of capacitive contact nodes (not shown) in a memory array structure.
Specifically, in one specific structure, the semiconductor substrate 1 further includes a semiconductor substrate (not shown), in which an active region and a word line are disposed, and a bit line and a capacitor contact node are disposed on the semiconductor substrate, and the capacitor contact node is electrically connected to a source of a transistor in the memory array structure.
As an example, the material of the lower electrode layer 7 includes one of the group consisting of titanium nitride, titanium oxide, titanium carbide, and tungsten. Preferably, the material of the lower electrode layer 7 comprises titanium nitride.
As an example, the capacitor array structure further includes a top supporting layer 23, a middle supporting layer 22, and a bottom supporting layer 21, all formed on the semiconductor substrate 1 and connected to the lower electrode layer 6, wherein the top supporting layer 23 is connected to an opening periphery of the lower electrode layer 6, the middle supporting layer 22 is connected to a middle portion of the lower electrode layer 6, and the bottom supporting layer 21 is formed on a surface of the semiconductor substrate 1 and connected to a bottom periphery of the lower electrode layer 6.
The top support layer 23, the middle support layer 22 and the bottom support layer 21 serve to increase the mechanical strength of the capacitor array.
Preferably the materials of the top support layer 23, the middle support layer 22 and the bottom support layer 21 comprise one of the group consisting of silicon nitride, silicon oxynitride.
As an example, the capacitor array structure further includes an upper electrode filling layer 9 covering the outer surface of the upper electrode layers 8 and filling up gaps between the upper electrode layers 8.
As an example, the material of the upper electrode layer 8 includes one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide, and tungsten, and the material of the capacitance medium layer 7 includes one of the group consisting of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide, and aluminum oxide.
According to the capacitor array structure provided by the invention, nitrogen ions are diffused and implanted on the inner surface and the outer surface of the lower electrode layer 6, and experiments prove that the resistivity of the lower electrode layer 6 can be effectively reduced. When titanium nitride is used as the lower electrode layer 6, the resistivity thereof can be reduced from 160. Mu. Ω. Cm to 180. Mu. Ω. Cm to 40. Mu. Ω. Cm to 160. Mu. Ω. Cm; when tungsten, titanium silicide and cobalt silicide are used as the lower electrode layer 6, the resistivity thereof is reduced to 8. Mu. Ω. Cm-15. Mu. Ω. Cm, 40. Mu. Ω. Cm-70. Mu. Ω. Cm, 13. Mu. Ω. Cm-16. Mu. Ω. Cm, 15. Mu. Ω. Cm-20. Mu. Ω. Cm, respectively.
In summary, the capacitor array structure and the preparation method thereof of the present invention, the preparation method of the capacitor array comprises the following steps: 1) Providing a semiconductor substrate, and forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a supporting layer and a sacrificial layer which are alternately laminated; 2) Forming a patterned mask layer on the laminated structure, and etching a plurality of capacitor holes in the laminated structure based on the patterned mask layer; 3) Forming a lower electrode layer at the bottom and the side wall of the capacitor hole, wherein the support layer is connected with the lower electrode layer; 4) Removing the sacrificial layer, wherein the supporting layer remains on the semiconductor substrate; 5) Performing a nitrogen ion plasma diffusion process on the lower electrode layer, wherein nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer; 6) And forming a capacitance medium layer on the inner surface and the outer surface of the lower electrode layer, wherein the capacitance medium layer covers the lower electrode layer, and forming an upper electrode layer on the outer surface of the capacitance medium layer, and the upper electrode layer covers the capacitance medium layer. According to the invention, the nitrogen ion plasma diffusion process is adopted to treat the lower electrode layer, nitrogen ions enter the lower electrode layer to extrude impurities therein, especially impurity chloride ions are extruded, and the impurity chloride ions are combined with hydrogen ions to generate hydrogen chloride gas to be discharged, so that the content of the impurity chloride ions in the lower electrode layer is reduced, the connection between the lower electrode layer and a substrate is stable, and the electrical connection stability of a capacitor is improved; in addition, chloride ions and hydrogen ions are combined to generate hydrogen chloride gas to be discharged, so that corrosion of impurity chloride ions to a lower electrode layer can be effectively reduced, and the leakage rate of the capacitor is reduced; and finally, when the capacitance dielectric layer is formed, oxygen element in the capacitance dielectric layer is not easy to dip into the lower electrode layer, so that the charge storage capacity of the capacitor is effectively ensured. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (24)
1. The preparation method of the capacitor array structure is characterized by comprising the following steps of:
1) Providing a semiconductor substrate, forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a bottom supporting layer, a first sacrificial layer, a middle supporting layer, a second sacrificial layer and a top supporting layer which are laminated in sequence, the material of the first sacrificial layer comprises boron-phosphorus doped silicon oxide (BPSG), the material of the second sacrificial layer comprises oxide, the first sacrificial layer comprises an upper first sacrificial layer and a lower first sacrificial layer, and the phosphorus ion doping concentration of the lower first sacrificial layer is greater than that of the upper first sacrificial layer;
2) Forming a patterned mask layer on the laminated structure, and etching a plurality of capacitor holes in the laminated structure based on the patterned mask layer;
3) Forming a lower electrode layer at the bottom and the side wall of the capacitor hole, wherein the support layer is connected with the lower electrode layer;
4) Removing the sacrificial layer, wherein the supporting layer remains on the semiconductor substrate;
5) Performing a nitrogen ion plasma diffusion process on the lower electrode layer, wherein nitrogen ions are diffused into the inner surface and the outer surface of the lower electrode layer;
6) And forming a capacitance medium layer on the inner surface and the outer surface of the lower electrode layer, wherein the capacitance medium layer covers the lower electrode layer, and forming an upper electrode layer on the outer surface of the capacitance medium layer, and the upper electrode layer covers the capacitance medium layer.
2. The method of manufacturing a capacitor array structure according to claim 1, wherein: the lower electrode layer formed in the step 3) contains impurity chloride ions, the nitrogen ions in the step 5) are diffused into the inner surface and the outer surface of the lower electrode layer, and the impurity chloride ions are extruded out to remove the impurity chloride ions.
3. The method of manufacturing a capacitor array structure according to claim 2, wherein: and forming the lower electrode layer at the bottom and the side wall of the capacitor hole by adopting a chemical vapor deposition method, wherein a precursor of the chemical vapor deposition method comprises metal chloride.
4. A method of fabricating a capacitor array structure according to claim 3, wherein: the material of the lower electrode layer includes at least one of the group consisting of titanium nitride, titanium oxide, titanium carbide, and tungsten.
5. A method of fabricating a capacitor array structure according to claim 3, wherein: the bottom electrode layer comprises a titanium nitride layer, the titanium nitride layer is formed at the bottom and the side wall of the capacitor hole by adopting a chemical vapor deposition method, and the chemical vapor deposition method comprises the following steps: TICl 4 +NH 3 →TIN+HCl+N 2 Wherein the precursor TICl 4 The lower electrode layer is made to contain the impurity chloride ions.
6. The method of manufacturing a capacitor array structure according to claim 1, wherein: the weight percentage of the phosphorus ion content of the lower layer first sacrificial layer is 3% -5%, the weight percentage of the boron ion content of the upper layer first sacrificial layer is 2% -7%, the weight percentage of the phosphorus ion content of the upper layer first sacrificial layer is 3% -5%, the weight percentage of the boron ion content of the lower layer first sacrificial layer is 5% -10%, and the phosphorus ion doping concentration of the lower layer first sacrificial layer is larger than that of the upper layer first sacrificial layer.
7. The method of manufacturing a capacitor array structure according to claim 1, wherein: step 2) comprises the steps of:
2-1) sequentially forming a plurality of barrier layers on the structure obtained in the step 1);
2-2) forming a first etching pattern on the structure obtained in the step 2-1) along the first direction by using a pitch multiplication process;
2-3) forming a second etching pattern on the structure obtained in the step 2-2) along a second direction by using a space multiplication process, so as to obtain a double-layer etching pattern, wherein the first direction and the second direction have included angles;
2-4) etching the area outside the overlapping area of the double-layer etching pattern to form the patterned mask layer.
8. The method of manufacturing a capacitor array structure according to claim 7, wherein: the multi-layer barrier layer sequentially comprises a polycrystalline silicon barrier layer, an oxide barrier layer and a carbide barrier layer; and, the step 2-4) comprises the following steps:
2-4-1) etching the area except the overlapping area of the area where the double-layer etching pattern is positioned to form a plurality of openings of the capacitor array structure;
2-4-2) etching the polysilicon barrier layer, the oxide barrier layer and the silicide barrier layer along the opening in sequence to form the patterned mask layer.
9. The method of manufacturing a capacitor array structure according to claim 8, wherein: the oxide barrier layer includes a silicon oxide barrier layer.
10. The method of manufacturing a capacitor array structure according to claim 1, wherein: step 4) comprises the steps of:
4-1) forming a first opening in the top support layer to expose the second sacrificial layer;
4-2) removing the second sacrificial layer by adopting a wet etching process based on the first opening;
4-3) forming a second opening in the intermediate support layer to expose the first sacrificial layer;
4-4) removing the first sacrificial layer by adopting a wet etching process based on the second opening.
11. The method of manufacturing a capacitor array structure according to claim 10, wherein: the wet etching solution in the step 4-2) contains 30% -60% of hydrofluoric acid, and the wet etching solution in the step 4-4) contains 30% -60% of hydrofluoric acid.
12. The method of manufacturing a capacitor array structure according to claim 10, wherein: in step 4-1), one of the first openings overlaps only one of the capacitor holes, or one of the first openings overlaps a plurality of the capacitor holes at the same time; in step 4-3), one of the second openings overlaps only one of the capacitor holes, or one of the second openings overlaps a plurality of the capacitor holes at the same time.
13. The method of manufacturing a capacitor array structure of claim 12, wherein: one of the first openings overlaps three of the capacitive apertures simultaneously, and one of the second openings overlaps three of the capacitive apertures simultaneously.
14. The method of manufacturing a capacitor array structure according to claim 1, wherein: the material of the support layer comprises at least one of the group consisting of silicon nitride and silicon oxynitride, the material of the upper electrode layer comprises at least one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide and tungsten, and the material of the capacitance medium layer comprises at least one of the group consisting of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.
15. The method of manufacturing a capacitor array structure according to any one of claims 1 to 14, wherein: step 5) comprises the steps of:
5-1) placing the structure obtained in the step 4) in a nitrogen ion generating device;
5-2) introducing a nitrogen ion gas source into the nitrogen ion generating device, generating nitrogen ions through the action of microwaves, and enabling the nitrogen ions to enter the lower electrode layer in a diffusion mode so as to remove impurity chloride ions in the lower electrode layer.
16. The method of manufacturing a capacitor array structure of claim 15, wherein: the working power of the nitrogen ion generating device is between 1.5KW and 2.5KW, the diffusion time is between 50s and 60s, the diffusion pressure is between 0.1TORR and 0.5TORR, and the heating temperature is between 350 ℃ and 500 ℃.
17. The method of manufacturing a capacitor array structure of claim 15, wherein: the source of nitrogen ion gas is introduced to comprise at least one of the group consisting of nitrogen and ammonia.
18. The capacitor array structure is characterized in that the capacitor array structure is prepared by the preparation method of any one of claims 1-17, and comprises the following steps:
a semiconductor substrate;
the cross section of the lower electrode layer comprises a U shape, and nitrogen ions are diffused and implanted on the inner surface and the outer surface of the lower electrode layer;
the capacitor dielectric layer covers the inner surface and the outer surface of the lower electrode layer;
and the upper electrode layer is covered on the outer surface of the capacitance medium layer.
19. The capacitor array structure of claim 18, wherein: the material of the lower electrode layer comprises titanium nitride.
20. The capacitor array structure of claim 18, wherein: the material of the lower electrode layer includes one of the group consisting of titanium oxide, titanium carbide, and tungsten.
21. The capacitor array structure of claim 18, wherein: the capacitor array structure further comprises a top supporting layer, a middle supporting layer and a bottom supporting layer which are all formed on the semiconductor substrate and connected with the lower electrode layer, wherein the top supporting layer is connected with the periphery of an opening of the lower electrode layer, the middle supporting layer is connected with the middle part of the lower electrode layer, and the bottom supporting layer is formed on the surface of the semiconductor substrate and connected with the periphery of the bottom of the lower electrode layer.
22. The capacitor array structure of claim 21, wherein: the top support layer, the middle support layer and the bottom support layer are made of a material selected from the group consisting of silicon nitride and silicon oxynitride.
23. The capacitor array structure of claim 18, wherein: the capacitor array structure further includes an upper electrode filling layer covering the outer surface of the upper electrode layer and filling up gaps between the upper electrode layers.
24. The capacitor array structure of claim 18, wherein: the material of the upper electrode layer comprises one of the group consisting of polysilicon, titanium nitride, titanium oxide, titanium carbide and tungsten, and the material of the capacitance medium layer comprises one of the group consisting of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.
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| CN112133625A (en) * | 2019-06-24 | 2020-12-25 | 长鑫存储技术有限公司 | Mask structure and forming method thereof, memory and forming method thereof |
| CN112397509A (en) * | 2019-08-16 | 2021-02-23 | 长鑫存储技术有限公司 | Capacitor array structure, forming method thereof and semiconductor memory |
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