CN1815734A - 发光二极管数组封装结构及其方法 - Google Patents

发光二极管数组封装结构及其方法 Download PDF

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CN1815734A
CN1815734A CNA2005100094052A CN200510009405A CN1815734A CN 1815734 A CN1815734 A CN 1815734A CN A2005100094052 A CNA2005100094052 A CN A2005100094052A CN 200510009405 A CN200510009405 A CN 200510009405A CN 1815734 A CN1815734 A CN 1815734A
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emitting diode
light
array
drive circuit
diode array
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杜顺利
庄智宏
钟怀谷
杨佳峰
杨呈尉
韩祖安
王虹东
洪建成
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Opto Tech Corp
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Opto Tech Corp
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Abstract

根据本发明的方法，是先在一基板上形成沟渠结构，此基板可为一般半导体晶圆或是适用于半导体微影制程的各种基板，如陶瓷基板或塑料基板等。根据本发明的最佳实施例中，是以硅晶圆为基板材料。接着将发光二极管数组和驱动集成电路数组放置于相对应的沟渠结构中，并形成一绝缘层于基板、发光二极管数组和驱动集成电路数组表面上，接着利用一微影制程程序在两者接脚间形成电性连接，并进行切割来完成各封装单元，再将封装单元固着于印刷电路板上，进行打线接合驱动集成电路与印刷电路板上的输出输入接脚。

Description

发光二极管数组封装结构及其方法
技术领域
本发明是有关于一种组装结构及其方法，且特别是有关于一种发光二极管数组的组装结构及其方法。
背景技术
传统打印机头所采用的技术是借助能量高，固定波段的激光将打印信息扫瞄在滚筒上。使用激光的优点在于，较一般光线而言没有散射的困扰，然而却有光学机构复杂使得激光打印机在机构上存在着无法进一步缩小的问题。因此，利用发光二极管(1ight-emitting diodes，LED)为替代光源来设计打印机，可简化光学机构，达到打印机机构简洁的目的。
参阅图1所示为一传统打印机的概略示意图。打印时，当打印机接收计算机传送的数据后，由多个发光二极管数组102所组成的打印机头100光源，会通过聚焦镜104照射到感光鼓106，感光鼓106上被照到的地方会带静电，此静电会吸引墨粉盒108中的碳粉，再由感光鼓106压印碳粉至纸张110，经热处理固定，即完成打印的动作。发光二极管是一种通电即可发光的半导体，成像面的每一个点都要对应一个发光二极管。以一台600dpi(Dot Per Inch，DPI)的LED打印机对于A4纸张大小的打印格式而言，其成像线面就要有约5,000个发光二极管与其对应，此时若以具192点的发光二极管数组102来形成此打印机头100，则需使用26支发光二极管数组。
由于在发光二极管打印技术中，若要提高分辨率，需要将发光二极管组件做的更小，以在相同的打印机头体积下，容纳更多发光二极管。然而，传统封装方法，如图2所示，需通过高精度的固晶设备将发光二极管数组102与驱动集成电路数组112精确的平行置放于印刷电路板114上。接着进行打线接合，将各发光二极管数组102与驱动集成电路数组112间的金垫以约5000条导线116进行连接，使驱动集成电路112得以电性驱动各发光二极管。
上述的封装方法，由于打线的条数及密度太高，将导致产出效率不佳及制程难度增加，因而造成产品良率降低以及制造成本增加。且随着分辨率要求越来越高，发光二极管组件会做得越来越小，使得打线接合制程更加困难。另一方面，在传统的封装结构下，是在发光二极管数组与驱动集成电路均安置于印刷电路板上后，再进行两者的电性连接，因此当连接完成后所进行的电性测试，发现有不良品时，不论是发光二极管数组或驱动集成电路，均需将其在从印刷电路板上拆卸下来，再以新品取代之，其重工制程不仅繁琐且相当困难。
因此，本发明提出一种新的封装方法及结构，来解决上述的缺点。
发明内容
因此本发明的主要目的就是在提供一种不需使用高密度打线接合的发光二极管数组封装结构及其方法。
本发明的另一目的是在提供一种可使用微影制程进行导线线路布局的封装结构及其方法。
本发明的再一目的为提供一种使用发光二极管数组制造打印机头的方法。
根据本发明的上述目的，提出一种发光二极管数组封装方法，根据本发明的方法，是先在一基板上形成沟渠结构，接着将发光二极管数组和驱动集成电路数组放置于相对应的沟渠结构中，并形成一绝缘层于基板、发光二极管数组和驱动集成电路表面上，接着利用一微影制程程序在两者接脚间形成电性连接，并进行切割来完成各封装单元，再将封装单元固着于印刷电路板上，进行打线接合驱动集成电路数组与印刷电路板上的输出输入接脚。
本发明也提出一种发光二极管的封装结构，根据本发明的结构，至少包括一印刷电路板和一与此印刷电路板连接的基板，其中此印刷电路板包含至少一输出输入接点，而此基板上形成有沟渠结构，至少一发光二极管数组和驱动集成电路数组放置于相对应的沟渠结构中，一第一电性连接电路形成于发光二极管数组和驱动集成电路数组间，一第二电性连接电路形成于驱动集成电路数组和印刷电路板的输出输入接点间。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂，将附图的详细说明如下：
图1所示为一传统打印机的概略示意图；
图2所示为一传统打印机头的封装方法；
图3a所示为沟渠结构于基板上的概略示意图；
图3b所示为图3a中AA线的剖面结构示意图；
图4a所示为将发光二极管数组与驱动电路数组置于基板的一实施例；
图4b所示为将发光二极管数组与驱动电路置于基板上的另一实施例；
图4c所示为将发光二极管数组与驱动电路数组置于基板上沟渠结构的示意图；
图5a、6a、7a、8a、10a所示为基板、发光二极管数组和驱动集成电路数组的表面上，沉积一层绝缘层的示意图；
图5b、6b、7b、8b、10b所示为将绝缘层蚀刻，以形成接触窗开口，来暴露出发光二极管数组和驱动集成电路数组的接脚的示意图；
图5c、6c、7c、8c、10c所示为利用微影制程方法，进行发光二极管数组接脚和驱动集成电路数组接脚间的导线连接示意图；
图5d、6d、7d、8d、10d所示为发光二极管数组与驱动集成电路数组放置于晶圆上的概略图；
图5e、6e、7e、8e、10e所示分别为图5d、6d、7d、8d区域308的放大概略图标；
图5f、6f、7f、8f、10f所示分别为图5e、6e、7e、8e中AA线的剖面结构示意图；
图9a所示为另一种沟渠结构在基板上的概略示意图；
图9b所示为图9a中AA线的剖面结构示意图；
图9c所示为将发光二极管数组与驱动电路数组置于基板上沟渠结构的示意图；
图11a～11e所示分别为根据本发明的五个较佳实施例完成的打印机头概略示意图。
附图标记说明
100  打印机头
102、302  发光二极管数组
104  聚焦镜
106  感光鼓
108  墨粉盒
110  纸张
112、304  驱动集成电路
114、500  印刷电路板
116  导线
300  基板
308  区域
310、310a、400  沟渠结构
312  绝缘层
314  导体层
316  发光二极管单元
317a、317b、318和504  接脚
320、320a、420a、420b、420c  虚线
322、502  黏着物质
具体实施方式
为了解决传统上打线接合制程的困难，与良率难提升的缺点，因此，本发明采用半导体微影制程的方法，来进行发光二极管数组和驱动集成电路间的导线连接。
根据一较佳实施例，本发明会先使用一现有的方法，如图3a所示，在一基板300，例如为一硅晶圆上，形成多个沟渠结构310与310a，其中沟渠结构310置放发光二极管数组302，而沟渠结构310a置放驱动集成电路数组304。此沟渠结构的深度与大小，一般是需可容纳相对应发光二极管数组302和驱动集成电路数组304，如图3b所示为图3a中AA线的剖面结构示意图。形成此沟渠结构310与310a的现有方法，例如可使用干式蚀刻、湿式蚀刻法或机械加工在晶圆上形成沟渠结构，然而其它可形成沟渠结构的制程方法均可用于本发明中。
如图4a所示，在半导体晶圆300完成沟渠结构310、310a后，会在沟渠结构310、310a的底部，形成一黏着物质322，此黏着物质322可为银胶或是一般半导体制程现有的聚合物(polymide)。制作方法可以旋转涂布法(spin coating)或点印法(stamping)进行。接着将发光二极管数组302和驱动集成电路数组304分别置入沟渠结构310、310a中。或是分别在发光二极管数组302与驱动集成电路数组304的底部先形成一黏着物质322，再分别固着于沟渠结构310与310a中，如图4b所示。图4c所示为发光二极管数组与驱动集成电路数组放置于基板上沟渠结构中的剖面结构示意图。
接着利用微影制程方法，进行发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的导线连接，下述通过各微影制程实施例来说明本发明的导线连接形成方法，但本发明并不以此实施例为限，各种可能的导线形成方法均可应用于本发明中。
本封装结构可使用不同设计规格的发光二极管数组和驱动集成电路数组以完成相同的应用。如图5a～5f为本发明的第一实施例的制程流程图，其中发光二极管数组302和驱动集成电路数组304是对称排列型数组，如第5e图所示。首先使用一现有制程，在基板300、发光二极管数组302和驱动集成电路数组304的表面上，沉积一层绝缘层312，如第5a图所示。本发明中是以Polymide为绝缘材料，但不以此为限，而沉积的方法，使用涂旋式涂布法(Spin-coating)，但也不以此为限。接着进行一现有的平坦化制程，用以平坦绝缘层312，例如可采用热流的方式，让所沉积的绝缘层因高温热流而平坦化，其它已知的平坦技术也可用于本发明中。
当完成平坦化后，即可在绝缘层312上进行微影制程，来暴露出发光二极管数组302的接脚317b，和驱动集成电路数组304上的接脚317a和318，其中接脚318为外接电源接脚。首先在绝缘层312上涂布一光阻层(附图未标示)，并图案化此光阻层。接着以此图案化光阻层为罩幕，蚀刻绝缘层312，以在绝缘层312中形成接触窗开口319，来暴露出发光二极管数组302和驱动集成电路数组304的接脚。如图5b所示。在另一较佳实施例中，也可以光感性polymide进行微影制程，以显影方式直接暴露出发光二极管数组302和驱动集成电路数组304的接脚。
接着在表面上全面沉积一层导体层314，填充接触窗口319，其导体材料可为铝、金等，根据本发明的最佳实施例而言，是采用金作为导线材料，其制造方法可利用电镀法、热蒸镀法、电子束蒸镀法等现有技术加以完成。
接着，涂布一光阻层(附图未标示)于导体层314之上，接着图案化此光阻层，使其具有所需的导线图案，然后以此图案化光阻层为罩幕，接着蚀刻暴露的导体层314。最后再将光阻层去除而完成导体层314的定义，亦即形成发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的连接。除了以蚀刻方式完成上述的电性连接外，也可以光电半导体的现有技术，以金属剥离法(Lift-off)完成电性连接，如图5c所示。如图5d所示为发光二极管数组302和驱动集成电路数组304在上述制程完成后，在基板300上的排列方式。如图5e所示，为图5d区域308的放大概略图标。接着即可在基板300上进行导线连接的电性测试，以筛选制程中的不良品，进一步降低在后段印刷电路板封装上的不良率。换句话说，通过本发明的方法，其电性测试不必在完成印刷电路板封装后再加以进行，因此可大幅降低重工发生的可能性。此外，由于在发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间已没有传统高密度打线接合的结构，因此可以打线方式进行后段印刷电路板封装后的重工，再进一走降低重工的复杂性。结合上述两项优点，可将封装上的不良率降至最低。
当在发光二极管数组302和驱动集成电路数组304间完成金线连接后，接着会进行切割制程，以形成印刷电路板上的封装单元。在切割制程上，是依循发光二极管数组302的中线320a与驱动集成电路数组304的中线320b进行切割，即可完成两个由发光二极管数组302和驱动集成电路数组304所共同构成的封装单元，如图5f所示，为图5e中AA线的剖面示意图。
由于在更高分辨率的打印机头应用下，如1200DPI的打印分辨率。发光二极管数组上的二极管单元排列更趋密集，因此在发光二极管数组的制作上通常将发光二极管数组的接脚分布于两侧，此时便需以两侧驱动集成电路数组一起驱动该发光二极管数组。
本结构也可适用于以两侧驱动集成电路一起驱动该发光二极管数组的应用。以本发明的第二实施例为例，其制程流程与上述第一实施例类似，如图6a～6f所示。差异之处在于使用不同型态的发光二极管数组与驱动集成电路数组时，微影布线的绕线型态有所不同。如图6a所示为绝缘层312沉积与平坦化。如图6b所示为，在绝缘层312中形成接触窗开口319，来暴露出发光二极管数组302和驱动集成电路数组304的接脚。如图6c所示为，完成发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的电性连接。如图6d所示为发光二极管数组302和驱动集成电路数组304在基板300上的排列示意图。如图6e所示，其为图6d区域308的放大概略图标。在切割制程上，是依循驱动集成电路304中线320b进行切割，即可完成一个由发光二极管数组302和两侧驱动集成电路数组304所共同构成的封装单元，如图6f所示，为图6e中AA线的剖面示意图。
当使用单边驱动集成电路数组时，也可以应用于本发明上。以本发明的第三实施例为例，是使用含有对称接脚的高密度发光二极管数组和单边驱动集成电路数组。其制程流程图如图7a～7f所示。如图7a所示为绝缘层312沉积与平坦化。如图7b所示为，在绝缘层312中形成接触窗开口319，来暴露出发光二极管数组302和驱动集成电路数组304的接脚。如图7c所示为，完成发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的电性连接。如图7d所示为发光二极管数组302和驱动集成电路数组304在基板300上的排列示意图。如图7e所示，为图7d区域308的放大概略图标。在切割制程上，是依循介于驱动集成电路数组304中的基板中线420进行切割，即可完成一个由发光二极管数组302和两侧驱动集成电路数组304所共同构成的封装单元，如图7f所示，为图7e中AA线的剖面示意图。
本发明的第四实施例，是使用一般单边发光二极管数组和单边驱动集成电路数组。其制程流程图如图8a～8f所示。如图8a所示为绝缘层312沉积与平坦化。如图8b所示为，在绝缘层312中形成接触窗开口319，来暴露出发光二极管数组302和驱动集成电路数组304的接脚。如图8c所示为，完成发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的电性连接。如图8d所示为发光二极管数组302和驱动集成电路数组304在基板300上的排列示意图。如图8e所示，为图8d区域308的放大概略图标。在切割制程上，是依循介于发光二极管数组302与驱动集成电路数组304中的基板中线420b进行切割，即可完成一个由发光二极管数组302和驱动集成电路数组304所共同构成的封装单元，如图8f所示，为图8e中AA线的剖面示意图。
本发明的第五实施例，也使用一般单边发光二极管数组和单边驱动集成电路数组。如图9a～9c所示，在半导体晶圆300形成沟渠结构400后，将发光二极管数组302和驱动集成电路数组304置入沟渠结构400后向两侧靠拢。如图10a所示为绝缘层312沉积。如图10b所示为，在绝缘层312中形成接触窗开口319，来暴露出发光二极管数组302和驱动集成电路数组304的接脚。如图10c所示为，完成发光二极管数组302接脚317b，和驱动集成电路数组304接脚317a间的电性连接。如图10d所示为发光二极管数组302和驱动集成电路数组304在基板300上的排列示意图。如图10e所示，为图10d区域308的放大概略图标。在切割制程上，是依循介于发光二极管数组302与驱动集成电路数组304中的沟渠中线420c进行切割，即可完成一个由发光二极管数组302和驱动集成电路数组304所共同构成的封装单元，如图10f所示，为图10e中AA线的剖面示意图。
接着请参阅图11a～11e所示分别为上述五个实施例的封装单元与一印刷电路板连接后的结构图。根据本发明的较佳实施例，切割完成的各封装单元可通过一黏着装置502，与印刷电路板500进行接合。同时，驱动集成电路数组304上的接脚318，会以打线接合的方式来与印刷电路板上的输出输入接脚504进行电性连接，如此完成打印机头的制程。
根据本发明的封装方法，其发光二极管数组和驱动集成电路数组是先置放于基板上，接着再以微影制程的方式在两者接脚间形成电性连接，最后进行切割来完成各封装单元。因此，本发明的方法，是以批量的制作方式，整批完成发光二极管数组和驱动集成电路数组间的电性连接，而不是如传统般采用一根一根进行的打线接合，因此其制程速率快。且本发明的方法，在基板上完成电性连接后，即可接着进行电性测试，因此可实时将不良品找出并同时以打线重工方式修补，而传统的方法，其电性测试是在完成后段印刷电路板封装，才得以进行，若在此时发现不良品，其重工制程将相当复杂。因此，本发明将可大幅提升生产效率与良率。
虽然本发明已以数个较佳实施例公开如上，然而它并不是用来限定本发明，任何熟悉此项技术的人，在不脱离本发明的创作思路和范围内，当可作各种变动与修饰，因此本发明的保护范围应当以权利要求书所界定的为准。

Claims (45)

1.一种发光二极管的封装结构，该结构至少包含：
一基板，其中该基板上具有多个沟渠；
至少一发光二极管数组，位于相对应的沟渠中；
至少一驱动电路数组，位于相对应的沟渠中；以及
一第一导电连接结构，位于该至少一发光二极管数组和该至少一驱动电路数组中。
2.如权利要求1所述的结构，其特征在于，所述的封装结构还包含一印刷电路板，该印刷电路板具有至少一输出/输入接点。
3.如权利要求2所述的结构，其特征在于，所述的封装结构还包含一第二导电连接结构，位于该至少一输出/输入接点和该至少一驱动电路中。
4.如权利要求3所述的结构，其特征在于，所述的第二导电连接结构是以打线连接的方式形成。
5.如权利要求1所述的结构，其特征在于，所述的封装结构还包含一绝缘层位于该基板、发光二极管数组和驱动电路数组上。
6.如权利要求5所述的结构，其特征在于，所述的第一导电连接结构是以微影制程方法形成。
7.如权利要求6所述的结构，其特征在于，所述的微影制程方法至少包括：
图案化该绝缘层；
形成一导体材料于该绝缘层上；以及
图案化该导体材料。
8.如权利要求7所述的结构，其特征在于，所述的导体材料为金或铝等导体。
9.如权利要求1所述的结构，其特征在于，所述的发光二极管数组具有对称排列的发光二极管晶粒，该驱动电路数组亦具有对称排列的晶粒。
10.如权利要求9所述的结构，其特征在于，当进行切割时，是分别沿着该发光二极管数组的中线，和该驱动电路数组的中线。
11.如权利要求1所述的结构，其特征在于，所述的发光二极管数组具有对称排列的接脚，所述的驱动电路数组具有对称排列的晶粒，以两侧驱动电路数组一起驱动该发光二极管数组。
12.如权利要求11所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组的中线。
13.如权利要求1所述的结构，其特征在于，所述的发光二极管数组具有对称排列的接脚，该驱动电路数组具单边排列的接脚，以两侧驱动电路数组一起驱动该发光二极管数组。
14.如权利要求13所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组间的基板中线。
15.如权利要求1所述的结构，其特征在于，所述的发光二极管数组具单边排列的接脚与发光二极管晶粒，所述的驱动电路数组具单边排列的接脚。
16.如权利要求15所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组与发光二极管数组间的基板中线。
17.一种发光二极管的封装结构，用于一打印机头上，该结构至少包含：
一基板，其中该基板上具有多个沟渠；
至少一发光二极管数组，位于相对应的沟渠中；
至少一驱动电路，位于相对应的沟渠中；
一第一导电连接结构，位于该至少一发光二极管数组和该至少一驱动电路中；
一印刷电路板，具有至少一输出/输入接脚，其中该基板位于该印刷电路板上；以及
一第二导电连接结构，位于该至少一输出/输入接脚和该至少一驱动电路中。
18.如权利要求17所述的结构，其特征在于，所述的第二导电连接结构是以打线连接的方式形成。
19.如权利要求17所述的结构，其特征在于，所述的封装结构还包含一绝缘层位于该基板、该发光二极管数组和该驱动电路上。
20.如权利要求19所述的结构，其特征在于，所述的第一导电连接结构是以微影制程方法形成。
21.如权利要求20所述的结构，其特征在于，所述的微影制程方法至少包括：
图案化该绝缘层；
形成一导体材料于该绝缘层上；以及
图案化该导体材料。
22.如权利要求21所述的结构，其特征在于，所述的导体材料为金或铝。
23.如权利要求17所述的结构，其特征在于，所述的发光二极管数组具有对称排列的发光二极管晶粒，所述的驱动电路数组也具有对称排列的晶粒。
24.如权利要求23所述的结构，其特征在于，当进行切割时，是分别沿着该发光二极管数组的中线，和该驱动电路数组的中线。
25.如权利要求17所述的结构，其特征在于，所述的发光二极管数组具有对称排列的接脚，所述的驱动电路数组具有对称排列的晶粒，以两侧驱动电路数组一起驱动该发光二极管数组。
26.如权利要求25所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组的中线。
27.如权利要求17所述的结构，其特征在于，所述的发光二极管数组具有对称排列的接脚、该驱动电路数组具有单边排列的接脚，以两侧驱动电路数组一起驱动该发光二极管数组。
28.如权利要求27所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组间的基板中线。
29.如权利要求17所述的结构，其特征在于，所述的发光二极管数组具有单边排列的接脚与发光二极管晶粒，该驱动电路数组具有单边排列的接脚。
30.如权利要求29所述的结构，其特征在于，当进行切割时，是沿着该驱动电路数组与发光二极管数组间的基板中线。
31.一种发光二极管的封装方法，该方法至少包含：
形成多个沟渠结构于一基板上；
放置至少一发光二极管数组于相对应的沟渠中；
放置至少一驱动电路于相对应的沟渠中；
形成一第一导电连接结构于该至少一发光二极管数组和该至少一驱动电路中；
切割该基板以形成多个封装单元；
黏附该些封装单元于一印刷电路板上，其中该印刷电路板具有至少一输出/输入接点；以及
形成一第二导电连接结构于该至少一输出/输入接点和该些封装单元间。
32.如权利要求31所述的方法，其特征在于，所述的第二导电连接结构是以打线连接的方式形成。
33.如权利要求32所述的方法，其特征在于，所述的方法还包含形成一绝缘层于该基板、该发光二极管数组和该驱动电路上。
34.如权利要求33所述的方法，其特征在于，形成一第一导电连接结构还包含：
图案化该绝缘层；
形成一导体材料于该绝缘层上；以及
图案化该导体材料。
35.如权利要求34所述的方法，其特征在于，所述的导体材料为金或铝等导体。
36.如权利要求31所述的方法，其特征在于，每一该封装单元至少包括一驱动电路数组和一发光二极管数组。
37.如权利要求31所述的方法，其特征在于，每一该封装单元至少包括二驱动电路数组和一发光二极管数组。
38.如权利要求36所述的方法，其特征在于，所述的发光二极管数组具有对称排列的发光二极管晶粒、该驱动电路数组也具有对称排列的晶粒。
39.如权利要求38所述的方法，其特征在于，当进行切割时，是分别沿着该发光二极管数组的中线，和该驱动电路数组的中线。
40.如权利要求36所述的方法，其特征在于，所述的发光二极管数组具有单边排列的接脚与发光二极管晶粒，所述的驱动电路数组具有单边排列的接脚。
41.如权利要求40所述的方法，其特征在于，当进行切割时，是沿着该驱动电路数组与发光二极管数组间的基板中线。
42.如权利要求37所述的方法，其特征在于，所述的发光二极管数组具有对称排列的接脚，所述的驱动电路数组具有对称排列的晶粒，以两侧驱动电路数组一起驱动该发光二极管数组。
43.如权利要求42所述的方法，其特征在于，当进行切割时，是沿着该驱动电路数组的中线。
44.如权利要求37所述的方法，其特征在于，所述的发光二极管数组具有对称排列的接脚，所述的驱动电路数组具单边排列的接脚，以两侧驱动电路数组一起驱动该发光二极管数组。
45.如权利要求44所述的方法，其特征在于，当进行切割时，是沿着该驱动电路数组间的基板中线。
CNA2005100094052A 2005-02-03 2005-02-03 发光二极管数组封装结构及其方法 Pending CN1815734A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101413646B (zh) * 2007-10-19 2010-09-22 环隆电气股份有限公司 多波长发光模块
WO2012011933A1 (en) 2010-07-23 2012-01-26 Tessera, Inc. Microelectronic elements with post-assembly planarization
CN101554803B (zh) * 2008-04-07 2012-05-16 环旭电子股份有限公司 具有高密度电连接的嵌入式构装结构模块的制作方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101413646B (zh) * 2007-10-19 2010-09-22 环隆电气股份有限公司 多波长发光模块
CN101554803B (zh) * 2008-04-07 2012-05-16 环旭电子股份有限公司 具有高密度电连接的嵌入式构装结构模块的制作方法
WO2012011933A1 (en) 2010-07-23 2012-01-26 Tessera, Inc. Microelectronic elements with post-assembly planarization
US9659812B2 (en) 2010-07-23 2017-05-23 Tessera, Inc. Microelectronic elements with post-assembly planarization
EP2596689A4 (en) * 2010-07-23 2017-07-26 Tessera, Inc. Microelectronic elements with post-assembly planarization
US9966303B2 (en) 2010-07-23 2018-05-08 Tessera, Inc. Microelectronic elements with post-assembly planarization
US10559494B2 (en) 2010-07-23 2020-02-11 Tessera, Inc. Microelectronic elements with post-assembly planarization

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