CN1794404A - Panel display having precise location trap anode array strcture and its manufacturing technology - Google Patents
Panel display having precise location trap anode array strcture and its manufacturing technology Download PDFInfo
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Abstract
This invention relates to a panel display with an accurate location trap cathode array structure and its process method, in which, said display includes a sealed vacuum cavity composed of a cathode panel, an anode panel and surrounding glasses, a photoetched anode conduction layer on the anode panel and a fluorescence powder layer on the anode conduction layer, a supporting wall structure and getters, an accurate location trap cathode array structure prepared on the cathode panel capable of determining the growing position of the carbon nm tube cathode and controlling its location, length and number and integrating with the control grating to reduce distances between them and avoid short circuit.
Description
Technical field
The invention belongs to the mutual crossing domain in Display Technique field, plane, microelectronics science and technology field, vacuum science and technical field and nanoscale science and technology field, relate to the element manufacturing of panel field emission display, be specifically related to the content of element manufacturing aspect of the panel field emission display of carbon nanotube cathod, specially refer to the manufacture craft that has a kind of accurate location field emission flat panel display device trap cathode array structural, carbon nanotube cathod.
Background technology
In nearest several years, flat-panel monitor is with its high definition, panelized, and high image quality and in light weight, advantages such as slimming have obtained approval widely, and its range of application is also more and more wider.The field emission flat-panel display that utilizes carbon nano-tube to make as cathode material is a kind of emerging planar device, except total characteristic with flat-panel display device, also has high display brightness, the visual angle is wide, be suitable for distinct advantages such as the big and response speed of warm area is fast, caused showing great attention to of numerous researchers, it is used more and more widely, has sizable development space future.
Carbon nano-tube is a kind of coaxial tubulose material, can launch a large amount of electronics under the alive outside situation, have little tip curvature radius, high aspect rate, excellent conducting performance and outstanding field emission characteristics are the splendid cold cathode emissive materials of a kind of performance.At present, the preparation method who is used for carbon nanotube cathod is broadly divided into two kinds, that is: direct growth method and grafting.Adopt grafting can carry out large-area carbon nanotube cathod and make, but the launching effect of carbon nanotube cathod is less better.The field emission characteristics of the carbon nanotube cathod of direct growth method preparation is better than the field emission characteristics of the carbon nanotube cathod of other implantation method preparation, it is more even to have emission current, emission is big, plurality of advantages such as emission current is more stable, this be with the carbon nanotube cathod of grafting preparation can't be comparable.But be subjected to the restriction of other device architecture, as cathode substrate material the temperature limitation that can bear, the thermal expansion problem of cathode substrate material and the material of cathode substrate material are selected or the like, are all restricting the application of the carbon nano-tube of direct growth method preparation.In addition, how making full use of on the basis that the direct growth legal system is equipped with the good field emission characteristics that carbon nanotube cathod has, control gate electrode structure and carbon nanotube cathod structure are organically combined, thereby promote the Highgrade integration development of integral device, this also is the realistic problem that needs emphasis to consider.
In the made of carbon nanotubes process of direct growth method, need the parameters such as position, quantity, length and directionality of effective controlling carbon nanotube, can prepare the better cathode material of performance.Need the position of effective controlling carbon nanotube negative electrode, can go out carbon nanotube cathod, then do not have carbon nanotube cathod in the zone of needs at required region growing; The quantity that needs effective controlling carbon nanotube negative electrode can farthest be brought into play the field emission performance of carbon nanotube cathod, avoids the current interference effect between the carbon nano-tube; Need the length of effective controlling carbon nanotube negative electrode, can control the distance between carbon nanotube cathod and the grid, avoid the generation of short circuit phenomenon between the two, also avoid surplus carbon nanotube arbitrarily conduction and the unpredictable consequence brought; Need the directionality of effective controlling carbon nanotube negative electrode, the High-Field that can bring into play carbon nanotube cathod effectively causes emissivities.For the problems referred to above, also there is not more efficiently solution in present device architecture and the manufacture craft.
In addition, in the middle of the panel field emission display spare of three-stage structure, guaranteeing that grid structure has carbon nanotube cathod under the prerequisite of good control action, also need to reduce as much as possible the total device cost, carry out reliable and stable, with low cost, function admirable, high quality devices is made.
Summary of the invention
The objective of the invention is to overcome the shortcoming that exists in the above-mentioned flat-panel display device and provide a kind of with low cost, manufacturing process is reliable and stable, be made into the power height, the flat-panel display device and the manufacture craft thereof that have accurate location trap cathode array structural simple in structure.
The object of the present invention is achieved like this:
A kind of flat-panel monitor that has accurate location trap cathode array structural, comprise by negative electrode panel, anode plate and all around glass enclose the sealed vacuum chamber that frame constitutes; The phosphor powder layer on anode conductive layer at anode conductive layer that photoetching is arranged on the anode plate and preparation; Supporting wall structure and getter subsidiary component are manufactured with accurate location trap cathode array structural on the negative electrode panel.
Accurately location trap cathode array structural comprises backing material silicon chip, one deck cathode conductive layer on the lower surface evaporation of backing material silicon chip, is coated with cathode coating on cathode conductive layer, the backing material silicon chip is provided with one-level location trap, secondary location trap, one-level location trap is positioned at the upper surface of silicon chip, present " U " font structure, to the silicon chip inner recess; Secondary location trap is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; The degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip, there is a dielectric isolation layer in upper surface at the backing material silicon chip, on dielectric isolation layer, there is a grid conducting layer, on grid conducting layer, there is a grid cover layer, have a catalyst metal layer in the trap of secondary location, preparation has carbon nanotube cathod on catalyst metal layer.
Grid conducting layer is one of gold, silver, copper, tin, indium, aluminium; The grid cover layer that is used for that whole gate electrodes is covered that exists above of grid conducting layer is a silicon dioxide layer, and there is silicon dioxide layer in one-level location trap inner surface.
There is a catalyst metal layer in the secondary location trap of described accurate location trap cathode array structural, one of this catalyst metal layer iron, cobalt, nickel, chromium, catalyst metal layer is positioned in the middle of the trap of secondary location fully, and is no more than the last plane of secondary location trap.
The lower surface of the backing material silicon chip of described accurate location trap cathode array structural exists a cathode conductive layer, one of these cathode conductive layer gold, silver, copper, aluminium, tin, indium; The cathode coating that is used for that cathode conductive layer is all covered that exists above of cathode conductive layer is a silicon dioxide layer.
A kind of manufacture craft that has the flat-panel monitor of accurate location trap cathode array structural, its manufacture craft is as follows:
The making of A, positive plate:
1), the making of anode plate: whole glass is carried out scribing, remove dust and impurity, form anode plate;
2), the making of anode conductive layer: evaporation one deck tin indium oxide rete on anode plate; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode conductive layer;
3), the making of insulation paste layer: in conjunction with silk-screen printing technique, non-display area printing insulation paste layer at anode conductive layer, after under 150 ℃ ± 10 ℃ temperature conditions, toasting 5～15 minutes, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
4), the making of phosphor powder layer: in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer on anode conductive layer is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
The making of B, negative electrode panel: whole plate glass is carried out cutting, remove surface impurity, form the negative electrode panel; And will accurately locate the trap cathode array structural and be fixed on the negative electrode panel;
The assembling of C, device: with negative electrode panel, anode plate and glass enclose frame, supporting wall structure is assembled together, and getter is put in the middle of the cavity, fixes with glass powder with low melting point, has smeared glass powder with low melting point around face glass, fix with clip;
D, finished product are made:
The device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
Accurately location trap cathode array structural comprises backing material silicon chip, cathode conductive layer, cathode coating, one-level location trap, secondary location trap, dielectric isolation layer, grid conducting layer, grid cover layer, catalyst metal layer and carbon nanotube cathod part, and adopts following technology to make:
1), the making of backing material silicon chip: whole silicon chip is carried out cutting, produce the backing material silicon chip;
2), the making of cathode conductive layer: at the lower surface evaporation last layer metallic aluminium of backing material silicon chip,, the metal aluminium lamination is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3), the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material silicon chip, as cathode coating; This silicon dioxide layer will cover the lower surface of cathode conductive layer and silicon chip fully;
4), the making of one-level location trap: in conjunction with conventional photoetching process, the upper surface of backing material silicon chip is carried out etching, produce one-level location trap; One-level location trap is positioned at the upper surface of silicon chip, presents " U " font structure, to the silicon chip inner recess;
5), the making of secondary location trap: in conjunction with conventional photoetching process, the bottom side of one-level location trap is carried out secondarily etched, produce secondary location trap; Secondary location trap is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; And the degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip;
6), the making of dielectric isolation layer: prepare the layer of silicon dioxide layer at the upper surface of backing material silicon chip,, silicon dioxide layer is carried out etching, form dielectric isolation layer in conjunction with conventional photoetching process; This dielectric isolation layer is kept apart cathode construction and grid structure mutually;
7), the making of grid conducting layer: evaporation layer of metal aluminium on dielectric isolation layer, in conjunction with conventional photoetching process, the metal aluminium lamination is carried out etching then, form grid conducting layer;
8), the tectal making of grid: on grid conducting layer, prepare the layer of silicon dioxide layer,, silicon dioxide layer is carried out etching, form the grid cover layer in conjunction with conventional photoetching process; This grid cover layer will all cover whole grid conducting layers, and also will cover the inner surface of one-level location trap,
9), the making of catalyst metal layer: at the surperficial evaporation layer of metal cobalt of secondary location trap, the conventional photoetching process of combination is carried out etching to layer of metal cobalt then, produces catalyst metal layer; Catalyst metal layer is positioned in the middle of the trap of secondary location fully, can not surpass the last plane of secondary location trap;
10), the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth method, grows carbon nanotube cathod in the trap of secondary location.
The present invention has following good effect:
Main characteristics among the present invention are to have made accurate location trap cathode array structural, and have made and have the accurate location field emission flat light-emitting display device trap cathode array structural, carbon nanotube cathod.
At first, in the accurate location trap cathode array structural in the present invention, on the backing material silicon chip, make one-level location well structure, be used to locate the position of carbon nanotube cathod.When after applying appropriate voltage on the grid, will form powerful electric field strength on the carbon nano tube surface top, force carbon nano-tube to launch a large amount of electronics, form awkward silence at a meeting and cause the emission phenomenon.Simultaneously,, made secondary location well structure again, be used for carrying out once more the accurate location of carbon nanotube cathod in the bottom side of one-level location trap.As everyone knows, although one-level location trap has been determined the position of carbon nanotube cathod on silicon chip, be used for mutual correspondence with the phosphor anode layer; But, for the carbon nanotube cathod that is positioned at one-level location trap, be generally speaking can't carry out pinpoint, but arbitrarily be distributed in one-level location trap around; Because the upper surface at one-level location trap exists the control grid, voltage that this grid applies will form certain electric field strength on the carbon nano-tube top so, obviously, the formed electric field strength of carbon nanotube cathod that is positioned at one-level location trap sidewall and bottom side is inequality, and electron emission ability is also just different; In addition, because the random distribution of carbon nanotube cathod in the trap of one-level location causes the generation of short circuit phenomenon between carbon nanotube cathod and the control grid extremely easily.Accurately locating in the trap cathode array structural, utilizing secondary location well structure just to solve the problems referred to above.Because catalyst metal layer only is positioned in the middle of the trap of secondary location, sidewall at one-level location trap does not have catalyst, therefore, after low temperature direct growth method has prepared carbon nanotube cathod, just only have carbon nanotube cathod in the trap of secondary location, this has also just thoroughly solved the random distribution problem of carbon nano-tube.In addition, be distributed in the middle of the trap of secondary location,, also just do not have the phenomenon of carbon nanotube cathod and the random short circuit of control grid as long as effectively controlled in the growth course after the length of carbon nanotube cathod because carbon nano-tube is concentrated.
The second, in the accurate location trap cathode array structural in the present invention, the backing material silicon chip has served as the backing material of whole accurate location trap cathode array structural, the effect of also having served as cathode conductive layer on the other hand on the one hand.When after applying appropriate voltage on the doped silicon wafer, just this voltage has been applied to above the carbon nanotube cathod.In addition, this structure is integrated together grid structure and carbon nanotube cathod structure height, helps further reducing the production cost of device, improves the display resolution of integral device.In the following table of backing material silicon chip and made cathode conductive layer, this is in order to remedy the more weak shortcoming of conductive wafer ability; And made cathode coating on the surface of cathode conductive layer, and the whole coverings of the lower surface of cathode conductive layer and silicon chip are got up, avoid in the process that device connects, leaky occurring, help improving the power that is made into of integral device.
The 3rd, in the accurate location trap cathode array structural in the present invention, made catalyst metal layer in the bottom side of secondary location trap, this has just done sufficient preparation for the growth of carbon nanotube cathod in the subsequent technique.Like this, just can locate in the trap direct growth carbon nanotube cathod at secondary, also just make grid structure and carbon nanotube cathod height be integrated together, both simplified the manufacture craft of integral device, also help further improving simultaneously the display resolution of integral device.
The 4th, in the accurate location trap cathode array structural in the present invention, utilize catalyst metal layer as catalyst, can carry out low temperature direct growth carbon nanotube cathod.By the control catalyst metal layer thickness, just the quantity of controlling carbon nanotube negative electrode effectively can make carbon nanotube cathod bring into play bigger usefulness in the process of field emitted electron, reduces the current interference effect between the carbon nanotube cathod.
In addition, in the accurate location trap cathode array structural in the present invention, do not adopt special structure fabrication material, do not adopt special device making technics yet, this has just further reduced the cost of manufacture of whole flat-panel display device to a great extent, simplify the manufacturing process of device, can carry out large-area element manufacturing, helped carrying out business-like large-scale production.
Description of drawings
Fig. 1 has provided the vertical structure schematic diagram of accurate location trap cathode array structural;
Fig. 2 has provided the transversary schematic diagram of accurate location trap cathode array structural;
Fig. 3 has provided and has had the accurate location structural representation trap cathode array structural, the carbon nanotube field emission flat-panel screens.
Embodiment
Below in conjunction with drawings and Examples the present invention is further specified, but the present invention is not limited to these embodiment.
The present invention includes by negative electrode panel 15, anode plate 11 and all around glass enclose the sealed vacuum chamber that frame 16 is constituted; The phosphor powder layer 14 on anode conductive layer 12 at anode conductive layer 12 that photoetching is arranged on the anode plate 11 and preparation; Supporting wall structure 17 and getter subsidiary component 18 are on the negative electrode panel 15] be manufactured with accurate location trap cathode array structural.
Accurately location trap cathode array structural comprises backing material silicon chip 1, one deck cathode conductive layer 2 on the lower surface evaporation of backing material silicon chip, is coated with cathode coating 3 on cathode conductive layer 2, the backing material silicon chip is provided with one-level location trap 4, secondary location trap 5, one-level location trap is positioned at the upper surface of silicon chip, present " U " font structure, to the silicon chip inner recess; Secondary location trap is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; The degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip, there is a dielectric isolation layer 6 in upper surface at the backing material silicon chip, on dielectric isolation layer 6, there is a grid conducting layer 7, on grid conducting layer 7, there is a grid cover layer 8, have a catalyst metal layer 9 in the trap of secondary location, preparation has carbon nanotube cathod 10 on catalyst metal layer 9.
Grid conducting layer 7 is one of gold, silver, copper, tin, indium, aluminium; The grid cover layer 8 that is used for whole gate electrodes is covered that exists above of grid conducting layer 7 is silicon dioxide layer, and there is silicon dioxide layer in one-level location trap inner surface.
There is a catalyst metal layer in the secondary location trap of described accurate location trap cathode array structural, one of this catalyst metal layer iron, cobalt, nickel, chromium, catalyst metal layer is positioned in the middle of the trap of secondary location fully, and is no more than the last plane of secondary location trap.
The lower surface of the backing material silicon chip of described accurate location trap cathode array structural exists a cathode conductive layer, one of these cathode conductive layer gold, silver, copper, aluminium, tin, indium; The cathode coating 3 that is used for cathode conductive layer is all covered that exists above of cathode conductive layer 2 is silicon dioxide layer.
The present invention by negative electrode panel, anode plate and all around glass enclose the sealed vacuum chamber that frame constitutes; The phosphor powder layer on anode conductive layer at anode conductive layer that photoetching is arranged on the anode plate and preparation; Accurate location trap cathode array structural is arranged on the negative electrode panel, be used to control grid and the carbon nanotubes grown negative electrode that electronics is launched; Supporting wall structure and getter subsidiary component.On the negative electrode panel, made accurate location trap cathode array structural, can determine the growth position of carbon nanotube cathod accurately, the location, length and the quantity that are used for the controlling carbon nanotube negative electrode, on the basis that utilizes the good field emission characteristics of direct growth method carbon nanotube cathod, be integrated together with the control gate height, can effectively reduce the distance between the two, avoid the generation of short circuit phenomenon.Help further improving the display resolution of flat-panel display device, simplify the manufacture craft of device, reduce the cost of manufacture of device.
The fixed position of the accurate location trap cathode array structural among the present invention is for being fixed on the negative electrode panel; Cathode construction and grid structure in the accurate location trap cathode array structural among the present invention highly are integrated together; The backing material of the accurate location trap cathode array structural among the present invention is a silicon chip; The backing material silicon chip of the accurate location trap cathode array structural among the present invention both can be the n type, also can be the p type; Backing material silicon chip in the accurate location trap cathode array structural among the present invention had both served as the backing material of accurate location trap cathode array structural, had also served as the negative electrode conductive electrode of accurate location trap cathode array structural; Having accurately location trap cathode array structural on the backing material silicon chip in the accurate location trap cathode array structural among the present invention, and be divided into two kinds of one-level location trap and secondary location traps, is to make in conjunction with conventional photoetching process; One-level location trap in the accurate location trap cathode array structural among the present invention is positioned at the upper surface of silicon chip, presents " U " font structure, to the silicon chip inner recess; Secondary location trap in the accurate location trap cathode array structural among the present invention also is positioned at the upper surface of silicon chip, but be positioned at the bottom side of one-level location trap, and continuation is to the inner recess of silicon chip, shape presents " U " font structure, its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; The degree of depth sum of one-level location trap in the accurate location trap cathode array structural among the present invention and secondary location trap can not surpass the thickness of silicon chip; There is a dielectric isolation layer in the upper surface of the backing material silicon chip in the accurate location trap cathode array structural among the present invention, and promptly silicon dioxide layer serves as the dielectric isolation layer between cathode construction and the grid structure; Have a grid conducting layer above the silicon dioxide insulator separator in the accurate location trap cathode array structural among the present invention, this grid conducting layer can be metallic gold, silver, copper, tin, indium, aluminium; Grid cover layer of top existence of grid conducting layer in the accurate location trap cathode array structural among the present invention, promptly silicon dioxide layer is used for whole gate electrodes is covered; There is silicon dioxide layer in one-level location trap inner surface in the accurate location trap cathode array structural among the present invention, and then there is not any silicon dioxide layer in the inner surface of secondary location trap; Have a catalyst metal layer in the secondary location trap in the accurate location trap cathode array structural among the present invention, this catalyst metal layer can be metallic iron, cobalt, nickel, chromium; Catalyst metal layer in the accurate location trap cathode array structural among the present invention is positioned in the middle of the trap of secondary location fully, and can not surpass the last plane of secondary location trap; There is a cathode conductive layer in the lower surface of the backing material silicon chip in the accurate location trap cathode array structural among the present invention, and this cathode conductive layer can be metallic gold, silver, copper, aluminium, tin, indium; Cathode coating of top existence of cathode conductive layer in the accurate location trap cathode array structural among the present invention, promptly silicon dioxide layer is used for cathode conductive layer is all covered; Can utilize the catalyst metals in the trap of secondary location to prepare carbon nanotube cathod in the accurate location trap cathode array structural among the present invention as catalyst.
A kind of manufacture craft that has the flat-panel monitor of accurate location trap cathode array structural, its manufacture craft is as follows:
The making of A, positive plate:
1), the making of anode plate [11]: whole glass is carried out scribing, remove dust and impurity, form anode plate [11];
2), the making of anode conductive layer [12]: evaporation one deck tin indium oxide rete on anode plate [11]; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode conductive layer [12];
3), the making of insulation paste layer [13]: in conjunction with silk-screen printing technique, non-display area printing insulation paste layer [13] at anode conductive layer [12], be used to prevent the parasitic electrons emission, after under 150 ℃ ± 10 ℃ temperature conditions, toasting 5～15 minutes, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
4), the making of phosphor powder layer [14]: in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer [14] on anode conductive layer [12] is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
The making of B, negative electrode panel [15]: whole sodium calcium plate glass is carried out cutting, remove surface impurity, form negative electrode and plate [15]; And will accurately locate the trap cathode array structural and be fixed on the negative electrode panel;
The assembling of C, device: with negative electrode panel [15], anode plate [11] and glass enclose frame [16], knee wall [17] structure is assembled together, and getter [18] put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fix with clip;
D, finished product are made: the device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
Accurate location trap cathode array structural among the present invention comprises backing material silicon chip [1], cathode conductive layer [2], cathode coating [3], one-level location trap [4], secondary location trap [5], dielectric isolation layer [6], grid conducting layer [7], grid cover layer [8], catalyst metal layer [9] and carbon nano-tube [10] cathode portion, and adopts following technology to make:
1, the making of backing material silicon chip: whole silicon chip is carried out cutting, produce the backing material silicon chip; The backing material silicon chip both can be the n type, also can be the p type; The backing material silicon chip had both served as the backing material of accurate location trap cathode array structural, had also served as the negative electrode conductive electrode of accurate location trap cathode array structural;
2, the making of cathode conductive layer: at the lower surface evaporation last layer metallic aluminium of backing material silicon chip,, the metal aluminium lamination is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3, the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material silicon chip, as cathode coating; This silicon dioxide layer will cover the lower surface of cathode conductive layer and silicon chip fully;
4, the making of one-level location trap: in conjunction with conventional photoetching process, the upper surface of backing material silicon chip is carried out etching, produce one-level location trap; One-level location trap is positioned at the upper surface of silicon chip, presents " U " font structure, to the silicon chip inner recess;
5, the making of secondary location trap: in conjunction with conventional photoetching process, the bottom side of one-level location trap [4] is carried out secondarily etched, produce secondary location trap; Secondary location trap also is positioned at the upper surface of silicon chip, but is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; And the degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip;
6, the making of dielectric isolation layer: prepare the layer of silicon dioxide layer at the upper surface of backing material silicon chip,, silicon dioxide layer is carried out etching, form dielectric isolation layer in conjunction with conventional photoetching process; This dielectric isolation layer is kept apart cathode construction and grid structure mutually;
7, the making of grid conducting layer: evaporation layer of metal aluminium on dielectric isolation layer, in conjunction with conventional photoetching process, the metal aluminium lamination is carried out etching then, form grid conducting layer;
8, the tectal making of grid: on grid conducting layer, prepare the layer of silicon dioxide layer,, silicon dioxide layer is carried out etching, form the grid cover layer in conjunction with conventional photoetching process; This grid cover layer will all cover whole grid conducting layers, and also will cover the inner surface of one-level location trap, but can not cover the inner surface of secondary location trap
9, the making of catalyst metal layer: the surperficial evaporation layer of metal cobalt at secondary location trap, in conjunction with conventional photoetching process, layer of metal cobalt is carried out etching then, produce catalyst metal layer; Catalyst metal layer is positioned in the middle of the trap of secondary location fully, can not surpass the last plane of secondary location trap;
10, the cleaning surfaces of accurately locating the trap cathode array structural is handled: clean is carried out on the surface to accurate location trap cathode array structural, removes impurity and dust;
11, the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth method, grows carbon nanotube cathod in the trap of secondary location;
12, the reprocessing of carbon nanotube cathod: adopt conventional treatment process (as pickling) that carbon nanotube cathod is carried out reprocessing, further improve the field emission characteristics of carbon nanotube cathod.
Claims (7)
1, a kind of flat-panel monitor that has accurate location trap cathode array structural, comprise by negative electrode panel [15], anode plate [11] and all around glass enclose the sealed vacuum chamber that frame [16] is constituted; The phosphor powder layer [14] on anode conductive layer [12] at anode conductive layer [12] that photoetching is arranged on the anode plate [11] and preparation; Supporting wall structure [17] and getter subsidiary component [18] is characterized in that: [15] are manufactured with accurate location trap cathode array structural on the negative electrode panel.
2, a kind of flat-panel monitor that has accurate location trap cathode array structural according to claim 1, it is characterized in that: accurately locate the trap cathode array structural comprise backing material silicon chip [1], at one deck cathode conductive layer [2] on the lower surface evaporation of backing material silicon chip, on cathode conductive layer [2], be coated with cathode coating [3], the backing material silicon chip is provided with one-level location trap [4], secondary location trap [5], one-level location trap is positioned at the upper surface of silicon chip, present " U " font structure, to the silicon chip inner recess; Secondary location trap is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; The degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip, there is a dielectric isolation layer [6] in upper surface at the backing material silicon chip, go up an existence grid conducting layer [7] at dielectric isolation layer [6], go up an existence grid cover layer [8] at grid conducting layer [7], have a catalyst metal layer [9] in the trap of secondary location, going up preparation at catalyst metal layer [9] has carbon nanotube cathod [10].
3, a kind of flat-panel monitor that has accurate location trap cathode array structural according to claim 2, it is characterized in that: grid conducting layer [7] is one of gold, silver, copper, tin, indium, aluminium, the grid cover layer [8] that is used for that whole gate electrodes is covered that exists above of grid conducting layer [7] is a silicon dioxide layer, and there is silicon dioxide layer in one-level location trap inner surface.
4, a kind of flat-panel monitor that has accurate location trap cathode array structural according to claim 2, it is characterized in that: have a catalyst metal layer in the secondary location trap of described accurate location trap cathode array structural, one of this catalyst metal layer iron, cobalt, nickel, chromium, catalyst metal layer is positioned in the middle of the trap of secondary location fully, and is no more than the last plane of secondary location trap.
5, a kind of flat-panel monitor that has accurate location trap cathode array structural according to claim 2, it is characterized in that: there is a cathode conductive layer in the lower surface of the backing material silicon chip of described accurate location trap cathode array structural, one of these cathode conductive layer gold, silver, copper, aluminium, tin, indium, the cathode coating [3] that is used for that cathode conductive layer is all covered that exists above of cathode conductive layer [2] is a silicon dioxide layer.
6, a kind of manufacture craft that has the flat-panel monitor of accurate location trap cathode array structural, it is characterized in that: its manufacture craft is as follows:
The making of A, positive plate:
1), the making of anode plate [11]: whole glass is carried out scribing, remove dust and impurity, form anode plate [11];
2), the making of anode conductive layer [12]: evaporation one deck tin indium oxide rete on anode plate [11]; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode conductive layer [12];
3), the making of insulation paste layer [13]: in conjunction with silk-screen printing technique, non-display area printing insulation paste layer [13] at anode conductive layer [12], after under 150 ℃ ± 10 ℃ temperature conditions, toasting 5～15 minutes, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
4), the making of phosphor powder layer [14]: in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer [14] on anode conductive layer [12] is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
The making of B, negative electrode panel [15]: whole plate glass is carried out cutting, remove surface impurity, form negative electrode panel [15]; And will accurately locate the trap cathode array structural and be fixed on the negative electrode panel;
The assembling of C, device: with negative electrode panel [15], anode plate [11] and glass enclose frame [16], supporting wall structure [17] is assembled together, and getter [18] put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fix with clip;
D, finished product are made:
The device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
7, a kind of manufacture craft that has the flat-panel monitor of accurate location trap cathode array structural according to claim 6, it is characterized in that: accurately locate the trap cathode array structural and comprise backing material silicon chip [1], cathode conductive layer [2], cathode coating [3], one-level location trap [4], secondary location trap [5], dielectric isolation layer [6], grid conducting layer [7], grid cover layer [8], catalyst metal layer [9] and carbon nanotube cathod part [10], and adopt following technology to make:
1), the making of backing material silicon chip: whole silicon chip is carried out cutting, produce the backing material silicon chip;
2), the making of cathode conductive layer: at the lower surface evaporation last layer metallic aluminium of backing material silicon chip,, the metal aluminium lamination is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3), the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material silicon chip, as cathode coating; This silicon dioxide layer will cover the lower surface of cathode conductive layer and silicon chip fully;
4), the making of one-level location trap: in conjunction with conventional photoetching process, the upper surface of backing material silicon chip is carried out etching, produce one-level location trap; One-level location trap is positioned at the upper surface of silicon chip, presents " U " font structure, to the silicon chip inner recess;
5), the making of secondary location trap: in conjunction with conventional photoetching process, the bottom side of one-level location trap [4] is carried out secondarily etched, produce secondary location trap; Secondary location trap is positioned at the bottom side of one-level location trap, and continues the inner recess to silicon chip, and shape presents " U " font structure, and its opening is less than the opening of one-level location trap, and its degree of depth also will be shallower than the degree of depth of one-level location trap; And the degree of depth sum of one-level location trap and secondary location trap can not surpass the thickness of silicon chip;
6), the making of dielectric isolation layer: prepare the layer of silicon dioxide layer at the upper surface of backing material silicon chip,, silicon dioxide layer is carried out etching, form dielectric isolation layer in conjunction with conventional photoetching process; This dielectric isolation layer is kept apart cathode construction and grid structure mutually;
7), the making of grid conducting layer: evaporation layer of metal aluminium on dielectric isolation layer, in conjunction with conventional photoetching process, the metal aluminium lamination is carried out etching then, form grid conducting layer;
8), the tectal making of grid: on grid conducting layer, prepare the layer of silicon dioxide layer,, silicon dioxide layer is carried out etching, form the grid cover layer in conjunction with conventional photoetching process; This grid cover layer will all cover whole grid conducting layers, and also will cover the inner surface of one-level location trap,
9), the making of catalyst metal layer: at the surperficial evaporation layer of metal cobalt of secondary location trap, the conventional photoetching process of combination is carried out etching to layer of metal cobalt then, produces catalyst metal layer; Catalyst metal layer is positioned in the middle of the trap of secondary location fully, can not surpass the last plane of secondary location trap;
10), the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth method, grows carbon nanotube cathod in the trap of secondary location.
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