CN1822292A - Flat panel display with integrated circular double cathode array structure and its producing process - Google Patents
Flat panel display with integrated circular double cathode array structure and its producing process Download PDFInfo
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- CN1822292A CN1822292A CN 200610017542 CN200610017542A CN1822292A CN 1822292 A CN1822292 A CN 1822292A CN 200610017542 CN200610017542 CN 200610017542 CN 200610017542 A CN200610017542 A CN 200610017542A CN 1822292 A CN1822292 A CN 1822292A
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Abstract
Said invention relates to flat panel display device having integration toroidal shape twin cathode array architecture and making technology. It contains cathode panel, anode panel and around glass enclose constituent sealed vacuum cavity, grid, cathode, anode conducting layer etched on anode panel, phosphor powder layer prepared anode conducting layer, knee wall structure and getter element. Said invention raises device electron emission efficiency with steady reliable manufacturing process, simple technology, cheaply cost, and simple structure etc advantages.
Description
Technical field
The invention belongs to the mutual crossing domain in Display Technique field, plane, microelectronics science and technology field, vacuum science and technical field and nanoscale science and technology field, the content of element manufacturing aspect that relates to a kind of panel field emission display of carbon nanotube cathod, particularly a kind of flat panel display device and manufacture craft thereof that has integrated circular double cathode array structure.
Background technology
Display device is a kind of crucial man-machine communication's equipment, is applied to widely in the middle of the various industries.And the field emission flat-panel display that utilizes carbon nano-tube to make as cathode material is a kind of novel planar device, have plurality of advantages such as definition height, display brightness height, panelized and suitable warm area be wide fully, caused showing great attention to of numerous researchers.
Carbon nano-tube is a kind of coaxial tubulose material, alive outside effect can be launched a large amount of electronics down, and it has little tip curvature radius, high aspect rate, good field emission characteristics and good physical and chemical stability are a kind of quite outstanding cold cathode emissive materials.In the middle of carbon nanotube cathod panel field emission display spare, grid structure is a relatively more crucial element, and it plays the necessary control effect to carbon nanotube cathod.So, how making full use of on the basis that the direct growth legal system is equipped with the good field emission characteristics that carbon nanotube cathod has, control gate electrode structure and carbon nanotube cathod structure are organically combined, thereby promote the Highgrade integration development of integral device, and how to select the grid structure form that is fit to, how to select the gate fabrication process that is fit to, or the like, these all are the realistic problems that needs emphasis to consider.
At present, the preparation method who is used for carbon nanotube cathod is broadly divided into two classes, that is: direct growth method and grafting.Adopt grafting can carry out large-area carbon nanotube cathod and make, but the launching effect of prepared carbon nanotube cathod is less better.The field emission characteristics of the carbon nanotube cathod of employing direct growth method preparation is better than the field emission characteristics of the carbon nanotube cathod of other implantation method preparation, the density of institute's carbon nanotubes grown is than higher, rete is also thicker, and the influence of essentially no other impurity, have emission current relatively evenly, plurality of advantages such as emission is big, emission current is more stable, this be with the carbon nanotube cathod of grafting preparation can't be comparable.
In addition, in the middle of panel field emission display spare, guaranteeing that grid structure has carbon nanotube cathod under the prerequisite of good control action, also need to reduce as much as possible the total device cost, carry out reliable and stable, with low cost, function admirable, high quality devices is made.
Summary of the invention
The objective of the invention is to overcome the shortcoming that exists in the above-mentioned flat-panel display device and provide a kind of with low cost, manufacturing process is reliable and stable, be made into the power height, flat-panel display device that has integrated circular double cathode array structure and manufacture craft thereof simple in structure.
The object of the present invention is achieved like this: comprise by negative electrode panel, anode plate and all around glass enclose the sealed vacuum chamber that frame constitutes, supporting wall structure and the getter subsidiary component at anode conductive layer that photoetching is arranged on the anode plate and preparation between phosphor powder layer, negative electrode panel and the anode plate on anode conductive layer, on the negative electrode panel, be mounted with the integrated circular double cathode array structure that grid and negative electrode are integrated together, circular negative electrode lays respectively at the inside and outside of circular grid, and its electronics emission is subjected to the control of grid structure.
Integrated circular double cathode array structure comprises backing material, the cathode conductive layer that is present in the backing material lower surface, cathode coating on the cathode conductive layer, the dielectric isolation layer that is present in the backing material upper surface, dielectric isolation layer is carried out etching, being shaped as of dielectric isolation layer after the etching is circular, expose following backing material in the middle of the annulus, the annulus outside is two semi-annular shapes, two semi-annular shapes partly expose the substrate of bottom portion material, evaporation has grid conducting layer on dielectric isolation layer, be coated with the grid cover layer at grid conducting layer, at the backing material upper surface evaporation that exposes catalyst metal layer is arranged, preparation has carbon nanotube cathod on catalyst metal layer.
Backing material is a doped silicon wafer, the backing material doped silicon wafer both can be the n type, also can be the p type, cathode conductive layer is a metal level, can be metallic gold, silver, aluminium, tin, molybdenum, one of chromium, the top existence of cathode conductive layer is used for the cathode coating that the lower surface with cathode conductive layer and whole silicon chip all covers, grid conducting layer is a metal level, can be metallic gold, silver, aluminium, tin, molybdenum, one of chromium, one of the top existence of grid conducting layer is used for the complete cover grid cover layer of grid conducting layer, and catalyst metal layer can be metallic iron, cobalt, one of nickel.
A kind of technology that has the flat-panel monitor of integrated circular double cathode array structure, its manufacture craft comprises the steps:
1), produce negative electrode panel and anode plate,
2), on the negative electrode panel, make integrated circular double cathode array structure,
3), on the anode glass panel, form anode electrode layer, at the non-display area printing insulation paste layer of anode electrode layer, the viewing area printing phosphor powder layer on anode electrode layer;
4), device assembling: cathode glass faceplate, anode glass panel, supporting wall structure glass are enclosed frame be assembled together, and getter is put in the middle of the cavity, fix with glass powder with low melting point;
5), finished product is made: the device that assembles is encapsulated.
The concrete steps of described step 2 are as follows:
1), produce backing material,
2), the making of cathode conductive layer: at backing material lower surface evaporation last layer metal,, metal level is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3), the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material,, be used for the lower surface of cathode conductive layer and silicon chip is all covered as cathode coating;
4), the making of dielectric isolation layer: prepare layer of silicon dioxide layer, i.e. dielectric isolation layer at the upper surface of backing material doped silicon wafer; In conjunction with conventional photoetching process, can carry out etching to dielectric isolation layer; This dielectric isolation layer is used for grid and negative electrode are kept apart mutually; Dielectric isolation layer after the etching should have following shape, that is: for a cathode array structural, its dielectric isolation layer should be for circular, silicon dioxide part in the middle of its annulus is etched away fully, expose following backing material, the silicon dioxide layer of its annulus outside is fallen by partial etching, promptly partial etching is carried out in the periphery near circular dielectric isolation layer, form two semi-annular shapes, requirement is removed the silicon dioxide layer of two semi-annular shape parts fully, exposes the substrate of bottom portion material;
5), the making of grid conducting layer: metal level of evaporation on dielectric isolation layer, in conjunction with conventional photoetching process, metal level is carried out etching then, form grid conducting layer;
6), the tectal making of grid: on dielectric isolation layer, prepare a silicon dioxide layer once more, in conjunction with conventional photoetching process, silicon dioxide layer is carried out etching then, form the grid cover layer; This grid cover layer is used for grid conducting layer is all covered, but can not cover the backing material of exposure;
7), the making of catalyst metal layer: in the upper surface evaporation layer of metal of the backing material that exposes, in conjunction with conventional photoetching process, metal level is carried out etching then, form catalyst metal layer;
8), the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth technology, grows carbon nanotube cathod
The concrete steps of described step 3 are as follows:
1), the making of anode glass panel: whole plate glass is carried out cutting, produce the anode glass panel;
2), the making of anode electrode layer: evaporation one deck tin indium oxide rete on the anode glass panel; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode electrode layer;
3), the making of insulation paste layer: in conjunction with silk-screen printing technique, the non-display area printing insulation paste layer at anode electrode layer is used to prevent the parasitic electrons emission; Through overbaking, baking temperature: 150 ℃, the retention time: 5 minutes, afterwards, be placed on and carry out high temperature sintering in the sintering furnace, sintering temperature: 580 ℃, the retention time: 10 minutes;
4), the making of phosphor powder layer: in conjunction with silk-screen printing technique, phosphor powder layer is printed in the viewing area on anode electrode layer; In the middle of baking oven, toast (baking temperature: 120 ℃, the retention time: 10 minutes);
5, a kind of manufacture craft that has the flat-panel monitor of integrated step type slot grid structure according to claim 4, it is characterized in that: the concrete steps of described step 4 are as follows: cathode glass faceplate, anode glass panel, supporting wall structure glass are enclosed frame be assembled together, and getter put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fixed with clip.
The concrete steps of described step 5 are as follows: the device that has assembled is carried out following packaging technology: toast in the middle of the sample device is put into baking oven; Carry out high temperature sintering in the middle of putting into sintering furnace; On exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside bake and disappears, install pin formation finished parts at last additional.
The present invention has following good effect:
Main characteristics among the present invention are to have made integrated circular double cathode array structure, and have made and have field emission flat light-emitting display device integrated circular double cathode array structure, carbon nanotube cathod.
At first, make integrated circular double cathode array structure in the present invention, greatly increased the emission area of carbon nanotube cathod, made full use of edge field emission enhancement effect.On the one hand, grid structure has been made into circular, and the growth of carbon nanotube cathod has all been carried out in the inboard and the outside at circular grid, so greatly increase the emission area of the carbon nanotube cathod in the cathode electronics launch point, improved the emission effciency of carbon nanotube cathod; On the other hand, because all preparing in the inboard of grid structure and the outside has carbon nanotube cathod, that is to say, when after applying appropriate voltage on the grid, will form powerful electric field strength on the carbon nanotube cathod top, force carbon nanotube cathod to launch a large amount of electronics, form awkward silence at a meeting and cause the emission phenomenon.Because in this integrated circular double cathode array structure, the adjacent contact area of grid and carbon nanotube cathod increases, also just utilized the edge field emission enhancement effect of carbon nanotube cathod more fully, improved the electronic transmitting efficiency of negative electrode, make that bad emission phenomenon has been subjected to inhibition to a certain degree in the carbon nanotube cathod area.
Secondly, made integrated circular double cathode array structure in the present invention, the backing material doped silicon wafer had both been served as the backing material of integrated circular double cathode array structure, had also served as the negative electrode conductive electrode of integrated circular double cathode array structure simultaneously; On dielectric isolation layer, made grid conducting layer, and prepared carbon nanotube cathod at the upper surface of the backing material silicon chip that exposes.This structure effectively is integrated together grid and carbon nanotube cathod height, helps further reducing the production cost of integral device, improves the display resolution of integral device, improves the electronic transmitting efficiency of device.
The 3rd, made integrated circular double cathode array structure in the present invention, upper surface at the backing material silicon chip that exposes has been made catalyst metal layer, this has just done sufficient preparation for the growth of the carbon nanotube cathod in the subsequent technique, so just can directly carry out the growth of carbon nano-tube at silicon chip surface; Owing to be positioned at the inboard carbon nanotube cathod of circular dielectric isolation layer and two semi-annular shape carbon nanotube cathods in the outside all are positioned on the backing material silicon chip, therefore, in fact the two links together.In conjunction with low temperature direct growth method, carried out the preparation of carbon nanotube cathod.Like this, just made full use of the good field emission characteristics that carbon nanotube cathod had of direct growth method preparation.
In the integrated circular double cathode array structure in the present invention, do not adopt special structure fabrication material, do not adopt special device making technics yet, further reduced the cost of manufacture of whole flat-panel display device, simplify the making flow process of device, helped carrying out business-like large-scale production.
Description of drawings
Fig. 1 has provided the vertical structure schematic diagram of integrated circular double cathode array structure;
Fig. 2 has provided the transversary schematic diagram of integrated circular double cathode array structure;
Fig. 3 has provided and has had structural representation integrated circular double cathode array structure, the carbon nanotube field emission flat-panel screens.
Embodiment
The present invention includes by negative electrode panel 9, anode plate 11 and all around glass enclose the sealed vacuum chamber that frame 10 is constituted, the phosphor powder layer 14 on anode conductive layer 12 at anode conductive layer 12 that photoetching is arranged on the anode plate 11 and preparation, supporting wall structure 16 between negative electrode panel 9 and the anode plate 11 and getter subsidiary component 15, on negative electrode panel 9, be mounted with the integrated circular double cathode array structure that grid and negative electrode are integrated together, circular negative electrode lays respectively at the inside and outside of circular grid, and its electronics emission is subjected to the control of grid structure.
Integrated circular double cathode array structure comprises backing material 1, the cathode conductive layer 2 that is present in the backing material lower surface, cathode coating 3 on the cathode conductive layer 2, the dielectric isolation layer 4 that is present in the backing material upper surface, dielectric isolation layer 4 is carried out etching, being shaped as of dielectric isolation layer after the etching is circular, expose following backing material in the middle of the annulus, the annulus outside is two semi-annular shapes, two semi-annular shapes partly expose the substrate of bottom portion material, evaporation has grid conducting layer 5 on dielectric isolation layer 4, be coated with grid cover layer 6 at grid conducting layer 5, at the backing material upper surface evaporation that exposes catalyst metal layer 7 is arranged, preparation has carbon nanotube cathod 8 on catalyst metal layer 7.
The fixed position of described integrated circular double cathode array structure is for being fixed on the negative electrode panel, grid structure and cathode construction are integrated together, circular negative electrode lays respectively at the inside and outside of circular grid, its electronics emission is subjected to the control of grid structure, backing material is a doped silicon wafer, the backing material doped silicon wafer both can be the n type, also can be the p type, the backing material doped silicon wafer had both been served as the backing material of integrated circular double cathode array structure, had also served as the negative electrode conductive electrode of integrated circular double cathode array structure simultaneously.
There is a cathode conductive layer in the lower surface of the backing material silicon chip of described integrated integrated circular double cathode array structure, cathode conductive layer is a metal level, can be one of metallic gold, silver, aluminium, tin, molybdenum, chromium, the top existence of cathode conductive layer is used for the cathode coating that the lower surface with cathode conductive layer and whole silicon chip all covers.
The upper surface of the backing material doped silicon wafer of described integrated integrated circular double cathode array structure exists and is used for dielectric isolation layer that grid and negative electrode are kept apart mutually, dielectric isolation layer after the etching should have following shape: for a cathode array structural, its dielectric isolation layer should be for circular, silicon dioxide part in the middle of its annulus is etched away fully, expose following backing material doped silicon wafer, the silicon dioxide layer of its annulus outside is fallen by partial etching, partial etching is carried out in periphery near circular dielectric isolation layer, form two semi-annular shapes, the silicon dioxide layer of two semi-annular shape parts removes fully, exposes the material doped silicon chip of substrate of bottom portion.
Have grid conducting layer above the dielectric isolation layer of described integrated circular double cathode array structure, grid conducting layer is one of metal gold, silver, aluminium, tin, molybdenum, chromium, exists above the grid conducting layer to be used for grid conducting layer cover grid cover layer.Have catalyst metal layer above the backing material doped silicon wafer that integrated integrated circular double cathode array structure exposes, catalyst metal layer is one of metallic iron, cobalt, nickel.
Integrated circular double cathode array structure among the present invention comprises backing material silicon chip, cathode conductive layer, cathode coating, dielectric isolation layer, grid conducting layer, grid cover layer, catalyst metal layer, carbon nanotube cathod part, and adopts following technology to make:
1, the making of backing material silicon chip: whole silicon chip is carried out cutting, produce the backing material doped silicon wafer; This silicon chip is a doped silicon wafer, both can be the n type, also can be the p type; The backing material doped silicon wafer had both been served as the backing material of integrated circular double cathode array structure, had also served as the negative electrode conductive electrode of integrated circular double cathode array structure simultaneously;
2, the making of cathode conductive layer: in the lower surface evaporation last layer metal molybdenum of backing material doped silicon wafer,, the metal molybdenum layer is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3, the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material doped silicon wafer,, be used for the lower surface of cathode conductive layer and silicon chip is all covered as cathode coating;
4, the making of dielectric isolation layer: prepare layer of silicon dioxide layer, i.e. dielectric isolation layer at the upper surface of backing material doped silicon wafer; In conjunction with conventional photoetching process, can carry out etching to dielectric isolation layer; This dielectric isolation layer is used for grid and negative electrode are kept apart mutually; Dielectric isolation layer after the etching should have following shape, that is: for a cathode array structural, its dielectric isolation layer should be for circular, silicon dioxide part in the middle of its annulus is etched away fully, expose following backing material doped silicon wafer, the silicon dioxide layer of its annulus outside is fallen by partial etching, promptly partial etching is carried out in the periphery near circular dielectric isolation layer, form two semi-annular shapes, requirement is removed the silicon dioxide layer of two semi-annular shape parts fully, exposes the material doped silicon chip of substrate of bottom portion;
5, the making of grid conducting layer: metallic chromium layer of evaporation on dielectric isolation layer, in conjunction with conventional photoetching process, metallic chromium layer is carried out etching then, form grid conducting layer;
6, the tectal making of grid: on dielectric isolation layer, prepare a silicon dioxide layer once more, in conjunction with conventional photoetching process, silicon dioxide layer is carried out etching then, form the grid cover layer; This grid cover layer is used for grid conducting layer is all covered, but can not cover the backing material doped silicon wafer of exposure;
7, the making of catalyst metal layer: at the upper surface evaporation layer of metal cobalt of the backing material doped silicon wafer that exposes, in conjunction with conventional photoetching process, layer of metal cobalt is carried out etching then, form catalyst metal layer;
8, the cleaning surfaces of integrated circular double cathode array structure is handled: clean is carried out on the surface to integrated circular double cathode array structure, removes impurity and dust;
9, the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth technology, grows carbon nanotube cathod.
The manufacture craft of carbon nanotube field emission flat-panel monitor that has integrated circular double cathode array structure among the present invention is as follows:
1, the making of backing material silicon chip: whole silicon chip is carried out cutting, produce the backing material doped silicon wafer; This silicon chip is a doped silicon wafer, both can be the n type, also can be the p type; The backing material doped silicon wafer had both been served as the backing material of integrated circular double cathode array structure, had also served as the negative electrode conductive electrode of integrated circular double cathode array structure simultaneously;
2, the making of cathode conductive layer: in the lower surface evaporation last layer metal molybdenum of backing material doped silicon wafer,, the metal molybdenum layer is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3, the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material doped silicon wafer,, be used for the lower surface of cathode conductive layer and silicon chip is all covered as cathode coating;
4, the making of dielectric isolation layer: prepare layer of silicon dioxide layer, i.e. dielectric isolation layer at the upper surface of backing material doped silicon wafer; In conjunction with conventional photoetching process, can carry out etching to dielectric isolation layer; This dielectric isolation layer is used for grid and negative electrode are kept apart mutually; Dielectric isolation layer after the etching should have following shape, that is: for a cathode array structural, its dielectric isolation layer should be for circular, silicon dioxide part in the middle of its annulus is etched away fully, expose following backing material doped silicon wafer, the silicon dioxide layer of its annulus outside is fallen by partial etching, promptly partial etching is carried out in the periphery near circular dielectric isolation layer, form two semi-annular shapes, requirement is removed the silicon dioxide layer of two semi-annular shape parts fully, exposes the material doped silicon chip of substrate of bottom portion;
5, the making of grid conducting layer: metallic chromium layer of evaporation on dielectric isolation layer, in conjunction with conventional photoetching process, metallic chromium layer is carried out etching then, form grid conducting layer;
6, the tectal making of grid: on dielectric isolation layer, prepare a silicon dioxide layer once more, in conjunction with conventional photoetching process, silicon dioxide layer is carried out etching then, form the grid cover layer; This grid cover layer is used for grid conducting layer is all covered, but can not cover the backing material doped silicon wafer of exposure;
7, the making of catalyst metal layer: at the upper surface evaporation layer of metal cobalt of the backing material doped silicon wafer that exposes, in conjunction with conventional photoetching process, layer of metal cobalt is carried out etching then, form catalyst metal layer;
8, the cleaning surfaces of integrated circular double cathode array structure is handled: clean is carried out on the surface to integrated circular double cathode array structure, removes impurity and dust;
9, the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth technology, grows carbon nanotube cathod;
10, the making of anode glass panel: whole sodium calcium plate glass is carried out cutting, produce the anode glass panel;
12, the making of anode electrode layer: evaporation one deck tin indium oxide rete on the anode glass panel; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode electrode layer;
13, the making of insulation paste layer: in conjunction with silk-screen printing technique, the non-display area printing insulation paste layer at anode electrode layer is used to prevent the parasitic electrons emission; Through overbaking (baking temperature: 150 ℃, retention time: 5 minutes) afterwards, be placed on and carry out high temperature sintering (sintering temperature: 580 ℃, retention time: 10 minutes) in the sintering furnace;
14, the making of phosphor powder layer: in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer on anode electrode layer; In the middle of baking oven, toast (baking temperature: 120 ℃, the retention time: 10 minutes);
15, device assembling: cathode glass faceplate, anode glass panel, supporting wall structure glass are enclosed frame be assembled together, and getter is put in the middle of the cavity, fix with glass powder with low melting point.Around face glass, smeared glass powder with low melting point, fixed with clip.
16, finished product is made: the device that has assembled is carried out following packaging technology: toast in the middle of the sample device is put into baking oven; Carry out high temperature sintering in the middle of putting into sintering furnace; On exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside bake and disappears, install pin formation finished parts at last additional.
Claims (8)
1, a kind of flat-panel monitor that has integrated circular double cathode array structure, comprise by negative electrode panel [9], anode plate [11] and all around glass enclose the sealed vacuum chamber that frame [10] is constituted, the phosphor powder layer [14] on anode conductive layer [12] at anode conductive layer [12] that photoetching is arranged on the anode plate [11] and preparation, supporting wall structure [16] between negative electrode panel [9] and the anode plate [11] and getter subsidiary component [15], it is characterized in that: on negative electrode panel [9], be mounted with the integrated circular double cathode array structure that grid and negative electrode are integrated together, circular negative electrode lays respectively at the inside and outside of circular grid, and its electronics emission is subjected to the control of grid structure.
2, a kind of flat-panel monitor that has integrated circular double cathode array structure according to claim 1, it is characterized in that: integrated circular double cathode array structure comprises backing material [1], the cathode conductive layer [2] that is present in the backing material lower surface, cathode coating [3] on the cathode conductive layer [2], the dielectric isolation layer [4] that is present in the backing material upper surface, dielectric isolation layer [4] is carried out etching, being shaped as of dielectric isolation layer after the etching is circular, expose following backing material in the middle of the annulus, the annulus outside is two semi-annular shapes, two semi-annular shapes partly expose the substrate of bottom portion material, evaporation has grid conducting layer [5] on dielectric isolation layer [4], be coated with grid cover layer [6] at grid conducting layer [5], at the backing material upper surface evaporation that exposes catalyst metal layer [7] is arranged, going up preparation at catalyst metal layer [7] has carbon nanotube cathod (8).
3, a kind of flat-panel monitor that has integrated circular double cathode array structure according to claim 2, it is characterized in that: backing material is a doped silicon wafer, the backing material doped silicon wafer both can be the n type, also can be the p type, cathode conductive layer is a metal level, can be metallic gold, silver, aluminium, tin, molybdenum, one of chromium, the top existence of cathode conductive layer is used for the cathode coating that the lower surface with cathode conductive layer and whole silicon chip all covers, grid conducting layer is a metal level, can be metallic gold, silver, aluminium, tin, molybdenum, one of chromium, one of the top existence of grid conducting layer is used for the complete cover grid cover layer of grid conducting layer, and catalyst metal layer can be metallic iron, cobalt, one of nickel.
4, a kind of technology that has the flat-panel monitor of integrated circular double cathode array structure, it is characterized in that: its manufacture craft comprises the steps:
1), produce negative electrode panel and anode plate,
2), on the negative electrode panel, make integrated circular double cathode array structure,
3), on the anode glass panel, form anode electrode layer, at the non-display area printing insulation paste layer of anode electrode layer, the viewing area printing phosphor powder layer on anode electrode layer;
4), device assembling: cathode glass faceplate, anode glass panel, supporting wall structure glass are enclosed frame be assembled together, and getter is put in the middle of the cavity, fix with glass powder with low melting point;
5), finished product is made: the device that assembles is encapsulated.
5, a kind of manufacture craft that has the flat-panel monitor of integrated step type slot grid structure according to claim 4, it is characterized in that: the concrete steps of described step 2 are as follows:
1), the making of backing material silicon chip:
2), the making of cathode conductive layer: at backing material lower surface evaporation last layer metal,, metal level is carried out etching, produce cathode conductive layer in conjunction with conventional photoetching process;
3), the making of cathode coating: prepare the layer of silicon dioxide layer at the lower surface of backing material,, be used for the lower surface of cathode conductive layer and silicon chip is all covered as cathode coating;
4), the making of dielectric isolation layer: prepare layer of silicon dioxide layer, i.e. dielectric isolation layer at the upper surface of backing material doped silicon wafer; In conjunction with conventional photoetching process, can carry out etching to dielectric isolation layer; This dielectric isolation layer is used for grid and negative electrode are kept apart mutually; Dielectric isolation layer after the etching should have following shape, that is: for a cathode array structural, its dielectric isolation layer should be for circular, silicon dioxide part in the middle of its annulus is etched away fully, expose following backing material, the silicon dioxide layer of its annulus outside is fallen by partial etching, promptly partial etching is carried out in the periphery near circular dielectric isolation layer, form two semi-annular shapes, requirement is removed the silicon dioxide layer of two semi-annular shape parts fully, exposes the substrate of bottom portion material;
5), the making of grid conducting layer: metal level of evaporation on dielectric isolation layer, in conjunction with conventional photoetching process, metal level is carried out etching then, form grid conducting layer;
6), the tectal making of grid: on dielectric isolation layer, prepare a silicon dioxide layer once more, in conjunction with conventional photoetching process, silicon dioxide layer is carried out etching then, form the grid cover layer; This grid cover layer is used for grid conducting layer is all covered, but can not cover the backing material of exposure;
7), the making of catalyst metal layer: in the upper surface evaporation layer of metal of the backing material that exposes, in conjunction with conventional photoetching process, metal level is carried out etching then, form catalyst metal layer;
8), the growth of carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube in conjunction with low temperature direct growth technology, grows carbon nanotube cathod
6, a kind of manufacture craft that has the flat-panel monitor of integrated step type slot grid structure according to claim 4, it is characterized in that: the concrete steps of described step 3 are as follows:
1), the making of anode glass panel: whole plate glass is carried out cutting, produce the anode glass panel;
2), the making of anode electrode layer: evaporation one deck tin indium oxide rete on the anode glass panel; In conjunction with conventional photoetching process, tin indium oxide rete is carried out etching, form anode electrode layer;
3), the making of insulation paste layer: in conjunction with silk-screen printing technique, the non-display area printing insulation paste layer at anode electrode layer is used to prevent the parasitic electrons emission; Through overbaking, baking temperature: 150 ℃, the retention time: 5 minutes, afterwards, be placed on and carry out high temperature sintering in the sintering furnace, sintering temperature: 580 ℃, the retention time: 10 minutes;
4), the making of phosphor powder layer: in conjunction with silk-screen printing technique, phosphor powder layer is printed in the viewing area on anode electrode layer; In the middle of baking oven, toast (baking temperature: 120 ℃, the retention time: 10 minutes);
7, a kind of manufacture craft that has the flat-panel monitor of integrated step type slot grid structure according to claim 4, it is characterized in that: the concrete steps of described step 4 are as follows: cathode glass faceplate, anode glass panel, supporting wall structure glass are enclosed frame be assembled together, and getter put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fixed with clip.
8, a kind of manufacture craft that has the flat-panel monitor of integrated step type slot grid structure according to claim 4, it is characterized in that: the concrete steps of described step 5 are as follows: the device that has assembled is carried out following packaging technology: toast in the middle of the sample device is put into baking oven; Carry out high temperature sintering in the middle of putting into sintering furnace; On exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside bake and disappears, install pin formation finished parts at last additional.
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| CNB2006100175425A CN100527317C (en) | 2006-03-20 | 2006-03-20 | Flat panel display with integrated circular double cathode array structure and its producing process |
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| CNB2006100175425A CN100527317C (en) | 2006-03-20 | 2006-03-20 | Flat panel display with integrated circular double cathode array structure and its producing process |
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| CN1822292A true CN1822292A (en) | 2006-08-23 |
| CN100527317C CN100527317C (en) | 2009-08-12 |
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