CN1755921A - 倒装焊封装方法及封装结构 - Google Patents

倒装焊封装方法及封装结构 Download PDF

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CN1755921A
CN1755921A CN 200410079357 CN200410079357A CN1755921A CN 1755921 A CN1755921 A CN 1755921A CN 200410079357 CN200410079357 CN 200410079357 CN 200410079357 A CN200410079357 A CN 200410079357A CN 1755921 A CN1755921 A CN 1755921A
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杨智安
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Via Technologies Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本发明涉及一种倒装焊封装方法及封装结构,尤其涉及一种应用合金热压合的方法使芯片结合于散热片上,使芯片的热量能良好地传导至散热片,以确保芯片正常运作。该倒装焊封装方法,包括下列步骤:提供一具有一镀有金膜的表面及一裸露面的散热片;提供一芯片,该芯片有一作用表面,其上有接合点及一接合面;加热散热片并将芯片的接合面置于散热片的金膜并使之交互摩擦,由此产生金硅的交互扩散作用使芯片结合于散热片上;将芯片的作用表面以倒装焊方式设置于一基板上;及提供一底层填充,填充于芯片及基板之间。

Description

倒装焊封装方法及封装结构
技术领域
本发明涉及一种倒装焊封装方法及封装结构,其通过倒装焊方式封装半导体芯片,特别涉及一种应用合金热压合将芯片与散热片结合的方法。
背景技术
倒装焊式半导体封装技术是一种先进的半导体封装技术,该项技术与一般现有技术打线球栅阵列(WBBGA)半导体封装技术最主要的区别在于该项技术将需要封装的半导体芯片采用作用表面(即铺设有多数电子电路与电子组件的芯片表面)朝下的倒置方式安装于基板上,同时通过多个焊块(SolderBumps)焊接来提供到基板的电连接,而后采用衬垫片(Underfill)方式将一绝缘性胶料填入相邻焊块之间,使得半导体芯片得以稳固地接合在基板上。由于倒装焊式封装结构中无需使用较占空间的焊线来使半导体芯片进行电连接,因此能够有效缩减封装件的整体厚度,更符合轻薄短小的封装趋势。
但伴随着芯片的集成电路功能的持续增长,芯片在工作中所产生的热量亦随之显著成长,因此为防止芯片产生的热量无法有效释放而影响到芯片的可靠性,如何将芯片产生之热量有效释放到外界就成另一主要技术课题。特别是对于高消耗功率的产品,例如中央处理器(CPU,Central Processing Unit)及图形处理器GPU(graphics processing unit),热量释放能力是整体性能的指针。
倒装焊式半导体封装的散热性能有一个关键的因素,是散热板及芯片之间的热导接口物质(thermal interface material,TIM)。现有技术中常用于CPU的热导接口物质有树脂类散热膏,以及锡铅焊料。
图1至图3,是现有技术倒装焊式半导体的封装工艺。首先将半导体芯片20a采用作用表面朝下的倒置方式安装于基板30a上并且经过回焊炉,该基板30a底面设有多个接脚31a,其与半导体芯片20a电连接。
接着,采用衬垫片(Underfill)方式将一绝缘性胶料32a填入相邻焊块之间使得半导体芯片20a稳固地接合在基板30a上。
最后,将嵌入式散热板10a通过热导接口物质12a粘合在半导体芯片20a上。为防止水气对半导体芯片20a造成损坏,进一步还将封装胶体填充于散热板10a及基板30a之间。
上述现有技术具有以下缺点:
1、树脂类的热导接口物质的热传导率(thermal conductivity)太低,以致无法具有良好的热量释放能力。
2、树脂类的热导接口物质,容易在散热片及该芯片之间残留小气泡,经过高温时会产生气爆,以致产生裂痕使散热效果变差。
3、采用锡铅焊料装配于该芯片及散热片之间,其热阻仍然很大,另外焊料中的铅存在环保方面的隐患。
4、以锡铅焊料粘接时,由于芯片(硅)及焊料的热膨胀系数(Coefficientof Thermal Expansion,CTE)差异过大,造成二者受热形变量不一致,从而在接口产生应力集中点,容易造成剥离或芯片的裂损。
因此若能提供一种在倒装焊封装上具有良好热传导率,以提高散热能力及发挥整体性的能热导接口物质,是众人所期盼的。
发明内容
本发明的主要目的是提供一种倒装焊封装方法及封装结构,其主要是提供一种具有金属热传导率的热导接口物质,使倒装焊型芯片的热量能良好地传导至散热片而释放到外界。
本发明的另一目的是提供一种倒装焊封装方法及封装结构,其能使散热片及芯片良好结合,避免两者之间产生应力或气泡。
为了达到上述目的,本发明的倒装焊封装方法,包括下列步骤:提供一散热片,其具有一镀有金膜的表面及一裸露面;提供一芯片,系具有一作用表面,其上设有接合点,及一接合面;加热上述散热片,并将上述芯片的接合面置于散热片的金膜并使之交互磨擦,由此产生金硅的交互扩散作用使芯片结合在散热片上;将上述芯片的作用表面以倒装焊方式设置于一基板上;及提供一底层填充,充填于该芯片及该基板之间。
为了达到上述目的,本发明的倒装焊封装结构,包括一散热片,具有一镀有金膜的表面及一裸露面;一芯片,其具有一作用表面,其上设有接合点,及一接合面;形成于该散热片的该金膜及该芯片的该接合面之间的一金硅合金层;上述芯片的作用表面以倒装焊方式设置于其上的一基板;及充填于该芯片及该基板之间的一底层填充。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1是现有技术的倒装焊封装中芯片置于基板的示意图。
图2是现有技术的倒装焊封装中衬垫片的示意图。
图3是现有技术的倒装焊封装中散热片粘接于芯片的示意图。
图4是本发明的倒装焊封装方法中散热片镀金膜的示意图。
图5是本发明的倒装焊封装方法中芯片与散热片进行热压合的示意图。
图6是本发明的倒装焊封装方法中芯片粘接于散热片的示意图。
图7是本发明的倒装焊封装方法中芯片置于基板并进行衬垫的示意图。
其中,附图标记
10a-散热板
12a-热导接口物质
20a-芯片
30a-基板
31a-接脚
32a-胶料
10-散热片
12-金膜
14-裸露面
15-金硅合金层
20-芯片
21-作用表面
22-接合面
212-接合点
30-基板
32-底层填充(底部填料)
40-夹具
具体实施方式
图4至图7是本发明的倒装焊封装方法各步骤示意图。如图4所示,本发明的倒装焊封装方法首先提供一散热片10,该散热片10具有一镀有金膜12的表面及一裸露面14。
如图5所示,提供一芯片20,具有一作用表面21,其上设有接合点212,及一接合面22;并且提供一夹具40夹持该芯片20的周围,将芯片20的接合面22置于散热片10的金膜12上。
对芯片20的接合面22与散热片10的金膜12进行合金热压合;由于芯片20主要是由硅构成,因此产生金硅的交互扩散作用使该芯片20粘接于散热片10上。合金热压合是利用金—硅合金在温度363℃时产生的共晶反应特性进行粘结固着,通常加热至约425℃,由于金硅之间的交互扩散作用而形成接合。合金热压合适宜在热氮环境中进行以防止硅高温氧化。散热片10与芯片20需要施加一交互磨擦作用以除去硅氧化表层,增加反应面的润湿性。
由于交互磨擦时也会产生热能,因此加热该散热片的温度范围可以是在350℃以上、450℃以下。交互磨擦时会产生振荡能,该振荡能进而转化为熔化能,使得金膜和硅向彼此扩散。其中交互磨擦芯片20的接合面22与散热片10的金膜12的时间在15秒至25秒之间,即可形成金硅合金层15,当然其交互磨擦的时间也可以更长。由于是借助金硅的扩散作用,金硅合金层15的金与硅之间组成比例不是固定的,靠近该金膜12的部份金原子较多,而靠近该芯片10的部份硅原子较多。
由上述可知,本发明借助金硅合金层15以结合散热片及该芯片,改善现有技术中热传导率低的情况,其热传导率远大于树脂类的热导接口物质、及锡铅焊。举例来说:Au/3Si为216W/m℃,TIM为0.88W/m℃,Sn63/Pb37为51W/m℃。因此本发明的热传导率为TIM的245倍,为锡铅合金的4倍。现有技术采用树脂类的热导接口物质通常需要烘干,而锡铅焊料需要经过回焊炉高温烘烤,本发明的金硅合金层所需的时间极短,可节省工艺时间。
本发明中该散热片10可以通过一治具加以固定,并且可以利用治具加热散热片10的裸露面14。
在实际操作中,进一步也可以由夹具40加热芯片20。加热该芯片的温度较佳在150℃至200℃之间,不宜过高。
如第七图所示,当芯片20粘接固定于散热片10之后,再将芯片20的作用表面21以倒装焊方式设置于一基板30上。最后提供一底层填充32充填于芯片20及基板30之间。
由上述的倒装焊封装方法即可得到本发明的倒装焊封装结构,包括散热片10、一芯片20、形成于散热片10的该金膜12及芯片20的接合面22之间的一金硅合金层;芯片20以倒装焊方式设置于基板30上。底层填充32充填于该芯片20及该基板30之间。其中进一步可以具有一封胶体包围于散热片10的周围及基板30之间。
本发明的特点及功能如下:
一、本发明的倒装焊封装方法以具有金属热传导率的热导接口物质—金硅合金层结合散热片及芯片,使倒装焊型芯片的热量能良好地传导至散热片而释放出去。
二、本发明的倒装焊封装方法能使散热片及芯片结合良好,避免两者之间产生应力或气泡。
三、本发明的倒装焊封装方法不具有铅,不会造成环境的污染。
当然,本发明还可有其他多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1、一种倒装焊封装结构,其特征在于,包括:一散热片,具有一镀有金膜的表面及一裸露面;一芯片,具有一作用表面,其上设有接合点、及一接合面;形成于所述散热片的金膜及接合面之间的一金硅合金层,所述芯片的作用表面以倒装焊方式设置其上的一基板;及充填于该芯片及该基板之间的一底层填充。
2、按照权利要求1所述的倒装焊封装结构,其特征在于,进一步具有一封胶体包围于所述散热片的周围及所述基板之间。
3、一种倒装焊封装方法,其特征在于,包括以下步骤:
提供一散热片,其具有一镀有金膜的表面及一裸露面;
提供一芯片,该芯片具有一作用表面,其上设有多个接合点、及一接合面;及
所述芯片的接合面和散热片的金膜之间通过合金热压合,产生金硅的交互扩散作用使芯片与散热片结合;
将上述芯片的作用表面以倒装焊方式设置于一基板上;及
提供一底层填充,填充于该芯片及该基板之间。
4、按照权利要求3所述的倒装焊封装方法,其特征在于,还包括提供一夹具夹合所述芯片,以将该芯片的接合面置于散热片的金膜。
5、按照权利要求4所述的倒装焊封装方法,其特征在于,进一步包括利用所述的夹具加热所述芯片。
6、按照权利要求5所述的倒装焊封装方法,其特征在于,加热所述芯片的温度在150℃至200℃之间。
7、按照权利要求3所述的倒装焊封装方法,其特征在于,还包括提供一治具以固定该散热片。
8、按照权利要求7所述的倒装焊封装方法,其特征在于,还包括利用上述治具加热所述散热片的裸露面。
9、按照权利要求7所述的倒装焊封装方法,其特征在于,加热所述散热片的温度范围在350℃以上450℃以下。
10、按照权利要求3所述的倒装焊封装方法,其特征在于,还包括交互磨擦所述芯片的接合面与散热片的金膜。
CN 200410079357 2004-09-30 2004-09-30 倒装焊封装方法及封装结构 Pending CN1755921A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100591181C (zh) * 2007-08-24 2010-02-17 武汉华灿光电有限公司 倒装焊发光二极管芯片的制造方法
CN102909156A (zh) * 2012-10-17 2013-02-06 日月光半导体制造股份有限公司 芯片点胶治具构造及其点胶方法
CN113257761A (zh) * 2021-02-24 2021-08-13 北京时代民芯科技有限公司 一种倒装焊器件主动式散热结构及互联方法
US11587799B2 (en) 2019-12-02 2023-02-21 Applied Materials, Inc. Methods and apparatus for processing a substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100591181C (zh) * 2007-08-24 2010-02-17 武汉华灿光电有限公司 倒装焊发光二极管芯片的制造方法
CN102909156A (zh) * 2012-10-17 2013-02-06 日月光半导体制造股份有限公司 芯片点胶治具构造及其点胶方法
US11587799B2 (en) 2019-12-02 2023-02-21 Applied Materials, Inc. Methods and apparatus for processing a substrate
CN113257761A (zh) * 2021-02-24 2021-08-13 北京时代民芯科技有限公司 一种倒装焊器件主动式散热结构及互联方法
CN113257761B (zh) * 2021-02-24 2024-05-07 北京时代民芯科技有限公司 一种倒装焊器件主动式散热结构及互联方法

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