CN1696887A

CN1696887A - High precision A/D conversion circuit

Info

Publication number: CN1696887A
Application number: CN 200510050435
Authority: CN
Inventors: 贺惠农
Original assignee: YIHENG TECH Co Ltd HANG ZHOU
Current assignee: YIHENG TECH Co Ltd HANG ZHOU
Priority date: 2005-06-24
Filing date: 2005-06-24
Publication date: 2005-11-16

Abstract

A high accurate A / D conversion circuit connects its all signal leading out wires to FPGA programmable logic circuit. The prepared circuit has high accuracy of A / D conversion with conversion cipher of 24 position, S - N ratio of 117 dB and dynamic range of 117 dB since it applies serial output after A / D conversion is finished.

Description

A kind of high precision A/D conversion circuit

Technical field

The present invention relates to data acquisition system (DAS), be applied to a kind of high precision A/D conversion circuit of data collecting instrument, direct digital controller and audio processing equipment.

Background technology

In traditional digital format change-over circuit based on analog/digital converter, because the restriction of chip pin, volume, the conversion figure place is generally 8,10, and conversion accuracy is low, is difficult to satisfy the occasion that collection has higher requirements to data.Under some occasion, adopt the A/D conversion chip of serial output directly to link to each other, cause the digital format conversion to take the CPU processing time with CPU, and poor expandability.

Summary of the invention

The invention provides a kind of high precision A/D conversion circuit, realize high-accuracy data acquisition.

The technical solution used in the present invention is: comprise that high precision A/D conversion circuit signal extension line all is connected to the FPGA Programmable Logic Device.

Described high precision A/D conversion circuit: comprise the AK5393 chip composition that can realize 24 high-precision analog/digital conversion, outside differential analog signal connects CH1AIL+, CH1AIL-and CH2AIL+, the CH2AIL-end of AK5393 chip.

Described FPGA Programmable Logic Device comprises fpga chip XC2S50E, 20.9M and 24.576M crystal oscillator chip, and the crystal oscillator chip links to each other with the GCK end of fpga chip, for high precision analogue/change-over circuit provides many group sampling rate clocks; The CPU download interface; The serial digital bus AD1LRCK of modulus conversion chip, AD1SCLK, AD1SDATA, AD1FSYNC and AD1MCLK are connected to the FPGA Programmable Logic Device; The FPGA Programmable Logic Device is by data line DSPED[31:0], address wire DSPEA[12:2], control line DSPARE, DSPAWE, DSPCE2, DSPAOE interrupt application line DSPEXIN5_ADINT and link to each other with the digital signal processor DSP parallel bus.

The present invention combines analog/digital converter and FPGA programming technique, provides a kind of and has been applicable to the demanding digital circuit of A/D conversion accuracy.On the basis of analog/digital converter, by the support of FPGA software, this digital circuit can be converted to digital signal with simulating signal with 24 precision fast, and can different sampling rates be set according to concrete application scenario.

The present invention compares with background technology, and the beneficial effect that has is:

1. analog/digital conversion precision height is changed figure place and is reached 24;

2. adopt serial output after the analog/digital conversion, pin is few, and chip volume is little;

3. A/D conversion chip signal to noise ratio (S/N ratio) height can reach 117dB, and dynamic range is 117dB, makes the overall digital circuit have high-performance;

4.FPGA the construction cycle is short, low in energy consumption, reliability is high, by program different sampling rates can be set; As a kind of data-interface, A/D conversion chip and data bus are joined, extensibility is strong.

Description of drawings

Fig. 1 is a structured flowchart of the present invention;

Fig. 2 is the high precision A/D conversion circuit schematic diagram;

Fig. 3 is a FPGA Programmable Logic Device schematic diagram.

Embodiment

The invention will be further described below in conjunction with drawings and Examples.

As shown in Figure 1, structured flowchart of the present invention is provided by accompanying drawing 1.Comprise that high precision A/D conversion circuit 1 signal extension line all is connected to FPGA Programmable Logic Device 2.

As shown in Figure 2, high precision analogue change-over circuit: adopt AK5393 modulus conversion chip 1.Chip has two-way analog difference signal input CH1AIL+, CH1AIL-and CH2AIL+, CH2AIL-.The SMODE1 and the SMODE2 of chip connect high level, and AK5393 chip serial digital interface is set to MASTERMODE.Reset signal/ADRST, calibrating signal AD1ZCAL, Hi-pass filter enable AD1HPFE, the double speed sampling enables AD1DFS and is connected to FPGA Programmable Logic Device 2.Analog to digital conversion circuit serial digital bus AD1LRCK, AD1SCLK, AD1SDATA, AD1FSYNC and AD1MCLK, they all are connected to FPGA Programmable Logic Device 2.AK5393 chip numeral circuit part is powered by 3.3V, and artificial circuit part is by+5V power supply.

As shown in Figure 3: the FPGA Programmable Logic Device: comprise fpga chip XC2S50E, 20.9M and 24.576M crystal oscillator chip, CPU download interface.The crystal oscillator chip is that high precision analogue change-over circuit [1] provides many group sampling rate clocks.Fpga chip is finished the digital interface of AK5393 and DSP, and it finishes the conversion of serial digital form to the Parallel Digital form.FPGA Programmable Logic Device 2 is by data line DSPED[31:0], address wire DSPEA[12:2], control line DSPARE, DSPAWE, DSPCE2, DSPAOE interrupt application line DSPEXIN5_ADINT and link to each other with the DSP parallel bus.FPGA Programmable Logic Device 2 and high precision analogue change-over circuit 1 are by serial digital bus AD1LRCK, AD1SCLK, AD1SDATA, AD1FSYNC and AD1MCLK interconnection.LED light is whether to download success for the program of indicating FPGA.The mode of operation base pin selection M0 of FPGA, M1, M2 is external pull-up resistor, the configuration mode that promptly shows FPGA has adopted the configuration of driven serial ports pattern.Configurable clock generator pin DLCLK, configuration data input pin DLDATA, configuration enable pin/PROG2 link to each other with cpu chip respectively with configuration successful pin DONE2.The program of FPGA downloads among the FPGA by the CPU download interface.

Below to concrete course of work explanation of the present invention:

1, the download of FPGA program.After system powered on, the CPU download interface downloaded to the FPGA program among the FPGA.The program of the bright indication of LED light FPGA is downloaded successfully.

2, DSP initialization AK5393 chip.DSP is by FPGA, and general/ADRST draws and is the AK5393 chip to be resetted low level.After the AK5393 chip enters and resets, carry out calibration operation automatically.The AD1CAL output decision calibration of FPGA is by VCOML, VCOMR, still carries out calibration operation by simulating input.Can judge that from the AD1CAL output low level of AK5393 chip calibration operation finishes.

3, the AK5393 chip is in normal operating conditions.The two-way analog input signal enters the AK5393 chip with the differential signal form.The AK5393 chip sends to FPGA Programmable Logic Device 2 by serial digital bus AD1LRCK, AD1SCLK, AD1SDATA, AD1FSYNC and AD1MCLK with 24 position digital signals after the conversion.The FPGA program converts serial 24 bit digital to parallel 24 bit digital.By interrupt mechanism notice DSP, DSP reads 24 AD translation data by data, address bus.

The control of AK5393 chip sampling rate.20.9M and the 24.576M crystal oscillator can produce many group sampling rate clocks through FPGA program frequency division.DSP can by with the FPGA interface, control the output of that group sampling rate clock, thus control AK5393 chip sampling rate.

Claims

1, a kind of high precision A/D conversion circuit is characterized in that: comprise that high precision A/D conversion circuit (1) signal extension line all is connected to FPGA Programmable Logic Device (2).

2, a kind of high precision A/D conversion circuit according to claim 1, it is characterized in that: described high precision A/D conversion circuit (1): comprise the AK5393 chip composition that can realize 24 high-precision analog/digital conversion, outside differential analog signal connects CH1AIL+, CH1AIL-and CH2AIL+, the CH2AIL-end of AK5393 chip.

3, a kind of high precision A/D conversion circuit according to claim 1, it is characterized in that: described FPGA Programmable Logic Device (2) comprises fpga chip XC2S50E, 20.9M and 24.576M crystal oscillator chip, the crystal oscillator chip links to each other with the GCK end of fpga chip, for high precision analogue/change-over circuit (1) provides many group sampling rate clocks; The CPU download interface; The serial digital bus AD1LRCK of modulus conversion chip, AD1SCLK, AD1SDATA, AD1FSYNC and AD1MCLK are connected to FPGA Programmable Logic Device (2); FPGA Programmable Logic Device (2) is by data line DSPED[31:0], address wire DSPEA[12:2], control line DSPARE, DSPAWE, DSPCE2, DSPAOE interrupt application line DSPEXIN5_ADINT and link to each other with the digital signal processor DSP parallel bus.