CN2835954Y

CN2835954Y - Embedded signal acquisition instrument based on network

Info

Publication number: CN2835954Y
Application number: CN 200520128122
Authority: CN
Inventors: 谭延磊; 张慧慧; 杨健; 李孝辉; 王恺
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2005-10-28
Filing date: 2005-10-28
Publication date: 2006-11-08
Anticipated expiration: 2015-10-28

Abstract

The utility model belongs to the field of signal acquisition, which overcomes the defects that the traditional instruments can not collect high-frequency signals, can not complete intensive operations and have small data transmission quantity. The utility model comprises a mainboard and a signal conditioning board, wherein the signal conditioning board comprises a signal conditioning circuit and an external control circuit. The utility model is characterized in that the mainboard comprises an ARM main controller circuit, a DSP coprocessor circuit, an AD converting circuit and an FPGA circuit; the ARM main controller circuit is provided with a 10M/100M network controller, and the running of the ARM main controller circuit is provided with an operating system of a TCP/IP framework; measured signals enter the AD converting circuit through the signal conditioning circuit; a DSP starts AD conversion with the aid of an FPGA and reads the converted signals to an internal memory thereof; after finishing processing data, the DSP sends out an interrupt to an ARM which reads the data from the DSP to a memory of the ARM through the FPGA; after being framed, the data is sent to a far-end server through a network; meanwhile, the ARM receives commands sent from the far-end server, displays the commands or running states, or sends out alarm messages with the aid of the FPGA. The instrument can carry out the high-speed signal acquisition and has the advantage of strong practicability.

Description

A kind of based on network embedded signal Acquisition Instrument

Technical field

The utility model is a kind of instrument that possesses the acquired signal of functions such as data processing, Network Transmission, liquid crystal display, external control, can be applicable to the collection to the lathe signal.

Background technology

Signal sampler all has in various fields very widely to be used, and is responsible for various analog signal digitals, so that further handle.General signal sampler all has the function with upper machine communication, and communication interface is generally the RS232 interface.Fig. 1 is the structural drawing that has signal sampler both at home and abroad now, and signal sampler generally consists of the following components at present: filtering circuit, amplification (conditioning) circuit, modulus (AD) change-over circuit, primary processor, liquid crystal display circuit, communication module.Be sampled signal elder generation wave circuit after filtration, normally filter high-frequency signal, again through amplifying (conditioning) circuit, signal is adjusted to the scope that satisfies the desired level of AD interface, then under the control of primary processor (generally being single-chip microcomputer), the digital signal that A/D convertor circuit converts is read in the storer, then information such as current state or warning are shown on the liquid crystal, and the data that collect are transferred to PC by serial ports.At present, most of lathe still needs the people to operate, and is difficult in time judge the problem place when going wrong in the process.When the utilization Acquisition Instrument is gathered the signal of lathe, need it at short notice data acquisition to be got off, and data are passed to expert system by network through after the preliminary signal Processing, by expert system signal is made judgement, in time lathe is controlled.Along with the precision of lathe is more and more higher, being sampled signal frequency reaches more than the 5K, require frequency acquisition more and more higher, also need processor to finish intensive functions such as computing simultaneously, aspect communication, data quantity transmitted is more than 2.34Mbps (300k/s bytes), and traditional signal sampler just can not well have been finished task that these are complicated.

The utility model content

The purpose of this utility model is to gather high speed signal, through after the signal Processing data is sent to the webserver by network high-speed, and the instruction of reception server is simultaneously controlled external unit and corresponding the demonstration.

The technical solution of the utility model such as Fig. 2 ~ shown in Figure 6, comprise mainboard and signal regulating panel two parts, wherein signal regulating panel comprises signal conditioning circuit and external control circuit, it is characterized in that: band 10M/100M network controller in main board comprises, and ARM main controller circuit, DSP coprocessor circuit, A/D convertor circuit, the FPGA circuit of the operating system of operation band TCP/IP framework; Measured signal enters A/D convertor circuit through modulate circuit, and the DSP coprocessor circuit starts the AD conversion under the FPGA circuit is assisted, and the digital signal that AD converts is read in the storer of DSP coprocessor circuit inside; The DSP coprocessor circuit sends look-at-me for the intact back of data processing the ARM main controller circuit, the ARM main controller circuit is read data in the storer of ARM main controller circuit by the FPGA circuit from the DSP coprocessor circuit, and framing is sent to data in the far-end server by network later; The ARM main controller circuit receives the order that far-end server is sent simultaneously, display command or running status under the assistance of FPGA circuit, or send warning message.

The work information highest frequency of lathe is 6kHz, by be Qwest's sampling thheorem as can be known, guarantee that the signal that collects can distortion, must satisfy formula: f _s〉=2f _m, f wherein _sBe sample frequency, f _mFor being sampled the signal highest frequency.According to practice analysis, former state is restored by acquired signal preferably, and sample frequency should be by more than 8 times of acquired signal highest frequency, i.e. 6k * 8=48kHz.The lathe signal has signals such as electric current, vibration, acoustic emission, vibration and acoustic emission signal will be gathered the signal ability good treatment signal on x, y, the z3 direction separately, so the port number of selection AD should be more than or equal to 8 passages, the single channel sample frequency should be more than 48KHz, measure according to practice, the accuracy requirement of lathe signals collecting is more than per mille, so AD chip precision should be selected more than 12.Total sample frequency of required AD chip should be greater than 48KHz * 8=384KHz.

According to 8 channel cycle samplings, the mode of the total sample frequency 400KHz of system is estimated, does maximum number of points, i.e. 2048 points, and FFT handles, and the one-channel signal processing requirements is 2048/ (400 * 10 ³)=5.12 * 10 ^-3S, promptly about 5ms, in finish.The Wave data that every road signals collecting is 2048 produces 1024 FFT frequency spectrum data, adds and extracts about 128 points of characteristic quantity data, and per 12 bit data are (2048+1024+128) * 2=6400byte with 2 byte representations, final required data quantity transmitted.8 tunnel signals collecting to data volume be 8 * 6400=51.2Kbyte.Consider that coprocessor also will carry out AD and gather and finish communication with master controller, according to the practical experience analysis, the dominant frequency of DSP coprocessor will be chosen in more than the 80MHz.

DSP produces in 5ms and need be by the network real-time data quantity transmitted: 2 * (1024+128)=2304byte, so the transfer rate of clear data is 2304/0.005=460k/s (byte)=3680kbps in the network.In addition, system has also required to show and externally control, workload of finishing as required and practical experience, so the arm processor dominant frequency will be more than 50MHz, and interior band 10M/100M network controller, and the operating system of employing band TCP/IP framework.

The function of FPGA circuit completion logic and sequential coupling, the debugging of hardware system for convenience, the FPGA that selects for use will support embedded logic analyzer.Simultaneously because data, the address wire of ARM, DSP all will be introduced FPGA, the data line of AD also will be introduced FPGA, also to stay the interface of 30 pins for liquid crystal, so FPGA remove power supply,, the fixing good line of letter such as debugging interface at least also should have 100 IO mouths can be for system's use outward, the quantity of the pin of chip should be more than 150.

Description of drawings:

The schematic block diagram of the existing signal sampler of Fig. 1

The schematic block diagram of Fig. 2 based on network embedded signal Acquisition Instrument of the present utility model

HPI interface schematic block diagram between Fig. 3 DSP and ARM

Fig. 4 LCD interface schematic block diagram

Fig. 5 AD interface schematic block diagram

Fig. 6 network interface signal connection layout

Embodiment

In conjunction with Fig. 2～Fig. 6 the utility model is further described:

A kind of novel based on network embedded signal Acquisition Instrument comprises mainboard and signal regulating panel two parts.Signal regulating panel comprises signal conditioning circuit and external control circuit.Main board comprises ARM main controller circuit, DSP coprocessor circuit, A/D convertor circuit, FPGA circuit, display circuit, power-switching circuit.Measured signal enters A/D convertor circuit through behind the modulate circuit, and DSP starts the AD conversion under FPGA assists, and the digital signal that AD converts is read in the storer of DSP inside.DSP sends interruption to the intact back of data processing to ARM, and ARM reads data in the storer of ARM from DSP, and framing is sent to data in the far-end server by network later.The order that the far-end server of ARM reception is simultaneously sent will be ordered under the assistance of FPGA or running status is presented on the LCD, or the control alarm provides warning message.

The each several part interface mode is as follows:

1, the interface mode of AD and DSP: as shown in Figure 5, AD is inner continuous at FPGA with the relevant line of DSP, conveniently analyzes sequential with embedded logic analyzer.The data line of AD links to each other with the data line of DSP, and the AD conversion starting signal is produced by the IO district chip select line IOSTRB of DSP

2, the interface mode of DSP and ARM: the two adopts the interface mode of HPI.The HPI expansion is in the IO0 district of ARM, interface schema is as shown in Figure 3: the HPI interface data line of DSP links to each other with the most-significant byte data line of ARM, in FPGA, realize bidirectional data transfers with the bidirectional buffering interface, the read-write line of HPI, byte control line, register select line are controlled by the universal I/O port (GPIO) of ARM, and the direction control line is by the read-write line traffic control of ARM

3, network interface mode: as shown in Figure 6, the extension line of the network controller of ARM directly links to each other with corresponding data, the control line of physical chip, and the differential signal of physical chip output links to each other with the network transformation, further outputs to the RJ45 interface

4, liquid crystal interface: liquid crystal interface is expanded in the IO1 district of ARM, and liquid crystal interface is drawn by FPGA, is controlled by ARM.The data line of liquid crystal links to each other with the inferior most-significant byte data line of ARM in FPGA inside, and register select line links to each other with the address3 of ARM, and reset signal is produced by logic in the FPGA sheet.Because ARM and FPGA are the 3.3V level system, liquid crystal is the 5V level, so need connect level transferring chip in liquid crystal interface.Liquid crystal interface ARM main processor circuit as shown in Figure 4 is made up of ARM, peripheral storage (SDRAM, FLASH), house dog, serial ports, network interface, debugging interface, and all communication interfaces and peripheral control are handled by ARM.The ARM primary processor is the flush bonding processor of embedded ARM7TDMI kernel., it is outside to come stores system parameters such as server ip address, this machine IP address, the network port etc. with the IIC storer.GPIO4 judges when connecing outer button and being used for starting shooting that entering parameter is provided with pattern or normal operation mode, enters parameter during for low level pattern is set, and enters normal operation mode during for high level.The least-significant byte address wire of ARM, high 16 position datawires, chip select line, read-write control line, interrupt line are introduced among the FPGA.The most-significant byte data line is used for and the HPI interface communication of DSP, and inferior most-significant byte data line is used for and the LCD communication, and chip select line Necs0 is as the chip selection signal of the HPI of DSP, and chip select line Necs1 is as the chip selection signal of LCD.GPIO0, GPIO1 connect two test lamps, so that debug hardware.

GPIO16 connects the toggle switch control system and starts and to enter bootloader and still start kernel.GPIO17 connects toggle switch, and whether control starts watchdog circuit.Processor inside has network controller, thus outside as long as expansion a slice physical chip just can come, be easy to design 100M/10M self-adaptation Ethernet.And system uses uClinux as operating system, and uClinux operating system is very complete to network support, is driven by whole network.

, be responsible for gathering and processing signals as coprocessor with the TMS320VC54 series DSP of TI company.The outside FLASH storer of DSP is NOR FLASH, and expansion is used for storing the boot table of DSP between the 0x8000～0xFFFF of the external data space of DSP.DSP adopts the form self-starting of parallel 16 bootloader.In the process of system start-up, the dominant frequency of DSP boot is 8MHZ in the system, when program is copied into when moving in the ram in slice, revises the value of clock register at the inlet of DSP program, system clock is adjusted to 160MHZ from 8MHZ, and the final full speed running of system is at 160MHZ.The AD expansion is at the PORT0 of DSP (during startup) and PORT1 (during reading of data), DSP controls sample frequency with timer, in timer interrupt routine, press passage storage data, start the software interruption deal with data, then PORT0 operation start AD converter is begun next passage conversion.Memory circuitry is used for storing the data of reading from AD, and it is read and write by DSP and controls.16 bit data bus of DSP, HPI signal wire, least-significant byte address wire, memory chip route selection, IO district chip select line, read-write control line etc. all are incorporated among the FPGA, make things convenient for sequential debugging and logical design.

The FPGA circuit is selected the CYCLONE of altera corp family chip for use, is the very high FPGA of cost performance, and there is the above RAM of 8K bytes inside, can be used as dual port RAM or FIFO as required.Inner two phaselocked loops in addition can carry out frequency multiplication or frequency division to external crystal-controlled oscillation easily.This kind of chip is also supported embedded logic analyzer, easily the debug hardware sequential.The function of the main completion logic of FPGA realizes that DSP is to the control of AD and the ARM control to LCD.Because the read-write sequence of ARM is than very fast, and the sequential that LCD requires is relatively slow, the sequential that must mate ARM and LCD with counter or shift register in FPGA.

The AD chip is selected the chip of Linear Tech for use, and the digital signal output interface can be selected 5V or 3V interface, and is very flexible.AD converter is operated in the SCAN pattern, and promptly successively by the channel sample signal, the sample frequency of AD is by the timer control of DSP.The AD input signal is single-ended unipolar signal, and signal level range is 0～4.096V.The chip selection signal CS ground connection of AD, read-write all connects high level, starts switching signal converst and links to each other with the IOSTRB of DSP, and the coupling sequential conforms to the two sequential in FPGA.

The liquid crystal of display circuit is selected 320 * 240 lattice lcds for use, and backlight is highlighted charactron, can be used for industry and commercial various occasion.Liquid crystal interface by ARM control, is convenient to the sequential coupling by drawing among the FPGA.

The signal conditioning circuit of signal regulating panel needs signal condition to AD level range, passage 0～3 is the unipolar signal input channel, the signal input range is 0～4.096V.4～7 passages are the bipolar signal input channel, the signal input range is-10～+ 10V.One tunnel control output signal is arranged on the signal regulating panel, be used for controlling alarm, this signal is produced by ARM, improves drive current by triode and drives relay work.

Based on network embedded signal Acquisition Instrument adopts 4 veneer structures; taked the power protection measure; all put filter capacitor between the power supply of each chip and the ground; adopt magnetic bead to simulate ground and digitally to separate, reduce the interference between mimic channel and the digital circuit as far as possible, system shell is made with iron plate; stronger antijamming capability is arranged; system's dress is by a fan, and good again heat-sinking capability can be used in the industry spot.

Master controller is operated in 50MHz in the based on network embedded signal Acquisition Instrument, and coprocessor is operated in 160MHz, and the ability of deal with data strengthens greatly, and network transfer speeds reaches 10Mbps.After the data that sample deposited storer in successively, the data upload that can be at a high speed will handle object for appreciation by network interface was carried out data analysis or data and is compiled record to far-end server, and the ability of very strong collection, processing and data transmission is arranged.

The utility model is simple, convenient, practical.

Claims

1, a kind of based on network embedded signal Acquisition Instrument, comprise mainboard and signal regulating panel two parts, wherein signal regulating panel comprises signal conditioning circuit and external control circuit, it is characterized in that: band 10M/100M network controller in main board comprises, and ARM main controller circuit, DSP coprocessor circuit, A/D convertor circuit, the FPGA circuit of the operating system of operation band TCP/IP framework; Measured signal enters A/D convertor circuit through modulate circuit, and the DSP coprocessor circuit starts the AD conversion under the FPGA circuit is assisted, and the digital signal that AD converts is read in the storer of DSP coprocessor circuit inside; The DSP coprocessor circuit sends look-at-me for the intact back of data processing the ARM main controller circuit, the ARM main controller circuit is read data in the storer of ARM main controller circuit by the FPGA circuit from the DSP coprocessor circuit, and framing is sent to data in the far-end server by network later; The ARM main controller circuit receives the order that far-end server is sent simultaneously, display command or running status under the assistance of FPGA circuit, or send warning message.

2, a kind of based on network embedded signal Acquisition Instrument according to claim 1, it is characterized in that: A/D convertor circuit single channel sample frequency is more than 48KHz, and accuracy selection is more than 12; The dominant frequency of DSP coprocessor is chosen in more than the 80MHz; The arm processor dominant frequency is more than 50MHz; The quantity of the pin of FPGA is more than 150.