CN2835954Y - Embedded signal acquisition instrument based on network - Google Patents

Abstract

The utility model belongs to the field of signal acquisition, which overcomes the defects that the traditional instruments can not collect high-frequency signals, can not complete intensive operations and have small data transmission quantity. The utility model comprises a mainboard and a signal conditioning board, wherein the signal conditioning board comprises a signal conditioning circuit and an external control circuit. The utility model is characterized in that the mainboard comprises an ARM main controller circuit, a DSP coprocessor circuit, an AD converting circuit and an FPGA circuit; the ARM main controller circuit is provided with a 10M/100M network controller, and the running of the ARM main controller circuit is provided with an operating system of a TCP/IP framework; measured signals enter the AD converting circuit through the signal conditioning circuit; a DSP starts AD conversion with the aid of an FPGA and reads the converted signals to an internal memory thereof; after finishing processing data, the DSP sends out an interrupt to an ARM which reads the data from the DSP to a memory of the ARM through the FPGA; after being framed, the data is sent to a far-end server through a network; meanwhile, the ARM receives commands sent from the far-end server, displays the commands or running states, or sends out alarm messages with the aid of the FPGA. The instrument can carry out the high-speed signal acquisition and has the advantage of strong practicability.

Description

An Embedded Signal Acquisition Instrument Based on Network

technical field

The utility model is an instrument for collecting signals with the functions of data processing, network transmission, liquid crystal display, external control, etc., and can be applied to the signal collection of machine tools.

Background technique

Signal collectors are widely used in various fields and are responsible for digitizing various analog signals for further processing. Generally, the signal acquisition instrument has the function of communicating with the upper computer, and the communication interface is generally RS232 interface. Figure 1 is a structural diagram of the existing signal acquisition instrument at home and abroad. At present, the signal acquisition instrument generally consists of the following parts: filter circuit, amplification (conditioning) circuit, analog-to-digital (AD) conversion circuit, main processor, liquid crystal display circuit, communication module. The sampled signal first passes through the filter circuit, usually to filter out the high-frequency signal, and then through the amplification (conditioning) circuit to adjust the signal to the level range required by the AD interface, and then in the main processor (usually a single-chip microcomputer) Under the control, the digital signal converted by the AD conversion circuit is read into the memory, and then the current status or alarm information is displayed on the LCD, and the collected data is transmitted to the PC through the serial port. At present, most machine tools still need people to operate, and it is difficult to judge the problem in time when there is a problem in the processing process. When using the acquisition instrument to collect the signal of the machine tool, it needs to be able to collect the data in a short time, and after preliminary signal processing, the data will be transmitted to the expert system through the network, and the expert system will make a judgment on the signal and timely monitor the machine tool. Take control. As the precision of machine tools is getting higher and higher, the frequency of the sampled signal reaches more than 5K, which requires a higher and higher sampling frequency. At the same time, a processor is required to complete intensive operations and other functions. In terms of communication, the amount of transmitted data is 2.34Mbps. (300k/s bytes), the traditional signal acquisition instrument cannot complete these complex tasks very well.

Utility model content

The purpose of the utility model is to collect high-speed signals, transmit the data to the network server through the network at high speed after signal processing, and at the same time receive instructions from the server to control external devices and display accordingly.

The technical solution of the utility model is shown in Figures 2 to 6, including two parts, the main board and the signal conditioning board, wherein the signal conditioning board includes a signal conditioning circuit and an external control circuit, and is characterized in that: the main board part includes an internal 10M/100M network Controller, and run the ARM main controller circuit, DSP coprocessor circuit, AD conversion circuit, FPGA circuit of the operating system with TCP/IP framework; the measured signal enters the AD conversion circuit through the conditioning circuit, and the DSP coprocessor circuit is in the The AD conversion is started with the assistance of the FPGA circuit, and the digital signal after the AD conversion is read into the internal memory of the DSP coprocessor circuit; the DSP coprocessor circuit sends an interrupt signal to the ARM main controller circuit after the data is processed, and the ARM main controller circuit The controller circuit reads the data from the DSP coprocessor circuit to the memory of the ARM main controller circuit through the FPGA circuit, and transmits the data to the remote server through the network after framing; at the same time, the ARM main controller circuit receives the data from the remote server. The command sent, with the assistance of the FPGA circuit, displays the command or running status, or sends out an alarm message.

The highest frequency of the working condition information of the machine tool is 6kHz. According to the Nyquist sampling theorem, to ensure that the collected signal will not be distorted, the formula must be satisfied: f _s ≥ 2f _m , where f _s is the sampling frequency, f _m is the sampled The highest frequency of the signal. According to practical analysis, to restore the collected signal better, the sampling frequency should be more than 8 times the highest frequency of the collected signal, that is, 6k×8=48kHz. Machine tool signals include current, vibration, acoustic emission and other signals. The vibration and acoustic emission signals must collect signals in the directions of x, y, and z respectively to process the signals well. Therefore, the number of channels selected for AD should be greater than or equal to 8 channels. The channel sampling frequency should be above 48KHz. According to actual measurement, the accuracy of machine tool signal acquisition is required to be above 1/1000, so the accuracy of the AD chip should be above 12 bits. The total sampling frequency of the required AD chip should be greater than 48KHz×8=384KHz.

According to 8-channel cyclic sampling, the total sampling frequency of the system is 400KHz, and the maximum number of points is 2048 points. For FFT processing, the single-channel signal processing requires 2048/(400×10 ³ )=5.12×10 ^-3 s, namely About 5ms, completed within. Each signal collects 2048 points of waveform data, generates 1024 points of FFT spectrum data, and extracts about 128 points of feature data. Each 12-bit data is represented by 2 bytes, and the final amount of data to be transmitted is (2048 +1024+128)×2=6400byte. The amount of data collected by the 8-channel signal is 8×6400=51.2Kbyte. Considering that the coprocessor also needs to carry out AD acquisition and complete the communication with the main controller, according to the actual experience analysis, the main frequency of the DSP coprocessor should be selected above 80MHz.

The amount of data that DSP needs to transmit in real time through the network within 5ms is: 2×(1024+128)=2304byte, so the transmission rate of pure data in the network is 2304/0.005=460k/s (byte)=3680kbps. In addition, the system also requires display and external control. According to the workload and practical experience to be completed, the main frequency of the ARM processor should be above 50MHz, with a 10M/100M network controller inside, and an operation with a TCP/IP framework. system.

The FPGA circuit completes the logic and timing matching functions. In order to facilitate the debugging of the hardware system, the selected FPGA must support the embedded logic analyzer. At the same time, since the data and address lines of ARM and DSP must be introduced into the FPGA, the data lines of AD must also be introduced into the FPGA, and a 30-pin interface must be left for the LCD, so the fixed signal lines such as power supply, ground, and debugging interface are removed from the FPGA. There should be at least 100 IO ports available for the system, and the number of chip pins should be more than 150.

Description of drawings:

The schematic block diagram of the existing signal acquisition instrument in Fig. 1

The schematic block diagram of the network-based embedded signal acquisition instrument of Fig. 2 of the present utility model

Figure 3 Schematic block diagram of HPI interface between DSP and ARM

Figure 4 Schematic Block Diagram of Liquid Crystal Display Interface

Figure 5 AD interface block diagram

Figure 6 Network interface signal connection diagram

Detailed ways

The utility model is described further in conjunction with Fig. 2～Fig. 6:

A new network-based embedded signal acquisition instrument includes two parts: a main board and a signal conditioning board. The signal conditioning board includes a signal conditioning circuit and an external control circuit. The motherboard part includes ARM main controller circuit, DSP coprocessor circuit, AD conversion circuit, FPGA circuit, display circuit, power conversion circuit. The measured signal enters the AD conversion circuit after the conditioning circuit, and the DSP starts the AD conversion with the assistance of the FPGA, and reads the digital signal after the AD conversion into the internal memory of the DSP. After the DSP processes the data, it sends an interrupt to the ARM, and the ARM reads the data from the DSP into the memory of the ARM, and after framing, transmits the data to the remote server through the network. At the same time, ARM receives the commands sent by the remote server, and with the assistance of FPGA, displays the commands or running status on the LCD, or controls the alarm to give alarm information.

The interface of each part is as follows:

1. The interface between AD and DSP: As shown in Figure 5, the relevant connections between AD and DSP are connected inside the FPGA, which is convenient for analyzing timing with an embedded logic analyzer. The AD data line is connected to the DSP data line, and the AD conversion start signal is generated by the IO area chip selection line IOSTRB of the DSP

2. The interface mode between DSP and ARM: the interface mode of HPI is adopted between the two. The HPI extension is in the IO0 area of the ARM, and the interface diagram is shown in Figure 3: the HPI interface data line of the DSP is connected to the high 8-bit data line of the ARM, and the two-way buffer interface is used in the FPGA to realize two-way data transmission. The read-write line of the HPI, The byte control line and register selection line are controlled by ARM's general-purpose IO port (GPIO), and the direction control line is controlled by ARM's read and write lines.

3. Network interface mode: As shown in Figure 6, the lead-out lines of the ARM network controller are directly connected to the corresponding data and control lines of the physical layer chip, and the differential signal output by the physical layer chip is connected to the network transformer, and further output to the RJ45 interface

4. LCD interface: The LCD interface is extended in the IO1 area of the ARM. The LCD interface is led out by the FPGA and controlled by the ARM. The data line of the liquid crystal is connected with the second-highest 8-bit data line of the ARM inside the FPGA, the register selection line is connected with the address3 of the ARM, and the reset signal is generated by the logic in the FPGA chip. Since both ARM and FPGA are 3.3V level systems and LCD is at 5V level, a level conversion chip needs to be connected to the LCD interface. The liquid crystal interface is shown in Figure 4. The ARM main processor circuit is composed of ARM, peripheral memory (SDRAM, FLASH), watchdog, serial port, network port, and debugging interface. All communication interfaces and peripheral control are handled by ARM. The ARM main processor is an embedded processor embedded with the ARM7TDMI core. , its external IIC memory is used to store system parameters such as server IP address, local IP address, network port, etc. GPIO4 is connected to an external button to determine whether to enter the parameter setting mode or the normal operation mode when the power is turned on. When it is low, it enters the parameter setting mode, and when it is high, it enters the normal operation mode. ARM's low 8-bit address lines, high 16-bit data lines, chip select lines, read and write control lines, and interrupt lines are introduced into the FPGA. The upper 8-bit data line is used to communicate with the HPI interface of the DSP, and the second-highest 8-bit data line is used to communicate with the LCD. The chip selection line Necs0 is used as the chip selection signal of the HPI of the DSP, and the chip selection line Necs1 is used as the chip selection signal of the LCD. GPIO0 and GPIO1 are connected to two test lights for debugging hardware.

GPIO16 is connected to the DIP switch to control the system to start into the bootloader or start the kernel. GPIO17 is connected to the DIP switch to control whether to start the watchdog circuit. The processor has a network controller inside, so it only needs to expand a physical layer chip externally, and it is easy to design 100M/10M adaptive Ethernet. And the system uses uClinux as the operating system. The uClinux operating system supports the network very completely and is driven by a complete network.

TI's TMS320VC54 series DSP is used as a coprocessor to collect and process signals. The external FLASH memory of the DSP is NOR FLASH, which is expanded between 0x8000 and 0xFFFF in the external data space of the DSP, and is used to store the boot table of the DSP. DSP adopts the form of parallel 16-bit bootloader to start automatically. In the process of system startup, the main frequency of DSP boot in the system is 8MHZ. When the program is copied to the on-chip RAM to run, the value of the clock register is modified at the entry of the DSP program, and the system clock is adjusted from 8MHZ to 160MHZ. Finally run at full speed at 160MHZ. AD expansion is in PORT0 (startup) and PORT1 (reading data) of DSP, DSP uses timer to control sampling frequency, stores data by channel in timing interrupt program, starts software interrupt to process data, and then starts AD for PORT0 operation The converter starts the next channel conversion. The memory circuit is used to store the data read from AD, and its reading and writing are controlled by DSP. The 16-bit data bus of DSP, HPI signal line, low 8-bit address line, memory chip select line, IO area chip select line, read and write control line, etc. are all introduced into FPGA to facilitate timing debugging and logic design.

The FPGA circuit uses Altera's CYCLONE series chips, which are very cost-effective FPGAs. There are more than 8K bytes of RAM inside, which can be used as dual-port RAM or FIFO according to needs. There are also two phase-locked loops inside, which can easily multiply or divide the frequency of the external crystal oscillator. The chip also supports an embedded logic analyzer for easy debugging of hardware timing. FPGA mainly completes the function of logic, realizes the control of DSP to AD and the control of ARM to LCD. Because the read and write timing of ARM is relatively fast, and the timing required by LCD is relatively slow, a counter or shift register must be used in FPGA to match the timing of ARM and LCD.

The AD chip is from Linear Technology, and the digital signal output interface can choose 5V or 3V interface, which is very flexible. The AD converter works in SCAN mode, that is, the signal is sampled according to the channel in turn, and the sampling frequency of AD is controlled by the timer of DSP. The AD input signal is a single-ended unipolar signal, and the signal level range is 0-4.096V. The chip select signal CS of AD is grounded, the read and write signals are all connected to high level, the start conversion signal converst is connected to the IOSTRB of the DSP, and the matching timing in the FPGA makes the timing of the two consistent.

The liquid crystal of the display circuit adopts 320×240 dot matrix liquid crystal, and the backlight is a high-brightness digital tube, which can be used in various industrial and commercial occasions. The liquid crystal interface is drawn out from the FPGA and controlled by the ARM, which is convenient for timing matching.

The signal conditioning circuit of the signal conditioning board adjusts the signal to the level range required by AD. Channels 0 to 3 are unipolar signal input channels, and the signal input range is 0 to 4.096V. Channels 4 to 7 are bipolar signal input channels, and the signal input range is -10 to +10V. There is a control output signal on the signal conditioning board, which is used to control the alarm. This signal is generated by ARM, and the driving current is increased by the triode to drive the relay to work.

The network-based embedded signal acquisition instrument adopts a 4-layer board structure and adopts power protection measures. A filter capacitor is placed between the power supply and the ground of each chip, and the analog ground and digital ground are separated by magnetic beads to reduce the analog ground as much as possible. The interference between the circuit and the digital circuit, the system casing is made of iron plate, which has strong anti-interference ability, and the system is equipped with a fan, which has good heat dissipation ability and can be used in industrial sites.

In the network-based embedded signal acquisition instrument, the main controller works at 50MHz, and the coprocessor works at 160MHz. The ability to process data is greatly enhanced, and the network transmission speed reaches 10Mbps. After the sampled data is stored in the memory one by one, the processed data can be uploaded to the remote server through the network interface at high speed for data analysis or data collection and recording. It has strong collection, processing and data transmission capabilities.

The utility model is simple, convenient and practical.

Claims (2)

1, a kind of based on network embedded signal Acquisition Instrument, comprise mainboard and signal regulating panel two parts, wherein signal regulating panel comprises signal conditioning circuit and external control circuit, it is characterized in that: band 10M/100M network controller in main board comprises, and ARM main controller circuit, DSP coprocessor circuit, A/D convertor circuit, the FPGA circuit of the operating system of operation band TCP/IP framework; Measured signal enters A/D convertor circuit through modulate circuit, and the DSP coprocessor circuit starts the AD conversion under the FPGA circuit is assisted, and the digital signal that AD converts is read in the storer of DSP coprocessor circuit inside; The DSP coprocessor circuit sends look-at-me for the intact back of data processing the ARM main controller circuit, the ARM main controller circuit is read data in the storer of ARM main controller circuit by the FPGA circuit from the DSP coprocessor circuit, and framing is sent to data in the far-end server by network later; The ARM main controller circuit receives the order that far-end server is sent simultaneously, display command or running status under the assistance of FPGA circuit, or send warning message.

2, a kind of based on network embedded signal Acquisition Instrument according to claim 1, it is characterized in that: A/D convertor circuit single channel sample frequency is more than 48KHz, and accuracy selection is more than 12; The dominant frequency of DSP coprocessor is chosen in more than the 80MHz; The arm processor dominant frequency is more than 50MHz; The quantity of the pin of FPGA is more than 150.

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