CN101527826B - Video monitoring front-end system - Google Patents
Video monitoring front-end system Download PDFInfo
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- CN101527826B CN101527826B CN2009100820423A CN200910082042A CN101527826B CN 101527826 B CN101527826 B CN 101527826B CN 2009100820423 A CN2009100820423 A CN 2009100820423A CN 200910082042 A CN200910082042 A CN 200910082042A CN 101527826 B CN101527826 B CN 101527826B
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Abstract
The present invention provides a video monitoring front-end system which comprises the following components: a camera shooting module which is used for collecting the field video image; a DSP module which is used for real-time compressing the video image with a high speed; an ARM module which is used for realizing the control to DSP module and FPGA module; and an FPGA module which is used for realizing the data exchange between the DSP module and the ARM module. The video monitoring front-end system of the invention realizes the high-quality and high-reliability real-time video monitoring function and has the advantages of low cost, simple device structure, convenient installation, convenient use and convenient maintenance. The problems of inferior stability and complicated maintenance existing in the video monitoring front-end system based on PC machine card insertion type in prior art are overcome.
Description
Technical field
The present invention relates to field of video monitoring, in particular to a kind of video monitoring front-end system.
Background technology
The monitoring fore-end system of forming by video camera, Digital Optical Terminal, realized the digitlization transmission of video data, solved the problem that transmission range is restricted under the analog form, but owing to do not carry out video compression, the communication bandwidth that causes the monitor video image to take is huge, and is unfavorable for storage and management.
Prior art provides a kind of video monitoring front-end system based on PC (Personal Computer, PC) machine transplanting of rice cassette, has realized video compression by means of the operational capability of PC.
In realizing process of the present invention, the inventor finds that there is less stable in the video monitoring front-end system based on the PC card insert type, safeguards than complicated problems in the prior art.
Summary of the invention
The present invention aims to provide a kind of video monitoring front-end system, and there is less stable in the video monitoring front-end system that can solve in the prior art based on the PC card insert type, safeguards than complicated problems.
In an embodiment of the present invention, provide a kind of video monitoring front-end system, this system comprises: photographing module is used for the video image of collection site; DSP (Digital SignalProcessor, Digital Signal Processing) module is used for the high-speed real-time compressed video image; ARM (Advanced RISC Machines, advanced reduced instruction set computing machine) module is used for the control of realization to DSP module and FPGA (Field-Programmable Gate Array, field programmable gate array) module; The FPGA module is used to realize the exchanges data between DSP module and the ARM module.
The foregoing description utilizes the stronger computing capability of DSP module by adopting the design of DSP+ARM+FPGA, and the video image of photographing module collection is carried out the high-speed real-time compressed encoding; Utilize the ARM module to realize the initialization and the program of DSP module are downloaded, be connected with the FPGA module simultaneously, realize the control of data communication by the FPGA module; And utilize the FPGA module to realize the data communication of DSP module and ARM intermodule.Present embodiment combines above-mentioned three's advantage, thereby realized the real-time video monitoring function of high-quality, high reliability, and cost is lower, device structure is simple, be convenient to mounting, commissioning and maintenance management, overcome that there is less stable in the video monitoring front-end system based on the PC card insert type, safeguards than complicated problems in the prior art.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 shows the structure chart of video monitoring front-end system according to an embodiment of the invention;
Fig. 2 shows the structure chart of DSP module in accordance with a preferred embodiment of the present invention the video monitoring front-end system;
Fig. 3 shows the structure chart of video monitoring front-end system according to an embodiment of the invention;
Fig. 4 shows the structure chart of ARM module in the video monitoring front-end system according to an embodiment of the invention;
Fig. 5 shows the structure chart of FPGA module in the video monitoring front-end system according to an embodiment of the invention;
Fig. 6 shows the structure chart of optical fiber communication module in the video monitoring front-end system according to an embodiment of the invention;
Fig. 7 shows the structure chart of ethernet communication module in the video monitoring front-end system according to an embodiment of the invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Fig. 1 shows the structure chart of video monitoring front-end system according to an embodiment of the invention, comprising:
DSP module 20 is used for the high-speed real-time compressed video image;
ARM module 30 is used to realize the control to DSP module 20 and FPGA module 40;
FPGA module 40 is used to realize between DSP module 20 and the ARM module 30, and the exchanges data of 30 of DSP module 20 and ARM modules.
The foregoing description utilizes the computing capability of DSP module the last 20 by adopting the design of DSP+ARM+FPGA, and the video image that photographing module 10 is gathered carries out the high-speed real-time compressed encoding; Utilize ARM module 30 to realize the initialization and the program of DSP module 20 are downloaded, be connected with FPGA module 40 simultaneously, realize the control of data communication by FPGA module 40; And utilize FPGA module 40 to realize the data communication of 30 of DSP modules 20 and ARM modules.Present embodiment combines above-mentioned three's advantage, thereby realized the real-time video monitoring function of high-quality, high reliability, and cost is lower, device structure is simple, be convenient to mounting, commissioning and maintenance management, overcome that there is less stable in the video monitoring front-end system based on the PC card insert type, safeguards than complicated problems in the prior art.
Preferably, this video monitoring front-end system also comprises: audio frequency input/output module 50 is used to realize the two way audio function of video monitoring front-end system.
Audio frequency input/output module 50 can realize two-way (for video monitoring front-end system, be input or output direction) audio-frequency function: on the one hand, but the sound of audio frequency input/output module 50 collection sites, obtain audio signal, input to DSP module 20, through high-speed real-time compressed encoding and data communication, can realize monitoring to on-the-spot sound; On the other hand, the voice data that is transmitted by ARM module 30 inputs to DSP module 20, and by after its processing, can be by audio frequency input/output module 50 to the direct output sound in scene, such as sending instruction or prompting warning etc., to realize the telemanagement of Surveillance center to the scene.
Fig. 2 shows the structure chart of DSP module in accordance with a preferred embodiment of the present invention the video monitoring front-end system.With reference to figure 2, this video monitoring front-end system also comprises: optical fiber communication module 60 and/or ethernet communication module 70 are used to realize communicating by letter between Video Front-end System and optical fiber and/or Ethernet.
Optical fiber communication module 60 is by LVPECL (Low-voltage positiveemitter-coupled logic, the low pressure positive emitter coupling logic) interface is connected with FPGA module 40, ethernet communication module 70 GMII (Gigabit Medium IndependentInterface, the gigabit Media Independent Interface) is connected with FPGA module 40, to realize required MAC (Media AccessControl, medium access control) the layer protocol support of optical fiber communication module 60/ ethernet communication module 70.ARM module 30 is connected with FPGA module 40 by SMC (SerialManagement Controller, Serial Management Controller) bus interface, with realization and optical fiber communication module 60/ ethernet communication module 70 communicate by letter and to its control.
The foregoing description adopts the design of optical fiber/ethernet communication double nip, both can support fiber optic network by optical fiber communication module 60, realize safe and reliable high-property transmission, can support Ethernet, PPPoE (Point to PointProtocol over Ethernet by ethernet communication module 70 again, peer-peer protocol on the Ethernet), WLAN (WirelessLocal Area Networks, WLAN) etc. plurality of access modes realizes system layout easily and flexibly.
Preferably, this video monitoring front-end system also comprises: peripheral interface 80, can carry out the function expansion easily, and satisfy the needs that system communicates by letter with ancillary equipment.
Fig. 3 shows the structure chart of DSP module 20 in the video monitoring front-end system according to an embodiment of the invention, comprise: a DSP unit 201 and the 2nd DSP unit 202, wherein, the one DSP unit 201, comprise first dsp chip 2012 and a coupled DDR SDRAM (Double Data Rate Synchronous DynamicRandom Access Memory, ddr sdram) 2014, Video Decoder 2016, audio codec 2018; The 2nd DSP unit 202 comprises second dsp chip 2022 and the 2nd DDR SDRAM 2024 that joins with it, is used for high-speed real-time and compresses the video image that a DSP unit 201 transmits.
In the one DSP unit 201, Video Decoder 2016 is used for analog video signal is converted to digital video signal; Audio codec 2018 is used for the analog/digital conversion and the digital-to-analog conversion of audio signal; The one DDR SDRAM 2014 is used for storing digital video signal in mode frame by frame; First dsp chip 2012 is used for fast acquisition of digital video signals, and the current characters such as time place of stack on vision signal are reduced into the wide height of vision signal original 1/2, again vision signal are met the H.264 compressed encoding computing of video compression standard; First dsp chip 2012 also is used to handle digital audio and video signals simultaneously: digital audio and video signals is met the G.722 computing of audio coding standard.
In the 2nd DSP unit 202, the 2nd DDR SDRAM 2024 is used for storing digital video signal in mode frame by frame; Second dsp chip 2022 is used for digital video signal is met the H.264 high speed compressed encoding computing of video compression standard.
Below with reference to Fig. 2 and Fig. 3, describe the DSP module 20 of the video monitoring front-end system of this embodiment in detail.
The video image of photographing module 10 collection sites, and pass through CVBS (CompositeVideo Broadcast Signal, composite video broadcast singal) interface to a DSP unit 201 output analog video signals.
201 pairs of these analog video signals in the one DSP unit form following two-way output through different processing:
(1) Video Decoder 2016 is digitized as this analog video signal the high resolution digital video signal of standard BT656 form, and by VPORT (Video PORT, video interface) delivers to first dsp chip 2012, first dsp chip 2012 is stored in this digital video signal among the one DDR SDRAM 2014 in mode frame by frame, and it is carried out preliminary treatment, change the characters such as time place that the mode of picture material superposes current by pointwise on video image, and the high resolution digital video signal behind the overlaying character is delivered to second dsp chip 2022 in the 2nd DSP unit 202 by VPORT;
The high resolution digital video signal of (2) first dsp chips 2012 after with this overlaying character is stored among the DDR SDRAM 2014 in mode frame by frame, dwindle processing, according to the mode of getting any every any the wide height of this vision signal all is reduced into original 1/2, obtain corresponding low resolution digital video signal, again this low resolution digital video signal is met the H.264 video compression coding computing of video compression standard, obtain NAL (Network Abstraction Layer, network abstraction layer) unit, and pass through EMIF (External Memory Interface, external memory interface) and deliver to FPGA module 40.
H.264 be ITU-T (International Telecommunication UnionTelecommunication Standardization Sector, International Telecommunications Union's telecommunication standards group) and ISO (International Organization for Standards, International Standards Organization)/IEC (International Electro Technical Commission, International Electrotechnical Commission) JVT of Zu Chenging (Joint Video Team, joint video expert group) video compression standard of new generation of common exploitation is the highest digital video coding standard of new generation of present compression efficiency.
By adopting audio codec 2018, the one DSP unit 201 except handling vision signal, but also audio signal, and then cooperate with audio frequency input/output module 50 and can realize the two way audio function:
On the one hand, the sound of audio frequency input/output module 50 collection sites, obtain simulated audio signal, after delivering to a DSP unit 201, be translated into digital audio and video signals by wherein audio codec 2018, and by McASP (Multi Channel AudioSerial Port, the multi-channel audio serial port) delivers to first dsp chip 2012, meet the G.722 computing of audio coding standard by 2012 pairs of these digital audio and video signals of first dsp chip again, and the operation result of will encoding is delivered to FPGA module 40 by EMIF;
On the other hand, compression digital audio frequency signal in the ARM module 30 is by HPI (HostPort Interface, host interface) delivers to a DSP unit 201, after being decoded as simulated audio signal via audio codec 2018, can be by audio frequency input/output module 50 to the direct output sound in scene, such as sending instruction or prompting warning etc., to realize the telemanagement of Surveillance center to the scene.
The 2nd DSP unit 202 receives (1) road output signal of a DSP unit 201, it is the high resolution digital video signal behind the overlaying character, and be stored among the 2nd DDR SDRAM 2024 in mode frame by frame, again this signal is met the H.264 high speed compressed encoding computing of video compression standard, obtain the NAL unit, and deliver to FPGA module 40 by the EMIF interface.
A DDR SDRAM 2014 and the 2nd DDR SDRAM 2024 all adopt the K4T1G164QQ chip in this enforcement.K4T1G164QQ is that capacity is the DDRSDRAM of 1Gb, and message transmission rate adopts the Interface design of the SSTL-1.8 of 1.8V up to 800Mbps, and systematic function is higher, and low in energy consumption, can realize 256 Mbytes dynamic memories of 32 Bit data width.
Video Decoder can be realized the conversion to video signal A/D (Analog/Digital, analog/digital), and Video Decoder 2016 adopts the TVP5150 chip in the present embodiment.TVP5150 is a super low-power consumption, support NTSC (National Television SystemsCommittee, national television systems committee)/PAL (Phase Alternating Line, line-by-line inversion)/SECAM (S é quential Couleur Avec M é moire, transmit colored and storage in order, claim SEQUAM system again) etc. the high-performance Video Decoder of form, when operate as normal, its power consumption is 115mW only, and has extra small encapsulation, be applicable to portable, big in batches, high-quality and high performance video product, can receive 2 road CVBS or 1 road S-Video (Separate Video, the input of S video) signal.
Audio codec can be realized A/D, D/A (Digital/Analog, the digital-to-analog) conversion to audio signal, and present embodiment sound intermediate frequency codec 2018 adopts the TLV320aic23 chip.TLV320aic23 is the audio coding decoding chip with high integrated analog functuion, A/D converter wherein and D/A converter are realized multichannel Delta-Sigma technology by over-sampling digital interpolative filter, be applicable to the application scenario that the portable digital audio-frequency recording playback machine of MP3 (MPEG Audio Layer 3, a kind of audio compression form) for example need carry out analog input/output.
Fig. 4 shows the structure chart of ARM module 30 in the video monitoring front-end system according to an embodiment of the invention, comprise: ARM chip 302 and coupled SDRAM (Synchronous Dynamic Random Access Memory, synchronous DRAM) 304, FLASH memory 306, first Ethernet interface 308 and monitoring circuit 310.
With reference to figure 2 and Fig. 4, ARM module 30 is joined with a DSP unit 201 and the 2nd DSP unit 202 respectively by the HPI bus interface, to realize that wherein a DDRSDRAM 2014 and the 2nd DDR SDRAM 2024 carried out read-write operation, and then realize that initialization, program to a DSP unit 201 and the 2nd DSP unit 202 download, and Control on Communication.In addition, ARM module 30 is also joined by SMC bus interface and FPGA module 40, to realize and the communicating by letter and control of optical fiber communication module 60/ ethernet communication module 70.
ARM chip 302 adopts the AT91RM9200 chip in the present embodiment.AT91RM9200 is the system that makes up around ARM920T ARM Thumb processor, for low-power consumption, low cost, high performance computer wide range of application provide One Chip Solutions, abundant application Peripheral Interface is provided, to finish the seamless link of using desired chip external memory and internal storage mapping peripheral configuration, the controller that SDRAM, FLASH and static memory are arranged, and integrated many standard interfaces, comprise USB 2.0 port and the widely used 10/100 Base-T Ethernet MAC controller of network layer at full speed.
SDRAM 304 adopts the HY57V561620T chip in the present embodiment, can realize 64 Mbytes dynamic memories of 32 Bit data width.Y57V561620T is CMOS (Complementary Metal-Oxide-Semiconductor Transistor, CMOS (Complementary Metal Oxide Semiconductor)) SDRAM, all input and output operations are all finished at the rising edge of clock, data channel is the internal pipeline structure, can satisfy the requirement of high bandwidth.
First Ethernet interface 308 adopts the RTL8201 chip in the present embodiment, can realize 10/,100,000,000 adaptive ethernet communications.
Fig. 5 shows the structure chart of FPGA module 40 in the video monitoring front-end system according to an embodiment of the invention, comprising: fpga chip 402 and the 3rd coupled DDR SDRAM 404.
Referring to figs. 2 and 5, FPGA module 40 is after receiving the data that a DSP unit 201, the 2nd DSP unit 202 send by the EMIF interface, with data encapsulation is the packet that meets the IEEE802.3 communication standard, be sent to ethernet communication module 70 by gmii interface, or be sent to optical fiber communication module 60 by the LVPECL interface, realize that by optical fiber communication module 60/ ethernet communication module 70 concrete physical layer data sends.
Fpga chip 402 adopts the EP1AGX20CF780C6N chip in the present embodiment.EP1AGX20CF780C6N is based on the low-cost FPGA of transceiver, its transceiver message transmission rate is up to 3.125Gbps (Giga bits per second, mbit/), 20K logical block and 4 transceiver passages are arranged, each passage all comprises CDR (Clock/DataRecovery, clock and data recovery) and embedded serializer and deserializer circuits, support PCI-Express (Peripheral Component Interconnect-Express, the high-speed peripheral connecting interface), gigabit Ethernet, SDI (Serial digital interface, serial digital interface) and SRIO high speed serial line interfaces such as (Serial Rapid IO).
The 3rd DDR SDRAM 404 adopts the K4D551638F chip in the present embodiment, to realize 32 64 Mbytes dynamic memories than data width.K4D551638F is that capacity is the DDR SDRAM of 256Mb, its synchronizing function with data strobe is increased to the 1.1GB/s/ sheet with systematic function, the I/O operation all can be carried out in the lower edge on the clock cycle, because frequency of operation broad, but and paired pulses time and postpone to implement programming Control, so can satisfy the application scenario of high-performance memory system.
Fig. 6 shows the structure chart of optical fiber communication module 60 in the video monitoring front-end system according to an embodiment of the invention, comprising: first optic communication device 6012 and coupled first optical fiber interface 6014, second optic communication device 6022 and second optical fiber interface 6024 that joins with it.Light signal leads to first optical fiber interface 6014 by SC (Standard Connector, modular connection) tail optical fiber from first optic communication device 6012, perhaps leads to second optical fiber interface 6024 from second optic communication device 6022.
In the present embodiment, first optic communication device 6012 and second optic communication device 6022 all adopt simplex optical module, and first optical fiber interface 6014 and second optical fiber interface 6024 all adopt the HWTR-24-045213132 optical module.
Fig. 7 shows the structure chart of ethernet communication module 70 in the video monitoring front-end system according to an embodiment of the invention, comprising: ethernet communication device 702 and second Ethernet interface 704 that joins with it.
In the present embodiment, ethernet communication device 702 adopts the 88E1111 chip, can realize 10,0/1,000,000,000 adaptive 802.3 communication protocol supports, second Ethernet interface 704 adopts HTSFP-24-1111SFP (Small Form-factor Pluggable transceiver, small package pluggable transceiver) module.Ethernet communication device 702 joins by LVDS (Low-Voltage Differential Singling, the Low Voltage Differential Signal) bus and second Ethernet interface 704.
Preferably, the peripheral interface 80 in this video monitoring front-end system is RS232 interface and/or RS485 interface.
In the present embodiment, the RS232/RS485 interface chip adopts the MAX3160 chip, to realize the RS232/RS485 full-duplex communication.MAX3160 is a RS232/RS485 multi-protocols transceiver able to programme, can be set to 2Tx/2Rx RS232 interface or single channel RS485/422 transceiver by pin.This chip adopts unique low pressure reduction to send output stage and inner dual charge pump ,+3V during to+5.5V power supply power supply assurance satisfy RS-232 and RS-485 consensus standard.Receiver has fail-safe circuit; when receiver input short circuit or open circuit, be output as high level; limit Slew Rate function can reduce EMI (Electromagnetic Interference, electromagnetic interference), and reduces signal reflex under unsuitable terminal match condition.The permission message transmission rate up to 10Mbps, is assigned 1Mbps in the RS-232 pattern when forbidding limitting the Slew Rate function under the RS-485/422 pattern.With reference to figure 4, RS232/RS485 interface chip and ARM chip 302 join.
As can be seen from the above description, the above embodiments of the present invention have realized following technique effect: improved the real-time and the reliability of video monitoring front-end system, simplified hardware configuration, and supported plurality of access modes such as optical fiber/Ethernet.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation module, they can concentrate on the single computing module, perhaps be distributed on the network that a plurality of computing module forms, alternatively, they can be realized with the executable program code of computing module, thereby, they can be stored in the memory module and carry out by computing module, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a video monitoring front-end system is characterized in that, comprising:
Photographing module is used for the video image of collection site;
The DSP module, be used for high-speed real-time and compress described video image, described DSP module comprises: a DSP unit and the 2nd DSP unit, wherein, a described DSP unit comprises first dsp chip and coupled first ddr sdram, Video Decoder, audio codec; Described the 2nd DSP unit comprises second dsp chip and second ddr sdram that joins with it, is used for high-speed real-time and compresses the video image that a described DSP unit transmits;
The ARM module is used to realize the control to described DSP module and FPGA module;
Described FPGA module is used to realize the exchanges data between described DSP module and the described ARM module;
The audio frequency input/output module is used to realize the two way audio function of described video monitoring front-end system;
Wherein, a described DSP unit forms following two-way output to the different processing of analog video signal process from described photographing module:
(1) described Video Decoder is digitized as described analog video signal the high resolution digital video signal of standard BT656 form, and deliver to described first dsp chip by video interface, described first dsp chip is stored in described digital video signal in described first ddr sdram in mode frame by frame, and it is carried out preliminary treatment, by pointwise point character, and the high resolution digital video signal behind the overlaying character is delivered to second dsp chip of the 2nd DSP unit by video interface with changing time that the mode of picture material superpose current on video image;
The high resolution digital video signal of (2) first dsp chips after with overlaying character is stored in first ddr sdram in mode frame by frame, dwindle processing, according to the mode of getting any every any the wide height of this vision signal all is reduced into original 1/2, obtain corresponding low resolution digital video signal, again this low resolution digital video signal is met the H.264 video compression coding computing of video compression standard, obtain network abstraction layer unit, and deliver to the FPGA module by external memory interface;
The 2nd DSP unit receives the high resolution digital video signal behind the overlaying character of exporting on (1) road, a DSP unit, and be stored in second ddr sdram in mode frame by frame, again this signal is met the H.264 high speed compressed encoding computing of video compression standard, obtain network abstraction layer unit, and deliver to the FPGA module by external memory interface.
2. video monitoring front-end system according to claim 1 is characterized in that, also comprises:
Optical fiber communication module and/or ethernet communication module are used to realize the information exchange of described Video Front-end System and optical fiber and/or Ethernet.
3. video monitoring front-end system according to claim 1 is characterized in that, also comprises: peripheral interface.
4. video monitoring front-end system according to claim 1 is characterized in that, described ARM module comprises:
ARM chip and coupled synchronous DRAM,
FLASH memory, first Ethernet interface and monitoring circuit.
5. video monitoring front-end system according to claim 1 is characterized in that, described FPGA module comprises:
Fpga chip and the 3rd coupled ddr sdram.
6. video monitoring front-end system according to claim 2 is characterized in that, described optical fiber communication module comprises:
First optic communication device and coupled first optical fiber interface, second optic communication device and second optical fiber interface that joins with it.
7. video monitoring front-end system according to claim 2 is characterized in that, described ethernet communication module comprises:
Ethernet communication device and second Ethernet interface that joins with it.
8. video monitoring front-end system according to claim 3 is characterized in that, described peripheral interface is RS232 interface and/or RS485 interface.
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| KR20070062687A (en) * | 2005-12-13 | 2007-06-18 | 엘지이노텍 주식회사 | Method and apparatus for monitoring of using the camera module |
| CN101364346A (en) * | 2008-09-03 | 2009-02-11 | 华中科技大学 | Embedded real-time intelligent traffic monitoring system based on video stream |
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