CN106911907A - A kind of accompanying flying opto-electric tracking and measurement gondola high definition compression and storage device - Google Patents

Abstract

The invention discloses a kind of compression of accompanying flying opto-electric tracking and measurement gondola high definition and storage device, belong to aircraft photoelectric nacelle technical field of image processing.Purpose aims to provide a kind of high definition compression and storage device, for in accompanying flying opto-electric tracking and measurement gondola, H.264 full HD view data is compressed during accompanying flying, the storage such as image compression encoding and synchronous GPS information, flight attitude information is in solid-state SATA hard disc；On ground by gigabit Ethernet mouthful fast discharging after the completion of flight, recorded video is played, and be superimposed time and positional information in video.The technology included in device：H.264, Bel's filtering, Cameralink camera controls and auto-exposure control, high-definition image compress realization, SATA hard disc storage and read operation, gigabit Ethernet design.Device includes FPGA module, dsp chip, and high definition compression also includes CameraLink chipsets, buffering DPRAM, DDR II chips, H.264 SATA hard disc, codec chip, Flash chip, Ethernet chip, network transformer with storage device.

Description

A kind of accompanying flying opto-electric tracking and measurement gondola high definition compression and storage device

Technical field

Present invention relates particularly to a kind of compression of accompanying flying opto-electric tracking and measurement gondola high definition and storage device, belong to aircraft light Electric gondola technical field of image processing.

Background technology

Photoelectricity accompanying flying measurement gondola mainly by accompanying flying mode to fly to have target carry out remote tracing measurement, by earth curvature The limitation of radius, ground control station just cannot receive the image information of UAV electro-optical pod's acquisition outside certain distance, For this reason, it may be necessary to design special video storage and playback system, paper " the embedded large-capacity video storage of airborne photoelectric gondola and The design of playback system ",《Optics and photoelectric technology》6th phase in 2009,30-32 pages, there is provided a kind of video storage and playback System, its storage is reliable, and replay image is clear, meets the requirement of unmanned plane image store and playback

But, with the raising of the requirement measured remote tracing in practice, treatment, storage and unloading to view data Mode, and the aspect such as superposition synchronizing information is proposed requirement higher in video, existing storage and playback system are Through these requirements can not be met.

The content of the invention

Therefore, for the above-mentioned deficiency of prior art, the object of the invention aims to provide a kind of accompanying flying opto-electric tracking and measurement and hangs The compression of cabin high definition and storage device, for accompanying flying opto-electric tracking and measurement gondola in, to full HD image 1920 during accompanying flying H.264, × 1080P data are compressed, and the storage such as image compression encoding and synchronous GPS information, flight attitude information is in solid-state In SATA hard disc；Recorded video is played, and fold in video by gigabit Ethernet mouthful fast discharging on ground after the completion of flight Between the added-time and positional information.

The technology included in device：

H.264, Bel's filtering, Cameralink camera controls and auto-exposure control, high-definition image compress realization, SATA Hard-disc storage and read operation, gigabit Ethernet design.

Specifically, device includes FPGA module, dsp chip, the high definition compression also includes with storage device CameraLink chipsets, buffering DPRAM, DDRII chip, H.264 SATA hard disc, codec chip, Flash chip, ether Web-roll core piece, network transformer, the FPGA module connect dsp chip, CameraLink chipsets, buffering DPRAM, SATA respectively Hard disk IO drivings, H.264 codec chip, Flash chip, the dsp chip connect DDRII chips, Ethernet chip respectively, The Ethernet chip connects network transformer.

Further, the FPGA module is VC5VSX50T-1FF1136L, and the DSP is TMS320C6455GTZ.

Wherein, the CameraLink chipsets include that image-receptive communication chip DS90CR288A, image send communication Chip DS90CR287, communication control chip DS90LV047 and communication control chip DS90LV048, the CameraLink cores Piece group be used for connect camera and under pass, the camera be color high-definition video camera, the color high-definition video camera to CameraLink chipsets are input into Bel's formatted data, and the buffering DPRAM is IDT70V9289L12PRF, the DDRII cores Piece is MT47H128M16HG, and the H.264 codec chip is MB86H46 chips, and the Flash chip is K9F8G08U0M, The Ethernet chip is ET1011C, and the network transformer is TG1G-E001NY.

Further, the high definition compression also includes light with storage device every chip, and the light connects FPGA moulds every chip Block.

Wherein, the light is HCPL5231 every chip, and the light is also connected with RS422 chips MAX390ESA every chip.

Further, the high definition compression also includes the RS422 chips being connected with FPGA module with storage device： MAX3077EESA。

The beneficial effects of the present invention are：Compared to the device of prior art, the accompanying flying photoelectric tracking that the present invention is provided is surveyed The compression of amount gondola high definition and storage device, with advantages below：

(1) 1920 × 1080p@30fps, 8 bayer format picture datas of energy Real-time Collection high-definition camera output；

(2) can Real Time Compression bayer format picture data 1920 × 1080p@30fps, compression standard：H.264.

(3) high clear colorful view data after the compression of energy real-time storage, storage duration is not less than 120 minutes；

(4) (time delay is not more than 10us, and interface is Camera in real time to export the LVDS signals of bayer format-patterns link)。

(5) camera scene illumination adaptation function is realized using camera aperture and electronic shutter.

(6) possess two kinds of exposure control modes：1st, auto exposure mode；2nd, Manual exposure pattern.

(7) possess two kinds of load shedding modes：1st, electric board (memory plane) is directly changed；2nd, by reserved data interface (gigabit Ethernet) fast discharging.

(8) view data, shooting time, lens focus, target range, height, attitude can be included with document form record The data such as information (are required to time sharing segment storage image file)；On ground during replay image video, above- mentioned information is superimposed；Thing Require to be directed at all information by markers during post processing.

(9) self-checking function：Host computer self-checking command can be received, self-inspection completes for each unit status to return to host computer.

(10) image recording media uses SATA interface solid-state electronic disk, and data continue reading speed and are not less than 60MB/s.

(11) compression video frequency output code check possesses in line adjustable function, code check：2Mbps~30Mbps.

(12) earth station's application software is provided, possesses the functions such as compressed data download, video data broadcasting.

Brief description of the drawings

Fig. 1 is the system framework figure of high definition compression of the present invention and storage device.

Fig. 2 is the System Working Principle schematic diagram of high definition compression of the present invention and storage device.

Fig. 3 is ET1011C chip interface circuit figures.

Fig. 4 is HFJ11-ET1011C cut-away views.

Fig. 5 is K9F8G08U0M write operation timing diagrams.

Fig. 6 is K9F8G08U0M read operation timing diagrams.

Fig. 7 is H.264 decoder block diagram.

Fig. 8 is earth station's software flow pattern.

Fig. 9 is device reliability block diagram.

Specific embodiment

Specific embodiment of the invention is illustrated below in conjunction with the accompanying drawings：

The system framework figure of high definition compression of the invention and storage device is as shown in figure 1, input requirement is high-definition camera Machine (colour)

Resolution ratio：1920×1080P

Frame frequency：30fps

Interface：Camera Link Bel's formatted datas,

Groundwork module is as follows：

1) FPGA is VC5VSX50T-1FF1136I, and technical grade has 480 IO, the block RAM of 4752kbit, and 8164 are patrolled Collect unit.

2) DSP is TMS320C6455GTZ, technical grade, dominant frequency 1GHz, 2MB internal memory, abundant interface (DDR II, gigabit Ethernet, EMIF etc.)；

3) H.264 codec chip：The MB86H46 chips of Fuji Tsu, support video and the AC-3 such as SD, high definition Compressing and decompressing audio file；

4) MAC PHY chips：ET1011C, technical grade supports RGMII, and GMII, MII, RTBI and TBI patterns are supported 10Base-TX, 100Base-TX, and 1000Base-TX agreements；

5) network transformer：TG1G-E001NY, technical grade；

6) CameraLink chipsets：Image communicating chip DS90CR288A (reception), DS90CR287 (transmission) series, Communication control chip DS90LV047 and DS90LV048；

7) buffer：IDT70V9289L12PRF, capacity 1M bits.

8) Flash chip：K9F8G08U0M, 1G x 8Bit NAND Flash Memory；

9) DDR II chips：MT47H128M16HG, 1Gb capacity, read or write speed are more than 533MHz；

10) light is every chip：HCPL5231, army's grade；

11) RS422 chips：MAX3077EESA, maximum rate is 16Mbps, technical grade；MAX490ESA, maximum rate is 2Mbps, technical grade.

High definition compression is as shown in Figure 2 with the System Working Principle of storage device：

System flow is divided into Three models：

1) ready mode：When board is operated for the first time, DSP searches the bad block of Flash, then reads MB86H46 compressions solid Part file, is written in Flash by FPGA.

2) compact model：HD video is transmitted into FPGA by CameraLink joints；By Bel's form in FPGA It is converted into YUV4：2：0 form；High definition SMPTE274M forms (needing buffering) are encoded the data to, is transported to and is H.264 encoded core Piece MB86H46：Compressed encoding, synchronizing information, flight attitude information etc. are stored in SATA solid state hard discs by DSP, FPGA.Pressure Contracting control, the working condition of circuit board and failure are communicated by RS422 and superior system.The same data of biography CameraLink at present, Control aperture size and the time for exposure of camera.

3) network mode：Compressed encoding, synchronizing information, flight attitude information in SATA hard disc etc. is stored to pass through FPGA, DSP are sent to host computer by gigabit Ethernet.Host computer carries out data parsing, image decompressor and superimposed image word The work such as symbol.Compressed encoding control, the working condition of circuit board and failure are communicated by RS422 and superior system.

Wherein, H.264 coding chip MB86H46 needs the firmware of 800Mb, stores in Flash；During configuration MB86H46, FPGA reads firmware content.

For the convenient plug of plug and installation, J30J series connectors need to be used.

(1) CameraLink standards center tap has 26 pins, and receiving terminal selects J30J-25ZKWP7-J, associated to be J30J-25TJL, definition is as shown in table 1：

Table 1

Transmitting terminal selects J30J-25TJWP7-J, and associated is J30J-25ZKL, and definition is as shown in table 2：

Table 2

Cable is numbered	Signal name	Type	Explanation
				1	NC	NC	NC
14	GROUND	ground	Ground
				2	-X0	LVDS-OUT	CameraLink sends 0-
15	+X0	LVDS-OUT	CameraLink sends 0+
				3	-X1	LVDS-OUT	CameraLink sends 1-
16	+X1	LVDS-OUT	CameraLink sends 1+
				4	-X2	LVDS-OUT	CameraLink sends 2-
17	+X2	LVDS-OUT	CameraLink sends 2+
				5	-XCLK	LVDS-OUT	CameraLink tranmitting data registers-
18	+XCLK	LVDS-OUT	CameraLink tranmitting data registers+
				6	-X3	LVDS-OUT	CameraLink sends 3-
19	+X3	LVDS-OUT	CameraLink sends 3+
				7	+SerTC	LVDS-IN	Serial data receiving+
20	-SerTC	LVDS-IN	Serial data receiving-
				8	-SerTFG	LVDS-OUT	Serial data transmission-
21	+SerTFG	LVDS-OUT	Serial data transmission+
				9	-CC1	LVDS-IN	Self-defined input
22	+CC1	LVDS-IN	Self-defined input
				10	+CC2	LVDS-IN	Self-defined input
23	-CC2	LVDS-IN	Self-defined input
				11	NC	NC	NC
24	NC	NC	NC
				12	NC	NC	NC
25	NC	NC	NC
				13	GROUND	ground	Ground

(2) gigabit Ethernet joint has 8 pins, and from J30J-9ZKWP7-J, associated is J30J-9TJL, and definition is such as Shown in table 3：

Table 3

Cable is numbered	Signal name	Explanation
			1	MAC_RX0+	Receive 0+
2	MAC_RX0-	Receive 0-
			3	MAC_RX1+	Receive 1+
4	MAC_RX1-	Receive 1-
			5	MAC_TX0+	Send 0+
6	MAC_TX0-	Send 0-
			7	MAC_TX1+	Send 1+
8	MAC_TX1-	Send 1-
			9	NC	NC

(3) RS422 communications need three tunnels (standby all the way all the way as control camera aperture all the way as synchronous and feedback With) J30J-15ZKWP7-J is selected, associated is J30J-15TJL, and definition is as shown in table 4：

Table 4

Cable is numbered	Signal name	Explanation
			1	RS422_RX0+	First via reception+
2	RS422_RX0-	First via reception-
			3	RS422_TX0+	First via transmission+
4	RS422_TX0-	First via transmission-
			5	RS422_GND	Communicatively
6	RS422_RX1+	Reserved reception+
			7	RS422_RX1-	Reserved reception-
8	RS422_TX1+	Reserved transmission+
			9	RS422_TX1-	Reserved transmission-
10	RS422_GND	Communicatively
			11	RS422_RX2+	Camera reception+
12	RS422_RX2-	Camera reception-
			13	RS422_TX2+	Camera transmission+
14	RS422_TX2-	Camera transmission-
			15	RS422_GND	Communicatively

(4) synchronizing signal is the RS422 signals of isolation, and from J30J-9TJWP7-J, associated is J30J-9ZKL, Definition is as shown in table 5：

Table 5

Cable is numbered	Signal name	Explanation
			1	SYNC+	Synchronous+
2	SYNC-	Synchronous-
			3
4
			5	SYNC_GND	Synchronously
6	SYNC_GND	Synchronously
			7	SYNC_POWER	Synchro source (5V)
8	SYNC_POWER	Synchro source (5V)
			9

(5) standard interface of the SATA hard disc interface from SATA 7+15.

(6) power connection selects two pin PCB binding posts.

MB86H46 chips

Fujitsu successfully produces the first in the world block H.264 compressed encoding chip MB86H51, and the chip can be located in real time The dynamic image of 1920 × 1080 (60i/50i) is managed, the FCRAM of 256MB is supported, consumption rate only has 750mW.

Fujitsu is proposed MB86H45/MB86H55/MB86H46/MB86H56 again within 2009, on original MB86H51 bases It is upper to support more video modes.

The MB86H46 working frequencies for using 90nm technique productions are 186MHz, can be to 1920 × 1080 (60p/50p/ 30p/24p)、1920×1080(60i/50i)、1440×1080(60i/50i)、1280×720(60p/50p)、720×480 The difference resolution output such as (60i), 720 × 576 (50i), maximum stream bit rate 30Mbps.Audio aspect, except that can recognize Outside traditional 5.1 sound channel such as Dolby Digital, DTS, Linear PCM, MPEG-2AAC, MPEG-1Audio are also supported The Lossless Compression surround sound such as Layer2.

MB86H46 features are：

1) single encapsulation LSI chips embed a 512Mb FCRAM；

2) video：H.264/AVC High Profile Level 4.0

3) audio：Dolby Digital (AC-3) Consumer Encoder/Decoder*3, Linear PCM, MPEG- 2AAC (LC profile), MPEG-1Audio Layer 2；

4) working frequency：186MHz；

5) power supply supply：Logic voltage 1.2V, IO voltage 1.8V, 2.7V~3.6V；FCRAM：1.75V~1.95V.

Gigabit Ethernet

TMS320C6455 is a high-performance, fixed-point dsp towards high-end user, maximum operating frequency It is 1.2GHz.In piece in addition to high performance C64x+ digital signal processing cores, abundant peripheral hardware resource is also integrated with, such as For chip level interconnection RapidlO interfaces, Gigabit Ethernet controller, pci interface, DDR2 interfaces, the EMIF interfaces of 64, I2C interfaces, McBSP interfaces, UTOPIA interfaces, JTAG emulator interfaces etc..

Using the gigabit ethernet interface module EMAC/MDIO in TMS320C6455 pieces, the PHY chip outside bonding pad ET1011C and simple peripheral circuit, extend the ethernet network communication interface of system, realize the networking of system.

EMAC modules are the interfaces of the networked physics layer data transfer outside dsp processor kernel and piece, are responsible for ether netting index According to reception and transmission.It realizes the ethernet mac layer protocol function of IEEE802.3 standards；To be transmitted from upper-layer protocol stack The data come are packaged into the Ethernet data bag for meeting IEEE802.3 standards, and are separated from the Ethernet data bag for receiving Load data, there is provided be analyzed and process to upper-layer protocol stack.Additionally, EMAC modules provide MII, RMII, GMII and RGMII interfaces, can be seamlessly connected with the outer PHY chip of piece for meeting IEEE802.3 standards.MDIO modules are responsible for and EMAC Connected all PHY chips, including PHY chip is enumerated, configure and device state detection etc..

In TMS320C6455 chips, the operation such as configuration, operation of EMAC/MDIO modules is all by controlling inside it Register group is realized.Additionally, EMAC inside modules there are two blocks of buffering areas of 8K sizes, it is respectively intended to deposit to be sent and connects Receive the description information of Ethernet data bag, such as data packet length, deposit position etc..These registers and buffer area are via in piece Peripheral bus are mapped in the fixing address space of dsp system memory block.Therefore, by means of these packet description informations and piece Interior direct memory access controller, EMAC/MDIO can in the case where CPU is not interrupted direct access storage areas number According to relatively independent work.

Based on the outer PHY chip of EMAC/MDIO modules, piece in TMS320C6455 pieces：ET1011C chips and its peripheral circuit Interface design, can rapidly realize the function of data link layer and physical layer in osi model.ET1011C chips are gigabits Ethernet physical layer self adaptation transceiver, supports IEEE802.3 standards, there is provided RGMII, GMII, MII, RTBI and TBI interface, Technical grade, can be seamlessly connected with the EMAC/MDIO modules in TMS320C645, support 10/100/1000Mb/s full duplex numbers According to transmission.Interface circuit is as shown in Figure 3.

Primary interface signal includes clock, control and monitoring signals and data/address bus, is described as follows respectively：

MTCLK：Tranmitting data register.System is 2.5MHz when being operated in 10Mb/s；System is 25MHz when being operated in 100Mb/s； System is 125MHz when being operated in 1000Mb/s.

MTXD[7-0]：Send data/address bus.Only when enable signal MTXEN is effective, the data on data/address bus just have Effect.

MTXEN：Send and enable signal.

GMTCLK：Reference clock, frequency is 125MHz.

MRCLK：Receive clock.System is 2.5MHz when being operated in 10Mb/s；System is 25MHz when being operated in 100Mb/s； System is 125MHz when being operated in 1000Mb/s.

MRXD[7-0]：Receive data/address bus.Only when enable signal MRXDV is effective, the data on data/address bus just have Effect.

MRXDV：Receive and enable signal.

MDXER：Receive error signal.

MDCLK：Management clock data.What the clock signal was realized by the MDIO modules on DSP pieces.The frequency of the clock It is to be controlled by CLKDIV in MDIO control registers.

MDIO：Management data wire.PHY is configured with to PHY write-ins or in the form of reading data frame.Meet IEEE802.3 consensus standards.The data frame is by several parts such as a frame head, read-write instruction, PHY addresses, register address, data Composition.

Network transformer HFJ11-ET1011C is a network transformer of ETC companies, and internal structure is as shown in Figure 4.

Have the special feature that：

Temperature range：-40to+85℃

Isolation voltage：1,500Vrms

OCL (100KHz, 0.1Vrms, 8mA)：350uH min

CMR(0.1-100MHz)：- 40dB (representative value)

Insertion Loss(0.1-100MHz)：-1.1dB Max

Crosstalk(0.1-100MHz)：- [33-20log (F/100Mhz)] dB (representative value).

CameraLink chipsets

The interface of Camera Link standard criterions between digital camera and image pick-up card, employs unified thing Reason connector and cable definition.As long as the video camera and image card that meet Camera Link standards just can be interconnected physically. Base, tri- specifications of Medium, Full are included in Camera Link standards, but all uses unified cable and connector. Camera Link Base use 4 data channel, and Medium has used 8 data channel, and Full uses 12 data channel. The maximum data transfer rate that Camera Link standards are supported is up to 680MB/s.One is additionally provided in Camera Link standards Two-way serial communication connection.Image card and video camera can be communicated by it, and user can send by from image card Corresponding control instruction is set and changed completing the hardware parameter of video camera, facilitates user to control to take the photograph in the way of Direct Programming Camera.

The suggestion of Camera Link specifications uses the 28bit Channel Link of National Semiconductor companies Chip.Camera Link image-receptive chips use DS90CR288A, send chip DS90CR287.Difference control chip is selected DS90LV047 and DS90LV048.

DS90CR28x family chips：DS90CR287/288A principal characters are as follows：

Support that clock frequency reaches as high as 77MHz；Transmission bandwidth reaches as high as 269.5MB/S (2.125Gbps)；LVDS electricity The pressure amplitude of oscillation only has 290mV；Rising edge clock latch data；Operating voltage 3.3V；Output high level voltage is 3.3V, low level electricity It is 0.1V to press.

DS90LV047 and DS90LV048 principal characters are as follows：Special Communication Control chip in Camera Link standards, point Not Bao Kuo 4 pairs transmitting-receiving differential signals, realize asynchronous communication.

Flash is stored

K9F8G08U0M capacity is 8G, its 8192 page (page) composition, wherein every page of amount of capacity is 2048bytes.And one block (block) of every composition of page 64.The basic read/write unit of K9F8G08U0M is page, basic erasing list Position is one piece, and this read-write for indicating that one one or erasing operation are forbidden.

By 8 I/O pins of multiplexing, it can be significantly reduced number of pin, and can protect for K9F8G08U0M addressing Hold the continuity of system board level：I.e. when system need to expand capacity, only chip need to be changed.And circuit board is not required to modification.Order, ground Location, data are transmitted by this 8 I/O ports.When CE is effective, in the trailing edge of WE, the data on IO are latched to In FLASH.

In addition to enhanced structure and interface, it also has copy-back functions, i.e.,：Delay external memory storage is not needed In the case of depositing, data can be transferred to other one page by copy-back programs from one page of flash.By order Call copy-back programs.

Flash contains a number of bad block when dispatching from the factory, and bad block includes specific information.And these information be can Erasing, therefore for any one piece of flash, it is to be ensured that the position of bad block was first determined before being wiped.

K9F8G08U0M write operation timing diagrams are as shown in Figure 5：

Wherein one byte write time：Twc (min)=25ns,

The unit of FLASH read-writes is page (one page includes 2048byte), and wherein one page time (representative value) is t_prog= 200us, so the writing rate of final FLASH is 8.15MHz.

K9F8G08U0M read operation timing diagrams are as shown in Figure 6：

Wherein one byte read time：t_wc(min)=25ns,

The unit of FLASH read-writes is page (one page includes 2048byte), and wherein one page time (maximum) is t_prog= 20us, so the minimum reading rate of final FLASH is 28.9MHz.

Key technology and its principle are as follows in device：

HD video

HD video, refers to just the video standard for supporting 1080i, 720P and 1080P.The definition of video, is with level Number of scanning lines is used as metering.Present giant-screen video, typically all support 1080i and 720P, the and " overall height that some are commonly called as (Full HD) clearly ", then refer to the video for supporting 1080P outputs.Current HD video data signal, highest supports 720P.Separately Outward, while supporting the video card of HD Video, HDCP, HDMI, Dolby four indices, Full HD video cards be can be described as.

High definition resolution ratio

Common resolution ratio：720p、1080i、1080p、a1080、a720、816p

First three is the key index for identifying HD video resolution ratio.Wherein, numeral followed by i and p be respectively The abbreviation of Interlace scan (interlacing scan) and Progressive scan (progressive scan), and numeral reflection is high definition The vertical resolution of video.Refer to just 1280 × 720 progressive scans as 720p, 1080i is exactly 1920 × 1080 interlacing scans, this It is a kind of naming rule that horizontal resolution by signal source carries out breviary according to method sanctified by usage.Reach more than 720p's Resolution ratio, is the access threshold in high-definition signal source, and 720p standards are also referred to as HD standards, and 1080i/1080p is referred to as Full HD (full HD) standard.The resolution ratio of partial video is a720 and a1080, is to employ deformation technology to obtain picture higher Matter.A1080 generally comprises 1440 × 1080 and 1280 × 1,080 two kinds of specifications, and longitudinal frame has all reached the standard of 1080p, It is extending transversely during by playing, realize the definition close to Full HD.A720 typically uses 960 × 720 specification, also has It is lower to 852 × 720.And 816p is not a kind of resolution ratio of standard, it is when recoding, in order to effective Utilize, reduce capacity, dismissed upper and lower black surround using AVS softwares.Film ratio such as 1920 × 1080 resolution ratio is 1.78: 1, Actual content is then 2.35: 1 wide-screen, is then 1980 × 816 after black surround is removed.Can also be using deformation technology by laterally Pixel is reduced to 1440, finally into 1440 × 816.

High-definition media interface

High-definition media interface (HDMI) has become HDTV (HDTV) and numerous for HDTV provides many of content Standard interface between medium source equipment.And with the arriving in high definition epoch, in domestic and international line display brand, by high definition Multimedia interface (HDMI) has been applied in the middle of newest product.With the standards of HDMI 1.3 are used in new system, using richer Rich high definition video data is possibly realized realizing more lucid and more lively clearly image.HDMI specifications are included for vivid Colored deep colored enhancing function, the improvement of also many other aspects, including more preferable lip synchronization, support lossless HD audios Form, " xvYCC " expanded color gamut, and an emerging miniature connector.Deep color system will provide lively electricity more true to nature Depending on experience, 10-, 12-, the color depth (RGB or YCbCr) of 16 bits are supported, using the teaching of the invention it is possible to provide more lively coloured image, eliminate mesh The banding interference that preceding high-contrast shows.It is deep colored by providing preferably most black dull and between most brilliant white ghost (shades Of grey), the quality that enhanced contrast shows is improved, so as to produce smoother coloured image.New specification is also supported " xvYCC " color standard, so as to greatly expand the colour gamut in current HDTV standards, causes more accurately color rendering, and Any color that eye can see can be shown.

HD video is encoded

Video coding：H.264、VC-1、MPEG-2、X264.

At present, the HD video coded format being used widely on BD and HD DVD mainly have H.264, VC-1 and MPEG-2 these three, from compression ratio and to hardware performance requirements come if sorting, H.264 ＞ VC-1 ＞ MPEG-2, and image quality table Now not definitely, VC-1 is prettyr good on the whole.H.264 it is common by ITU-T (International Telecommunication Union) and ISO/IEC MPEG With exploitation, AVC is also generally referred to as.There is a kind of form for being X264 now, be in fact mutation H.264, it is provided Freely, the encoder increased income, is common in HDre and HDRip forms.Briefly, H.264 it is exactly a standard, and X264 is to hold One specific product of capable this standard.VC-1 is the coded format dominated by Microsoft, in hardware performance requirements and video Accomplish preferable balance in volume, and MPEG-2 is more ripe due to technical foundation, in the range of application in early stage high definition field Also it is very wide.

High definition encapsulation format

Encapsulation format：TS、AVI、MKV、WMV

Generally this four terms are understood as the extension name of high-definition video file by more than, but more precisely, this should be The most common four kinds of encapsulation format of HD video.In theory, the coded format and audio format of encapsulation format and video In the absence of inevitable contact.Now, TS forms have become the widest encapsulation format of web-based applications, and some are than higher-end Audiotechnica, such as DTS-HD, can only be encapsulated with the form of TS.It is that our one kind the most familiar encapsulate lattice as AVI Formula, but belong to more backward specification, to the compatible poor of emerging video coding.MKV and WMV are also relatively abundanter, but overall For or be not so good as TS forms.

High-definition digital is sampled

SMPTE 274M standards define HD video 1920x1080 numeral specifications.Wherein, 1920x1080/30/P, has Imitating size is：1920x1080, frame frequency 30Hz, progressive scan, sample frequency 74.25MHz, a line number of samples is 2200, a frame There are 1125 rows.

Bel filters

In order to obtain the photo of digital camera shooting, generally require three imageing sensors and obtain red, green and blue respectively Three primary colours information, in order to cost-effective, single-sensor imaging technique obtains visual scene using cheap instrument, i.e., only With a sensor, the image for then obtaining sensor by multi-color filtrate lens array CFA (Color Filter AlTay), Such as Bayer pattern filtering, finally by the image of Bel's form by demosaicing into full color image.This method widely should For 14 department in consumption electronic product, such as digital camera and video camera, imaging device and individual digital equipment on mobile phone are helped Reason (PDA) etc..No matter for which type of imageing sensor, CFA color filter lens array technologies are to produce coloured image One of key technology.The generation of coloured image, is based primarily upon the philosophys such as the Jim Glassman of colorimetry, by imageing sensor Photo-sensitive cell obtain the basic reference colour stimuli (primitive color light) that can mix and produce random color.Imageing sensor is generally adopted CFA structures are to be similar to cellular (U.S. is also called mosaic technology) color filter plate, and it is lower with photo-sensitive cell, sentences whereby It is RGB trichromatic any to be incorporated into the light penetrated.The most frequently used array structure is that Bel (Bayer) mould is pulled, in this array The sample frequency of structure Green is the twice of red (indigo plant) color, more conforms to human eye to colored sensitiveness.

The mode that primary colors RGB Bayer patterns are mainly characterized by interval places the filter of red, green, blue color, and green filter Quantity is the twice of red (or blue), because human eye is more sensitive than red blue dichromatism to green light wave, such quantity point With causing brightness of image seen by human eye suitable, closer to realistic colour.

Theoretically, bayer image sensor is closer to [23] with the visual characteristic of human eye；And from manufacturing process Say, the cost of Bell formwork image sensor is relatively low, technology maturation.Bayer pattern is in level, vertical, diagonally opposed (green with 2 times Color is with one times) it is down-sampled, so that brightness and aberration can be optimally separated and come in frequency domain.Certainly, object spatial frequencies increase Added-time, may cause the region of light tone spectral aliasing increases therewith.Here it is bayer image sensor be widely used it is main Reason.

The limitation due to physical arrangement is previously mentioned that, CCD color image sensors can only be gathered on a pixel The one-component of RGB color, and realized by using color filter array CFA.In order to reconstruct full color image, it is necessary to The color component value of other two kinds of loss is estimated, this method is commonly referred to color interpolation (Colo Interpolation) Method or colored demosaicing (Color Demosaicing) treatment.

H.264 technology

H.264, it is dynamic by ITU-T Video Coding Experts Groups (VCEG) and ISO/IEC while being also MPEG-4 Part X The high compression number that the joint video team (JVT, Joint Video Team) that state motion picture expert group version (MPEG) is constituted jointly is proposed Word Video Codec standard.H.264/MPEG-4AVC (H.264) it is nineteen ninety-five from after the issue of MPEG-2 video compression standards Newest, most promising video compression standard.By the standard, the compression efficiency under equal image quality is than former mark Standard improves more than 2 times, therefore, H.264 it is generally considered most influential professional standard.

H.264 it is to be set up on the basis of MPEG-4 technologies, its encoding and decoding flow mainly includes 5 parts： Interframe and infra-frame prediction (Estimation), conversion (Transform) and inverse transformation, quantization (Quantization) and inverse Change, loop filtering (Loop Filter), entropy code (Entropy Coding).

H.264 the main target of standard is：Compared with other existing video encoding standards, provided under identical bandwidth More outstanding image quality.

H.264 the key technology of standard：

A. intraframe predictive coding

When to a given macroblock coding, first can be according to the macroblock prediction of surrounding (typically according to the upper left corner Macro block, because this macro block has been encoded treatment), then predicted value is encoded with the difference of actual value, so, relative to Directly for frame coding, code check can be greatly reduced.

B. inter prediction encoding

H.264 more functions are neatly with the addition of, in addition to supporting P frames, B frames, between H.264 also supporting a kind of new stream Transmission frame --- SP frames.

(1) macroblock partition of different size and shape

(2) high-precision sub-pel motion compensation

(3) multi-frame prediction

(4) de-blocking filter

C. integer transform

In terms of conversion, the quantization error influence that Integer DCT Transform causes is simultaneously little.Additionally, Integer DCT Transform also has Operand and complexity are reduced, is conducive to the advantage transplanted to fixed DSP.

D. quantify

H.264 optional 32 kinds of different quantization steps in, this with H.263 in have 31 quantization steps much like, but H.264 in, step-length is progressive with 12.5% recombination rate, rather than a fixed constant.

E. entropy code

The final step of Video coding treatment is exactly entropy code, and two kinds of different entropy coding methods are employed in h .264： Universal variable long codes (UVLC) and text based adaptive binary arithmetic coding (CABAC).

H.264 with former international standard as H.263 with MPEG-4 compared with, maximum advantage is embodied in following four side Face：

A., each frame of video is separated into the block being made up of pixel, therefore the process of the coded treatment of frame of video can reach The rank of block.

B. using the method for spatial redundancy, some original blocks to frame of video carry out spatial prediction, conversion, optimization and entropy volume Code (Variable Length Code).

C. to the different masses of successive frame using interim storage method, so, only need to be to the part that has change in successive frame Encoded.The algorithm is completed using motion prediction and motion compensation.To some specific blocks, enter at one or more The frame of coding of having gone performs search to determine the motion vector of block, and thus in the coding and decoding below predicts main piece.

D. remaining space redundancy is used, the residual block in frame of video is encoded.For example：For source block and accordingly The difference of prediction block, again using conversion, optimization and entropy code.

H.264 maximum advantage is that have data compression ratio very high, under conditions of equal picture quality, H.264 Compression ratio be more than 2 times of MPEG-2, be 1.5~2 times of MPEG-4.For example, the size of original document if 88GB, 3.5GB is become after being compressed using MPEG-2 compression standards, and compression ratio is 25: 1, and after using H.264 compression standard compression It is changed into 879MB, from 88GB to 879MB, compression ratio H.264 reaches surprising 102: 1.It is isobaric with MPEG-2 and MPEG-4ASP Contracting technology is compared, and H.264 compress technique will greatly save download time and the data flow charging of user.Especially it is worth mentioning It is H.264 also to possess high-quality smooth image while with high compression ratio, Just because of this, by what is H.264 compressed Video data, it is less in the bandwidth wanted needed for network transmission process, also more economically.

Auto-exposure control

The size of digital cameral exposure amount, during depending on the power and stop for being irradiated to sensor devices CCD, CMOS glazed thread Between, thus we can be adjusted by adjusting aperture sensor devices receive the external world illumination, by adjust shutter speed come Control light residence time on sensor devices.And light exposure also finally determines the light and shade situation of photo, for same field Scape, then photo brightens light exposure greatly, and light exposure is small, and photo tends to dimmed.

In different environments, the characteristics of scene has different, in fact and in the absence of being completely suitable under any scene Automatic explosion method.For different applications, according to this using the characteristics of can find out relatively applicable automatic explosion method.

If digital camera suitable speed, it is known that if exposure value be exactly the function on brightness values, it is and each Individual brightness value corresponds to and corresponds only to a suitable exposure value.If preset with reference to brightness value, and be given and the ginseng The corresponding exposure value of angle value is illuminated, the exposure of digital camera can be thus controlled.This is accomplished by being set inside digital camera Put the exposure value enquiry form corresponding with reference brightness.The bright of subject is measured by the photometric system of digital camera during shooting Angle value, finds corresponding exposure value in exposure value enquiry form, controls the time for exposure to realize according to the exposure value Automatic exposure.

Conventional auto exposure system compares the luminance mean value of entire image with reference value set in advance to carry out Spectrum assignment.When main reference object is relatively low with background contrast in image, image can preferably be reappeared.But work as When main reference object and excessive background reflectance, because CCD/CMOS is moved in current most of consumer cameras and video camera products State scope is narrower, and high-brightness region produces supersaturation in image, and low brightness area seems dark, so as to cause mainly to be clapped in image Take the photograph the overexposure of object or owe to expose.The special case of such case is exactly backlight and front high light scene.In both scenes, image Mean flow rate is determined by background luminance, so the spectrum assignment based on the common average of image will cause the main reference object of image Improper exposure.

The design attainable lens aperture of hardware and time for exposure control method.

Basic principle：Entire image average gray value is maintained at 128 scopes nearby (whole tonal range is 0~255).

Preparation：The different exposure gear correspondence of the setting 32 different time for exposure, and count several size apertures pair The image averaging grey scale change amount of each gear answered.

Operation：(1) initial exposure time is set according to pre-knowledge, counts the average gray Y of a two field picture.When Y is 110 In the range of~150, the time for exposure is not adjusted.When Y is less than above range, exposure gear higher is selected according to pre-knowledge.Work as Y Higher than above range, lower exposure gear is selected.

(2) only there is under-exposure situation, count under-exposure pixel number.If under-exposure pixel number exceedes threshold value N1, The corresponding exposure gear of average gray is then improved, under-exposure situation is overcome.

(3) only there is overexposure situation, count overexposure pixel number.If overexposure pixel number exceedes threshold value N2, The corresponding exposure gear of average gray is then reduced, overexposure situation is overcome.

(4) while there is under-exposure, overexposure situation, it is narrower to reflect camera CCD/CMOS dynamic ranges, the time for exposure Choose near 128 scopes for only ensureing average gray.Image can go out that item is under-exposure, overexposure situation.

(5) when gears are exposed beyond 32 in the time for exposure, when still there is under-exposure or overexposure situation, according to statistics Information adjusts aperture size to OK range.

SATA interface is designed

Solid state hard disc (Solid State Disk) is a kind of new hard disk storage devices, with traditional magnetic recording hard disk Compare, have the advantages that data transmission rate is high, energy consumption is low, shock resistance good, market potential is huge in high-end storage application.Due to Solid state hard disc uses semiconductor storage medium, no longer contains mechanical part, and its reading and writing data speed is obviously improved.Adopt With the interface standard of Serial Advanced Technology Attachment agreement (Serial Advanced Technology Attachmet, SATA), The interface rate of solid state hard disc will be made to be substantially improved on the basis of ATA agreements.

With the lifting of message transmission rate, various the problems such as signal skew and crosstalk of Parallel ATA transmission technology, equipment The limited grade of addressability all turned into improve protocol data transmission efficiency major obstacle, therefore allow data carry out serial transmission into For one kind is selected.In in August, 2001, Seagate companies announce that Serial ATA 1.0 are marked in the conferences of IDF Fall 2001 Standard, SerialATA specifications are formally established, protocol specifies data transfer rate theoretical value 150MB/s, are much higher than Parallel ATA association View.As SATA II and SATA III consensus standards are formulated successively, its interface data transmission speed can bring up to 300MB/s very To 600MB/s.

When serial data transmission is carried out, SATA interface only has 7 stitch lines：4 differential signal lines and 3 ground wires, it Main Function be respectively data is activation and receive capabilities, ground connection, wherein two pairs of data wires, a pair of inputs, a pair of output, number It is transmitted according to using common-mode differential signal.SATA is powered and uses 15 stitch lines, and 12V, 5V power supply and ground are provided respectively.Such knot Structure can also reduce the power consumption of data transfer, improve the stability of data conventional procedure.

Serial ATA have many advantages in performance due to making data carry out serial transmission compared with Parallel ATA：Reduce The stitch quantity of SATA interface, it is easy to which space connects up；Using differential signal transmission data, effectively excluded using own physical characteristic Interference problem is transmitted between data-signal；Benefit structure is opened up using point-to-point bus, CRC data verification scheme, data transfer is used It is more quick, accurately；Advantage is had more in transmission speed, the data transmission rate of Serial ATA1.0 versions has reached 150MB/ S, it is higher than Parallel ATA maximum data transfer rate, and scalability is good, and later release protocol data transmission rate will also significantly Lifting.

The architecture of SATA protocol specification is typical hierarchical structure, and agreement is broadly divided into 4 layers：Physical layer, link layer, Transport layer and application layer.

When the command register of host side SATA interface is changed, both specification interface had obtained a new read-write operation and had referred to Order, application layer can analyze the hard disk operation order that obtains and be parsed accordingly according to agreement, and being parsed into corresponding transmission please Ask, the transmission operation of data is carried out finally according to data transfer request requirement transport layer.

After transport layer receives the data transfer operation request of application layer, just by the content of related register in SATA interface The form specified according to agreement is encapsulated as a Frame Information Structure bag FIS (Frame Information Structures), presses According to the various Data Transmission Controlling flows of agreement regulation, command frame packet and data information frame are passed into link layer successively.

Link layer is mainly responsible for the transmitting procedure of control frame.Link layer defines data frame starting primitive for each is auspicious (SOF) and data frame end primitive (EOF), recipient judges an auspicious border by distinguishing them.Link layer gives auspicious letter The upper SOF and EOF primitive of breath encapsulation, and after CRC check and data, then data to be sent are carried out into scrambler, after scrambler is finished 8b/10b codings are carried out again, are finally sent by physical layer.

After physical layer receives the data that link layer process is crossed, these data separate differential signal lines are sent, and Checked by distinctive out of band signal (OOB) in bus whether carry equipment.

SATA IP kernels

XILINX FPGA GTP realize SATA physical layers；

VHDL description can integrated logic realize SATA transport layers and link layer；

SATA Gen (1.5Gbps) rate interface hard disk；

The user interface of Cache patterns, simple control flow.

The Main Resources of the FPGA of the Virtex5LXT series required for single SATA controller are as shown in table 6：

Table 6

FPGA resource title	Resource consumption number (individual)
		Register Register	About 1400
Look-up table LUT	About 1200
		Memory BlockRAM	4
High-speed transceiver GTP	1

The Basic Design thinking of SATA IP kernels is：Complicated SATA protocol is shielded, user is allowed as read-write FPGA internal RAMs The same simply reading writing harddisk.

The physical layer of SATA protocol is connected by a pair of high-speed serial signals lines outside FPGA by GTP realizations with hard disk, GTP provides parallel interface data and a series of control and state interface inside FPGA.

Data exchange between user logic and hard disk passes through a double port memory (DPRAM) realization inside FPGA, One side ports of this block storage are read and write by SATA controller, and another side ports are read and write by user's control.The data bit width of DPRAM It it is 32, SATA controller maximum can support the DPRAM of 128KB, that is, provide 15 bit address control lines.DPRAM is by sector (512 byte) is managed for unit.

Compressed bit stream and other information

Compressed bit stream and other information are stored separately.The image of 32 is added before compressed bit stream is per frame (P frames or I frames) Number information.Synchronizing information frame frequency is faster than picture frame frequency.The picture number of current image frame is added before synchronizing information is per frame, together When add 8 synchronizing signal numbering.

When host computer reads SATA hard disc, two parts file is read respectively；Find out the compressed code of identical image numbering Stream and synchronizing information, the synchronizing information of one frame of correspondence is superimposed upon on decompressing image.

Earth station's Software for Design

H.264 how one codec of no clear stipulaties to realize, specify only the syntax of encoded video bit stream And the coding/decoding method of the bit stream, take into account the intercommunity of the flexibility and codec realized.H.264 the function of codec Block diagram such as Fig. 7 shows.

Earth station's software function includes：Network sets up contact, selected compression is received by network with synchrodata and preserve, H.264 decode and be superimposed synchrodata and show.When host computer reads SATA hard disc, two parts file is read respectively；Look for Go out the compressed bit stream and synchronizing information of identical image numbering, the synchronizing information of one frame of correspondence is superimposed upon on decompressing image.It is soft Part flow chart is as shown in Figure 8：

High definition compression set system is carried out, it is expected that crash rate ＜ 100010 of the invention by with Stress Analysis Method^-6/ h, MTBF ＞ 2000h.

The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications Should be regarded as protection scope of the present invention.

Claims (6)

1. a kind of accompanying flying opto-electric tracking and measurement gondola high definition compression and storage device, including FPGA module, dsp chip, its feature It is that the high definition compression also includes that CameraLink chipsets, buffering DPRAM, DDR II chips, SATA are hard with storage device Disk, H.264 codec chip, Flash chip, Ethernet chip, network transformer, the FPGA module connect DSP cores respectively Piece, CameraLink chipsets, buffering DPRAM, H.264 SATA hard disc IO drivings, codec chip, Flash chip, it is described Dsp chip connects DDR II chips, Ethernet chip respectively, and the Ethernet chip connects network transformer.

2. accompanying flying opto-electric tracking and measurement gondola high definition as claimed in claim 1 is compressed and storage device, it is characterised in that described FPGA module is VC5VSX50T-1FF1136I, and the DSP is TMS320C6455GTZ.

3. accompanying flying opto-electric tracking and measurement gondola high definition as claimed in claim 2 is compressed and storage device, it is characterised in that described CameraLink chipsets include that image-receptive communication chip DS90CR288A, image send communication chip DS90CR287, control Communication chip DS90LV047 and communication control chip DS90LV048, the CameraLink chipsets be used for connect camera and Under pass, the camera be color high-definition video camera, the color high-definition video camera to CameraLink chipsets be input into Bel's lattice Formula data, the buffering DPRAM is IDT70V9289L12PRF, and the DDR II chips are MT47H128M16HG, described H.264 codec chip is MB86H46 chips, and the Flash chip is K9F8G08U0M, and the Ethernet chip is ET1011C, the network transformer is TG1G-E001NY.

4. accompanying flying opto-electric tracking and measurement gondola high definition as claimed in claim 1 is compressed and storage device, it is characterised in that described High definition is compressed and also include light with storage device every chip, and the light connects FPGA module every chip.

5. accompanying flying opto-electric tracking and measurement gondola high definition as claimed in claim 4 is compressed and storage device, it is characterised in that described Light is HCPL5231 every chip, and the light is also connected with RS422 chips MAX390ESA every chip.

6. accompanying flying opto-electric tracking and measurement gondola high definition as claimed in claim 1 is compressed and storage device, it is characterised in that described High definition is compressed also includes the RS422 chips being connected with FPGA module with storage device：MAX3077EESA.