CN102215173B - Ethernet service transmitting and receiving method and device capable of dynamically configuring bandwidth - Google Patents
Ethernet service transmitting and receiving method and device capable of dynamically configuring bandwidth Download PDFInfo
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Abstract
The embodiment of the invention discloses an Ethernet service transmitting and receiving method and device capable of dynamically configuring a bandwidth, which are used for the field of information transmission; an Ethernet data frame is scrambled into a high-definition image HD-SDI signal after being encoded; the Ethernet service is enabled and decoded to seamlessly fuse two service data of a HD-SDI (High-Definition Serial Digital Interface) image signal and Ethernet data on an HD-SDI; without substantially affecting the image quality, the bandwidth is dynamically configured to transmit the Ethernet service data while the HD-SDI image signal is transmitted; meanwhile, absolute isolation is assured at two levels of the high-definition image signal and the Ethernet service data so that the mutual influence during transmission is avoided. Therefore, a large quantity of wiring resources, huge time cost and human resources cost are saved for related projects in the fields like broadcast television, security monitoring and the like.
Description
Technical field
The present invention relates to field of information transmission, relate in particular to the device of a kind of transmission of capable of dynamic configured bandwidth, the method that receives Ethernet service and transmission, reception Ethernet service.
Background technology
HD-SDI (high definition serial digital interface, High Display-Serial Digital Interface) be high-definition digital input and an output interface that is used in broadcast level, this interface is in field of broadcast televisions successful Application, also at the safety-security areas of high-definition video monitoring, adopts in a large number in a large number now.HD-SDI adopts 1.485G and two kinds of speed of 2.97G to transmit, and maximum can support the image of 1920x108060Hz to transmit without time delay.
HD-SDI high definition serial digital interface adopts coaxial cable, using bnc interface as standard interface, effective propagation path is 100 meters, is to pass through at present cable transmission high-definition image distance interface farthest, holds big lead over the digital picture interfaces such as HDMI, Displayport, DVI.
Ethernet service is the most general benchmark service of current data service communication, and major applications is all carried out the exchange of business datum by Ethernet now, as VOIP, IPTV, HTTP, E-Mail etc.If high-definition image is changed into IP signal, due to needs when transmission to data encapsulate, coding etc., cause video image to occur larger time delay, picture quality also has very large loss simultaneously.And in many instances, the HD-SDI signal of high definition and Ethernet service all will access and transmit simultaneously, if guarantee the transmission of high-quality high-definition image, just the different circuit of needs carry out the carrying of these two kinds of completely different business, has greatly wasted interconnection resource or fiber resource like this.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of method and device of transparent transmission Ethernet service of capable of dynamic configured bandwidth, comprise the method that sends the method for described Ethernet service and receive described Ethernet service and can transparent transmission described in the device of Ethernet service, can be seamlessly by high-definition image HD-SDI signal, these two kinds of business datums of Ethernet data merge, in the situation that substantially not affecting picture quality, in transmission high-definition image HD-SDI signal, dynamic-configuration bandwidth is carried out transparent transmission Ethernet service data, to in high-definition image signal and these two aspects of Ethernet service data, guarantee absolute isolation simultaneously, avoid influencing each other when transmission.
In order to reach foregoing invention object, the method for the transmission Ethernet service of a kind of capable of dynamic configured bandwidth that the embodiment of the present invention proposes is achieved through the following technical solutions:
A method for the transmission Ethernet service of capable of dynamic configured bandwidth, described method comprises:
The HD-SDI high-definition image signal of input, after equalizer carries out equilibrium treatment, enters the high speed Serdes passage of FPGA; The serdes receiver module of FPGA recovers 20bit parallel data and HD-SDI link clock according to reference clock; Described 20bit parallel data enters HD-SDI protocol detection module, detects the quality of current video standard and input signal;
The Ethernet service message of input is by Ethernet switching chip or directly by Ethernet physical port, enter FRGA, and described Ethernet switching chip is connected with described FPGA by a gigabit port;
The MAC module of described FPGA receives described Ethernet service message, carries out protocol detection and data check, and filters out after Pause frame, BPDU frame and relevant check errors frame, and the Frame of described Ethernet service message is sent into queue module;
The Frame of described Ethernet service message is carried out to serialization coding, after coding, shine upon the parallel data into HD-SDI20bit;
By the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI of port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service;
After utilizing the SAV region of shining upon the HD-SDI 20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
The Serdes passage of the 20bit data of indication bandwidth information being delivered to FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber.
In order to realize goal of the invention of the present invention, the embodiment of the present invention also provides a kind of method of reception Ethernet service of capable of dynamic configured bandwidth, and described method is to realize by following technical scheme:
A method for the reception Ethernet service of capable of dynamic configured bandwidth, described method comprises:
Serialized data enter the Serdes receiver module of FPGA after equalizer, according to reference clock, recover 20bit parallel data and HD-SDI link clock;
Described serialized data enter HD-SDI protocol detection module, described HD-SDI protocol detection module is extracted up Ethernet service enable signal and bandwidth index signal, according to described enable signal and bandwidth index signal, from 20bit parallel data, isolates high-definition image signal and Ethernet data;
Isolated high-definition image signal, delivers to the Serdes passage of FPGA by the scrambling of 20bit, the Serdes of FPGA is sending to physical link side after 20bit data serializing;
Isolated Ethernet data, enters serial decode module, obtains normal Ethernet service message, and gives exchange chip by the MAC module of FPGA, and exchange chip is then forwarded to corresponding Ethernet physical port.
In order to realize goal of the invention of the present invention, the embodiment of the present invention also provides a kind of device of transmission Ethernet service of capable of dynamic configured bandwidth, and described device is to realize by following technical scheme:
A device for the transmission Ethernet service of capable of dynamic configured bandwidth, described device comprises:
HD-SDI equalizer, for the HD-SDI high-definition image signal of input is carried out after equilibrium treatment, sends described HD-SDI high-definition image signal to the high speed Serdes passage of FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The serdes receiver module of FPGA, for recovering 20bit parallel data and HD-SDI link clock according to described reference clock;
HD-SDI protocol detection module, for detecting the quality of current video standard and input signal to described 20bit parallel data;
Ethernet switching chip, for the Ethernet service message of input is sent to FPGA, described Ethernet switching chip is connected with described FPGA by a gigabit port;
The MAC module of described FPGA, for receiving described Ethernet service message, carries out protocol detection and data check, and filters out after Pause frame, BPDU frame and relevant check errors frame, and the Frame of described Ethernet service message is sent into queue module;
Coding module, for the Frame of described Ethernet service message is carried out to serialization coding, shines upon into described HD-SDI 20bit parallel data;
Band width configuration module, for the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI by port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service, and after utilizing the SAV region of shining upon the HD-SDI 20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
Sending module, for the 20bit data of indication bandwidth information being delivered to the Serdes passage of FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber.
In order to realize goal of the invention of the present invention, the embodiment of the present invention also provides a kind of device of reception Ethernet service of capable of dynamic configured bandwidth, and described device is to realize by following technical scheme:
A device for the reception Ethernet service of capable of dynamic configured bandwidth, described device comprises:
HD-SDI equalizer, for described serialized data are carried out after equilibrium treatment, is sent to the Serdes receiver module of receiving terminal FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The Serdes receiver module of FPGA, for recovering 20bit parallel data and HD-SDI link clock according to reference clock;
HD-SDI protocol detection module, be used in the up Ethernet service enable signal of described serialized extracting data and bandwidth index signal, and from 20bit parallel data, isolate high-definition image signal and Ethernet data according to described enable signal and bandwidth index signal;
Decoder module, for isolated Ethernet data is carried out to serial decode, obtains normal Ethernet service message, and gives exchange chip by the MAC module of FPGA;
Described exchange chip, for by described Ethernet service message repeating to corresponding Ethernet physical port.
The embodiment of the present invention is by method and the device of the sending and receiving Ethernet service of described capable of dynamic configured bandwidth, realization seamlessly merges high-definition image HD-SDI signal, these two kinds of business datums of Ethernet data on high-definition digital interface HD-SDI, in the situation that substantially not affecting picture quality, in transmission high-definition image HD-SDI signal, dynamic-configuration bandwidth is carried out transparent transmission Ethernet service data, to in high-definition image signal and these two aspects of Ethernet service data, guarantee absolute isolation simultaneously, avoid influencing each other when transmission.This,, by the correlation engineering that is the fields such as radio and television, safety monitoring, saves a large amount of interconnection resources, saves huge time cost and cost of human resources.
Accompanying drawing explanation
By the description of its exemplary embodiment being carried out below in conjunction with accompanying drawing, the above-mentioned feature and advantage of the present invention will become apparent and easily understand.
Fig. 1 is the method flow diagram of the transmission Ethernet service of 1 one kinds of capable of dynamic configured bandwidths of the embodiment of the present invention;
Fig. 2 is the method flow diagram of the transmission Ethernet service of 2 one kinds of capable of dynamic configured bandwidths of the embodiment of the present invention;
Fig. 3 is embodiment of the present invention 3HD-SDI transmitting terminal system schematic;
Fig. 4 is embodiment of the present invention 3HD-SDI receiving terminal system schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 1, be the method for the transmission Ethernet service of 1 one kinds of capable of dynamic configured bandwidths of the embodiment of the present invention, described method comprises:
The HD-SDI high-definition image signal of input, after equalizer carries out equilibrium treatment, enters the high speed Serdes passage of FPGA; The serdes receiver module of FPGA recovers 20bit parallel data and HD-SDI link clock according to reference clock, and described 20bit parallel data enters HD-SDI protocol detection module, detects the quality of current video standard and input signal;
The Ethernet service message of input is by Ethernet switching chip or directly by Ethernet physical port, enter FRGA, and described Ethernet switching chip is connected with described FPGA by a gigabit port;
The MAC module of described FPGA receives described Ethernet service message, carries out protocol detection and data check, and filters out after Pause frame, BPDU frame and relevant check errors frame, and the Frame of described Ethernet service message is sent into queue module;
The Frame of described Ethernet service message is carried out to serialization coding, after coding, shine upon the parallel data into HD-SDI20bit;
By the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI of port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service;
After utilizing the SAV region of shining upon the HD-SDI 20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
The Serdes passage of the 20bit data of indication bandwidth information being delivered to FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber.
The business packet of up direction is containing high-definition image signal and Ethernet service data, and related data path and control mode are as follows:
The HD-SDI high-definition image signal of input, after equalizer carries out equilibrium treatment, enters the high speed Serdes passage of FPGA;
The clock module of FPGA provides the difference reference clock of FPGA low jitter; The serdes receiver module of FPGA recovers 20bit parallel data and HD-SDI link clock according to described difference reference clock, then high-definition image data enter HD-SDI protocol detection module, described HD-SDI protocol detection module detects the quality of current video standard and input signal, as very poor in the HD-SDI signal of current input or do not have, transmitting terminal is local with the own colour bar replacement producing;
The Ethernet service data of input are introduced into Ethernet switching chip, and described Ethernet switching chip is connected with FPGA by a gigabit port; If externally, only with an Ethernet interface, can omit exchange chip and directly enter FPGA by ethernet PHY;
The gigabit MAC of FPGA receives the message that exchange chip sends, carry out protocol detection and data check, filter out Pause frame, BPDU frame and relevant check errors frame, then described Ethernet message enters queue module, at this moment, FPGA is inner needs certain data buffer storage space, as not, needs the outside data storage of expanding as DDR etc.
Then, the Frame of Ethernet message is carried out to serialization coding, after coding, shine upon into the low 2bit of HD-SDI parallel data Y component and CBCR component, altogether 4bit.Because each pixel of HD-SDI image is comprised of 20bit, 10bit Y component, 10bit CBCR component, generally Digital Image Processing is all by 24bit 4: 4: 4RGB or 16bit 4: 2: 2YCbCr processes, be that each component channel is 8bit, data-storing and transmission are convenient in such processing, as each component channel adopts 10bit sampling precision, as long as get high 8bit, substantially do not affect the quality of image yet.Therefore, according to the characteristic of Digital Image Transmission, utilize the data bit of low 4bit to carry out transparent transmission Ethernet data, both can guarantee the quality of image, also expanded the business of Ethernet.As not with full 4bit, can also use with other bit and transmit original view data.
The bandwidth of HD-SDI transmission is 74.25M*16bit=1.485Gbps and 148.5M*16bit=2.97Gbps, and every bit can provide the upstream bandwidth of 74.25M or 148.5M, therefore, by client software, the upstream bandwidth of the configuration ethernet business of capable of dynamic.Because collocating uplink bandwidth relates to the upstream data flow of port between exchange chip and FPGA, HD-SDI is up is used for the water level thresholding of the bit number of transparent transmission Ethernet data and the data buffer storage of FPGA inside.For example, when need to be on 1.485Gbps HD-SDI the Ethernet data of transparent transmission 297Mpbs, the upstream data flow that needs to configure port between exchange chip and FPGA is 297Mpbs, the up bit number that is used for transparent transmission Ethernet data of HD-SDI is 4bit, and the water level thresholding of the data buffer storage of FPGA inside is 297Mbps.
Shone upon the later HD-SDI 20bit parallel data of Ethernet service data, behind the SAV region of data, the bit8-bit6 of line number indication section LN1 is total to 3bit as the bandwidth indication of up Ethernet.Wherein, Bit8 is used to refer to whether there is Ethernet data, and as it's not true, high-definition image is by original 20bit transfer of data.As effective in bit8, bit7-bit6 is used to refer to current bandwidth, wherein, and 00: represent 1bit bandwidth, 01 represents 2bit bandwidth, and 10 represent 3bit bandwidth, and 11 represent 4bit bandwidth.
The concrete numerical value of each bit bandwidth is as follows:
Under 1.485G HD-SDI pattern, bit bandwidth=74.25M*1bit=74.25Mpbs;
Under 2.97G HD-SDI pattern, bit bandwidth=148.5M*1bit=148.5Mpbs.
The speed of HD-SDI can draw by the locking mechanism of Serdes data clock, and the video standard that can lock as reference clock 74.25M is 1.485G; The video standard that can lock as reference clock 148.5M is 2.97G.
Because HD-SDI interface adopts serial digital interface, physical layer encodes adopts the scrambling mode of DC equilibrium, is highly susceptible to Optical Fiber Transmission, as long as add the optical module of coupling in sending and receiving end, just greatly expansion of transmission range like this, according to the performance of optical module, the longlyest transmits kilometers up to a hundred.
Insert after bandwidth information, the CRC check information of 20bit data, unification replaces to the CRC check information of 16bit, then by the scrambling of 20bit, delivers to the Serdes passage of FPGA, and FPGA Serdes is sending to physical link side after 20bit serial data jargon.
The serialization coding of the ethernet data frame relating to above can bring certain coding expense, need choose a kind of expense of encoding little, again the few mode of fpga logic resource occupation.The coded system of adoptable 8B/10B, becomes after 10B, need be mapped to dynamically 1 in 4bit.
As shown in Figure 2, the method for the reception Ethernet service of 2 one kinds of capable of dynamic configured bandwidths of the embodiment of the present invention, described method is to realize by following technical scheme:
A method for the reception Ethernet service of capable of dynamic configured bandwidth, described method comprises:
Serialized data enter the Serdes receiver module of FPGA after equalizer, according to reference clock, recover 20bit parallel data and HD-SDI link clock;
Described serialized data enter HD-SDI protocol detection module, described HD-SDI protocol detection module is extracted up Ethernet service enable signal and bandwidth index signal, according to described enable signal and bandwidth index signal, from 20bit parallel data, isolates high-definition image signal and Ethernet data;
Isolated high-definition image signal, delivers to the Serdes passage of FPGA by the scrambling of 20bit, the Serdes of FPGA is sending to physical link side after 20bit data serializing;
Isolated Ethernet data, enters serial decode module, obtains normal Ethernet service message, and gives exchange chip by the MAC module of FPGA, and exchange chip is then forwarded to corresponding Ethernet physical port.
Receiving terminal is connected with transmitting terminal by coaxial cable or optical fiber, the data of serial are sent into the Serdes module of FPGA after equalizer, according to reference clock, recover 20bit parallel data and HD-SDI link clock, then data enter HD-SDI protocol detection module, HD-SDI protocol detection is taked binary channels 16bit pattern, be each passage 8bit, the SAV/EAV synchronization character 3FF of original 10bit changes the FF of 8bit into, extract up Ethernet service enable signal and bandwidth index signal simultaneously, add up data accuracy rate and the video standard of up HD-SDI circuit.According to these indications, from 20bit parallel data, isolate high-definition image signal and ethernet signal.
Isolated high-definition image signal is as figure place deficiency 20bit, from the high-order displacement of trend, low level mends 0, so enter HD-SDI protocol channel, recalculate the CRC check information of 20bit, then by the scrambling of 20bit, deliver to the Serdes passage of FPGA, FPGA Serdes, sending to physical link side after 20bit serial data jargon, has so just reached the object that transmits high-definition image.
Isolated 1-4bit Ethernet data, enter serial decode module, by 8B/10B, decode and obtain normal Ethernet service message, then by the MAC module of FPGA, give exchange chip, exchange chip is then forwarded to corresponding physical port, has so just reached the object that transmits Ethernet service up direction data.
Because Ethernet service is two-way, and the data of down direction only comprise Ethernet service data, and therefore, related data path and control mode are as follows:
The descending Ethernet message that receiving terminal Ethernet data interface side receives, be introduced into exchange chip, the Frame that exchange chip down forwards needs by the port being connected with FPGA is sent into the MAC module of FPGA, the gigabit MAC module of FPGA receives the message that exchange chip sends, carry out protocol detection and data check, filter out Pause frame, BPDU frame and relevant check errors frame, then Frame enters queue module, therefore, the inner data buffer storage space that need to be certain of FPGA, as not, need the outside data storage of expanding as DDR etc.
Then, Frame is carried out to serialization coding, the coded system of adoptable 8B/10B.If physical link side is coaxial cable, need Digital Modulation to Mid Frequency, up high-frequency data is not produced and disturbed, downstream rate can reach 500Mbps like this;
If physical link side is optical fiber, 10B data are sent into FPGA Serdes module, serial send into optical module, the up-downgoing of optical module adopts different wavelength, upstream rate is 1.485Gpbs or 2.97Gpbs, descending can be symmetrical be 1.485Gps or 2.97Gps, descending also can be asymmetric, adopt and up different speed, to reduce the cost of optical module.
Descending optical module speed reaches 1.25Gpbs, just can reach the linear speed of descending 1Gbps.As the descending reason because of physical link side does not reach the words of linear speed, just answer the water level thresholding of the data buffer storage of port speed that configuration ethernet exchange chip is connected with FPGA and FPGA inside, the upstream data flow that configures port between exchange chip and FPGA is 500Mpbs, and the water level thresholding of the data buffer storage of FPGA inside is 297Mbps.
Transmitting terminal is connected with receiving terminal by coaxial cable or optical fiber, if coaxial cable signal enters filtration module, filters high frequency and low frequency part, then enters decoder module and recovers normal Ethernet message;
If fiber-optic signal, the data of serial are sent into the Serdes module of FPGA after equalizer, enter 8B/10B decoder module after unstringing, and recover normal Ethernet message.The Ethernet message recovering is given exchange chip by the MAC module of FPGA, and exchange chip is then forwarded to corresponding physical port, has so just reached the object that transmits Ethernet downlink data.
As shown in Figures 3 and 4, under concrete implementation condition, the method that the embodiment of the present invention 3 realizes transparent transmission Ethernet service on HD-SDI interface can be by transmitting terminal, receiving terminal, and physical transmission medium completes.
Transmitting terminal is a kind of independently interconnecting device, and the transmission direction by high-definition image, may be defined as upstream plant.Business interface input side has two kinds of interfaces: the input of standard bnc interface and standard ethernet RJ45 interface, and wherein, Ethernet interface can be single channel or multichannel, 10/100/1000M mode adaptive; Ethernet interface can be also the optical fiber interface of GBIC or SFP standard.Business interface outlet side only has an interface, and by physical link pattern, coaxial cable, is the bnc interface of standard in this way; Optical fiber, is SFP optical fiber interface in this way.
The hardware of transmitting terminal forms can be as follows: HD-SDI equalizer, HD-SDI driver, the FPGA with high speed Serdes, Ethernet switching chip, 1.5G/3G optical module (when adopting Optical Fiber Transmission), filtration module, power module, clock module.
Receiving terminal is a kind of independently interconnecting device, and the transmission direction by high-definition image, may be defined as downstream plant.Business interface input side only has an interface, and by physical link pattern, coaxial cable, is the bnc interface of standard in this way; Optical fiber, is SFP optical fiber interface in this way.Business outlet side is two kinds of interfaces: standard bnc interface output and standard ethernet RJ45 interface, Ethernet interface can single channel to multichannel, 10/100/1000M mode adaptive, Ethernet interface can be also the optical fiber interface of GBIC or SFP standard.
The hardware of receiving terminal is constructed as follows: HD-SDI equalizer, HD-SDI driver, the FPGA with high speed Serdes, Ethernet switching chip, 1.5G/3G optical module (when adopting Optical Fiber Transmission), filtration module, power module, clock module.
The data path of transmitting terminal and receiving terminal is symmetrical, and input/output interface is also symmetrical.
Transmitting terminal and receiving terminal connect together by physical transmission medium, and physical transmission medium can be 100M coaxial cable, also can monomode fiber, and fiber lengths can determine by optical module separately, maximumly supports kilometers up to a hundred.
Because Ethernet is two-way communication, that just needs receiving terminal that descending Ethernet data is passed to transmitting terminal by physical link, coaxial cable transmission in this way, downlink Ethernet data need to and be modulated to Mid Frequency through coding, avoid interference the HD-SDI signal of up high frequency.If optical fiber transmits, just need two-way optical module, up employing HD-SDI agreement, descending employing SGMII agreement, can, with symmetrical optical module, also can select more inexpensive asymmetrical optical module.
The function of transmitting terminal is mainly seamless, dynamically up Ethernet data is encapsulated in HD-SDI signal, and downlink data receiving, decoding and being packaged into standard ethernet message outwards sends.Client software can be enabled Ethernet transparent transmission function, collocating uplink bandwidth, statistics and detection HD-SDI signal and video standard, be added up each ethernet port data message by network management path.
The function of receiving terminal is mainly isolated high-definition image data and Ethernet data automatically from the HD-SDI signal of access, and high-definition image data transmit to other equipment by HD-SDI interface, and Ethernet data forwards outside it by exchange chip.Downlink Ethernet data are encapsulated and encoded, by physical link, send to transmitting terminal.Video standard, up ethernet traffic in the HD-SDI signal of reception be added up and be detected to client software can by webmaster, adds up each ethernet port data message.
In order to realize goal of the invention of the present invention, the embodiment of the present invention 3 also provides a kind of device of transmission Ethernet service of capable of dynamic configured bandwidth, and described device is to realize by following technical scheme:
A device for the transmission Ethernet service of capable of dynamic configured bandwidth, described device comprises:
HD-SDI equalizer, for the HD-SDI high-definition image signal of input is carried out after equilibrium treatment, sends described HD-SDI high-definition image signal to the high speed Serdes passage of FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The serdes receiver module of FPGA, for recovering 20bit parallel data and HD-SDI link clock according to described reference clock;
HD-SDI protocol detection module, for detecting the quality of current video standard and input signal to described 20bit parallel data;
Ethernet switching chip, for the Ethernet service message of input is sent to FPGA, described Ethernet switching chip is connected with described FPGA by a gigabit port;
The MAC module of described FPGA, for receiving described Ethernet service message, carries out protocol detection and data check, and filters out after Pause frame, BPDU frame and relevant check errors frame, and the Frame of described Ethernet service message is sent into queue module;
Coding module, for the Frame of described Ethernet service message is carried out to serialization coding, shines upon into described HD-SDI 20bit parallel data;
Band width configuration module, for the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI by port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service, and after utilizing the SAV region of shining upon the HD-SDI 20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
Sending module, for the 20bit data of indication bandwidth information being delivered to the Serdes passage of FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber;
In order to realize goal of the invention of the present invention, the embodiment of the present invention 4 also provides a kind of device of reception Ethernet service of capable of dynamic configured bandwidth, and described device is to realize by following technical scheme:
A device for the reception Ethernet service of capable of dynamic configured bandwidth, described device comprises:
HD-SDI equalizer, for described serialized data are carried out after equilibrium treatment, is sent to the Serdes receiver module of receiving terminal FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The Serdes receiver module of FPGA, for recovering 20bit parallel data and HD-SDI link clock according to reference clock;
HD-SDI protocol detection module, be used in the up Ethernet service enable signal of described serialized extracting data and bandwidth index signal, and from 20bit parallel data, isolate high-definition image signal and Ethernet data according to described enable signal and bandwidth index signal;
Decoder module, for isolated Ethernet data is carried out to serial decode, obtains normal Ethernet service message, and gives exchange chip by the MAC module of FPGA;
Described exchange chip, for by described Ethernet service message repeating to corresponding Ethernet physical port.
The embodiment of the present invention is by method and the device of the sending and receiving Ethernet service of described capable of dynamic configured bandwidth, realization seamlessly merges high-definition image HD-SDI signal, these two kinds of business datums of Ethernet data on high-definition digital interface HD-SDI, in the situation that substantially not affecting picture quality, in transmission high-definition image HD-SDI signal, dynamic-configuration bandwidth is carried out transparent transmission Ethernet service data, to in high-definition image signal and these two aspects of Ethernet service data, guarantee absolute isolation simultaneously, avoid influencing each other when transmission.This,, by the correlation engineering that is the fields such as radio and television, safety monitoring, saves a large amount of interconnection resources, saves huge time cost and cost of human resources.
One of ordinary skill in the art of the present invention are appreciated that; the above embodiment of the present invention is only one of the preferred embodiments of the present invention; for length restriction; here can not all execution modes of particularize; any enforcement that can embody the claims in the present invention technical scheme, all in protection scope of the present invention.
It should be noted that; above content is in conjunction with concrete execution mode further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; under above-mentioned guidance of the present invention; those skilled in the art can carry out various improvement and distortion on the basis of above-described embodiment, and these improvement or distortion drop in protection scope of the present invention.
Claims (9)
1. a method for the transmission Ethernet service of capable of dynamic configured bandwidth, is characterized in that, described method comprises:
HD-SDI high-definition image signal to input carries out equilibrium treatment and recovers 20bit parallel data according to difference reference clock, and detects the quality of current video standard and input signal;
The Ethernet service message of input is by Ethernet switching chip or directly by Ethernet physical port, enter FPGA, and described Ethernet switching chip is connected with described FPGA by a gigabit port;
Receive described Ethernet service message, carry out protocol detection and data check, and filter out after Pause frame, BPDU frame and relevant check errors frame, the Frame of described Ethernet service message is sent into queue module;
The Frame of described Ethernet service message is carried out to serialization coding, after coding, shine upon the parallel data into HD-SDI20bit;
By the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI of port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service;
After utilizing the SAV region of shining upon the HD-SDI20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
The Serdes passage of the 20bit data of indication bandwidth information being delivered to FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber.
2. method according to claim 1, is characterized in that, described the Frame of described Ethernet service message is carried out to serialization coding, shines upon into HD-SDI20bit parallel data and specifically comprise after coding:
The Frame of described Ethernet service message is carried out to serialization coding, after coding, shine upon into the low 2bit of HD-SDI parallel data Y component and CBCR component.
3. method according to claim 2, is characterized in that, describedly Frame is carried out to serialization coding specifically comprises:
Adopt the coded system of 8B/10B to carry out serialization coding to described Frame.
4. a method for the reception Ethernet service of capable of dynamic configured bandwidth, is characterized in that, described method comprises:
Serialized data enter the Serdes receiver module of FPGA after equalizer, according to reference clock, recover 20bit parallel data and HD-SDI link clock;
Described serialized data enter HD-SDI protocol detection module, described HD-SDI protocol detection module is extracted up Ethernet service enable signal and bandwidth index signal, according to described enable signal and bandwidth index signal, from 20bit parallel data, isolates high-definition image signal and Ethernet data;
Isolated high-definition image signal, delivers to the Serdes passage of FPGA by the scrambling of 20bit, the Serdes passage of FPGA will be sent to physical link side after 20bit data serializing;
Isolated Ethernet data, enters serial decode module, obtains normal up Ethernet service message, and sends to exchange chip by the MAC module of FPGA, and exchange chip is by the extremely corresponding Ethernet physical port of described up Ethernet service message repeating.
5. method according to claim 4, is characterized in that, described method also comprises:
Receiving terminal Ethernet data interface side carries out the forwarding of downlink Ethernet service message after receiving up Ethernet message.
6. a device for the transmission Ethernet service of capable of dynamic configured bandwidth, is characterized in that, described device comprises:
HD-SDI equalizer, for the HD-SDI high-definition image signal of input is carried out after equilibrium treatment, sends described HD-SDI high-definition image signal to the high speed Serdes passage of FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The serdes receiver module of FPGA, for recovering HD-SDI20bit parallel data and HD-SDI link clock according to described reference clock;
HD-SDI protocol detection module, for detecting the quality of current video standard and input signal to described 20bit parallel data;
Ethernet switching chip, for the Ethernet service message of input is sent to FPGA, described Ethernet switching chip is connected with described FPGA by a gigabit port;
The MAC module of described FPGA, for receiving described Ethernet service message, carries out protocol detection and data check, and filters out after Pause frame, BPDU frame and relevant check errors frame, and the Frame of described Ethernet service message is sent into queue module;
Coding module, for the Frame of described Ethernet service message is carried out to serialization coding, shines upon into described HD-SDI20bit parallel data;
Band width configuration module, for the up water level thresholding that is used for the bit number of transparent transmission Ethernet service data and the data buffer storage of FPGA inside of upstream data flow, HD-SDI by port between configuration exchange chip and FPGA, configure the upstream bandwidth of described Ethernet service, and after utilizing the SAV region of shining upon the HD-SDI20bit parallel data after Ethernet message data frame, line number indicates section to indicate the bandwidth information of up Ethernet service;
Sending module, for the 20bit data of indication bandwidth information being delivered to the Serdes passage of FPGA, the Serdes passage of FPGA will be sent to physical link side after described data serializing, and described physical link comprises coaxial cable or optical fiber.
7. device according to claim 6, is characterized in that, described coding module carries out serialization coding to the Frame of described Ethernet service message, shines upon into the low 2bit of HD-SDI parallel data Y component and CBCR component after coding.
8. device according to claim 7, is characterized in that, described coding module adopts the coded system of 8B/10B to carry out serialization coding to described Frame.
9. a device for the reception Ethernet service of capable of dynamic configured bandwidth, described device comprises:
HD-SDI equalizer, for serialized data are carried out after equilibrium treatment, is sent to the Serdes receiver module of receiving terminal FPGA;
Clock module, for providing the difference reference clock of FPGA low jitter;
The Serdes receiver module of FPGA, for recovering 20bit parallel data and HD-SDI link clock according to reference clock;
HD-SDI protocol detection module, be used in the up Ethernet service enable signal of described serialized extracting data and bandwidth index signal, and from 20bit parallel data, isolate high-definition image signal and Ethernet data according to described enable signal and bandwidth index signal;
Decoder module, for isolated Ethernet data is carried out to serial decode, obtains normal Ethernet service message, and gives exchange chip by the MAC module of FPGA;
Described exchange chip, for by described Ethernet service message repeating to corresponding Ethernet physical port.
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| US20220321840A1 (en) * | 2021-03-30 | 2022-10-06 | Shenzhen Antu Autonomous Driving Technologies Ltd. | Method for transmitting high bandwidth camera data through serdes links |
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| CN104780333A (en) * | 2014-12-03 | 2015-07-15 | 中国航天科工集团第三研究院第八三五七研究所 | High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) |
| CN105611225B (en) * | 2015-10-09 | 2019-04-23 | 杭州中威电子股份有限公司 | Real-time Transmission device and transmission method when SDI multistage is reset |
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