CN1695242A - 通过表面改进提高半导体器件的温度/湿度/偏压性能的方法和结构 - Google Patents

通过表面改进提高半导体器件的温度/湿度/偏压性能的方法和结构 Download PDF

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CN1695242A
CN1695242A CNA028298098A CN02829809A CN1695242A CN 1695242 A CN1695242 A CN 1695242A CN A028298098 A CNA028298098 A CN A028298098A CN 02829809 A CN02829809 A CN 02829809A CN 1695242 A CN1695242 A CN 1695242A
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chip
integrated circuit
dielectric substance
silazane
siloxanes
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CN100390970C (zh
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约翰·A·菲茨西蒙斯
斯蒂芬·M·盖茨
迈克尔·W·莱恩
埃里克·G·利尼格
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International Business Machines Corp
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Abstract

公开了一种修复半导体芯片如高速半导体微处理器、专用集成电路(ASIC)、及其他高速集成电路器件上的引线键合损伤的方法，特别使用低k电介质材料的器件。该方法包括使用反应液体的表面改进。在优选实施例中，该方法包括将含硅液体试剂前体如TEOS涂敷到芯片的表面，并允许液体试剂与湿气反应以形成固体电介质栓塞或薄膜(50)，以产生阻止湿气进入的阻挡层，由此提高这种半导体器件的温度/湿度/偏压(THB)性能。

Description

通过表面改进提高半导体器件的温度/湿度/偏压 性能的方法和结构
技术领域
本发明总体上涉及高速半导体微处理器、专用集成电路(ASIC)及其他高速集成电路器件的制造。更具体，本发明涉及通过使用反应液体的表面改进提高这种半导体器件的温度/湿度/偏压(THB)性能的方法，尤其涉及使用低k电介质材料的器件。
背景技术
超大规模集成(VLSI)或特大规模集成(ULSI)电路中的金属互连一般由包含金属布线的构图层的互连结构构成。典型的集成电路(IC)器件包含三至十五层金属布线。随着特征尺寸减小和器件面积密度增加，互连层的数目应该增加。
优选选择这些互连结构的材料和布局，以使信号传播延迟最小化，因此使整个电路速度最大化。互连结构内信号传播延迟的指示是每个金属布线层的RC时间常数，其中R是布线的电阻，C是选择的信号线(即，导体)和多层互连结构中的围绕导体之间的有效电容。通过降低布线材料的电阻可以减小RC时间常数。因此铜是用于IC互连的优选材料，因为其相对低的电阻。通过使用具有较低介电常数(k)的电介质材料也可以减小RC时间常数。
通过使用低k电介质材料作为用于高速微处理器、专用集成电路(ASIC)和相关的集成电路器件的后端线(BEOL)互连的层间电介质(ILD)获得许多性能优点。在高级的互连结构中，ILD优选是低k聚合物热固性材料如SiLKTM(可以从Dow Chemical Company获得的芳香烃热固性聚合物)。其他优选的低k电介质材料包括碳掺杂的二氧化硅(亦称碳氧化硅或SiCOH电介质)；掺氟的氧化硅(亦称氟硅酸玻璃，或FSG)；旋涂玻璃；硅倍半氧烷，包括氢化硅倍半氧烷(HSQ)，甲基硅倍半氧烷(MSQ)和HSQ和MSQ的混合物或共聚物；以及任意含硅低k电介质。
当选择有机热固性聚合物时有几个制造优点。有机热固性聚合物的主要优点是较低的介电常数(一般约2.65)，在外加应力下较低的裂纹速率和刻蚀(RIE)选择率。在外加应力下和潮湿空气中玻璃电介质材料如SiCOH或碳掺杂的氧化物易于裂纹，而有机热固性聚合物不会裂纹。而且，在用来在每个通孔的底部开口帽盖的RIE化学方法中碳基热固性聚合物不被刻蚀，而在该刻蚀步骤中硅基SiCOH被刻蚀。换句话说，碳基热固性聚合物显示出高刻蚀选择率，而硅基SiCOH显示出低选择率。最终，有机热固性聚合物材料被旋涂，而一般使用等离子体增强化学气相淀积(PECVD)工具涂敷玻璃。旋涂工具与PECVD工具相比具有更低的财产成本。
但是，一个缺点是有机聚合物或低k CVD电介质的低模量，当完成的IC芯片通过引线键合(或焊接)方法电连接到IC固定器时可能导致在钝化层中形成缺陷或裂口。例如，在键合垫附近的钝化层中可能形成裂纹。这种裂纹一般具有1000埃至5000埃的宽度，几微米的深度，以及1微米至100微米的长度。同样在芯片的接线端绝缘体水平面常常出现裂纹。这些裂纹具有许多原因：最显著的是由封装之前完成的芯片的粗暴操作和在管芯引线键合工序过程中可能导致的损伤所引起的裂纹。钝化层的层离也是潜在的问题。
尽管在使用常规无机电介质材料的现有器件中可能已经存在这些微裂纹，但是那些器件中的集成性质使这些缺陷对产品可靠性的有害影响最小化。对于无机氧化物，由于低k电介质的出现和它们固有的较差机械性能，观察到芯片的接线端绝缘体水平面处的灵敏度和微裂纹的数量增加。
在包括低k电介质材料的器件中，常常利用无机氧化层构建作为潮气阻挡层的芯片的接线端绝缘体水平面。但是，由于低k电介质集成的独特机械结构，与所有层间电介质使用氧化物的器件相比，这些接线端无机氧化物更容易被损伤。此外，随着器件研磨规则继续减小，即使没有过渡到低k电介质，但是如果在最终封装和包封之前他们未修复，这些微裂纹和层离可能成为器件性能下降的重要来源。
在密封芯片的接线端绝缘体水平面中的这些裂纹中，后引线键合封装和包封工序是无效的。由于在芯片的接线端绝缘体水平面缺乏密封或修复这些裂纹，在温度和湿度应力测试过程中观察到半导体芯片电气性能中的电性能下降。例如，美国专利号5,689,089公开了使用用于包封的硅酮基聚合物。但是，观察到这种聚合物对湿气入侵不能单独提供有效的阻挡。
在钝化层和金属键合垫中使用新材料的更加复杂方案已被提出。例如，由The U.S.Army Manufacturing Technology(Man Tech)Program赞助的用于PEM保护的Wafer Applied Seal(WASPP)是高成本多层方法。旋涂材料(如氢化硅倍半氧烷，HSQ)和PECVD涂敷材料(碳化硅)用于钝化。此外，两个金属层(金加钛)添加到键合垫。但是，非常规材料的使用和附加金属层显著地增加制造工艺的成本。
因此，业界仍然需要一种提高半导体器件的温度/湿度/偏压性能的低成本方法。
发明内容
因此本发明要解决的技术问题是提供一种用于修复或密封由于电连接如引线键合的半导体芯片上的损伤的方法，更具体地提供一种使用不引入非常规材料或附加金属层的低成本方法来提高半导体芯片的温度/湿度/偏压性能的方法。
在一个方面，本发明旨在一种集成电路芯片，包括集成电路芯片的顶表面处的第一电介质材料；连接到集成电路芯片的顶表面的电连接；以及集成电路芯片的顶表面顶上的第二电介质材料层，其中第二电介质材料是含硅的保形密封剂。
在另一方面，本发明旨在一种用于包封集成电路芯片的方法，该方法包括以下步骤：将电连接连接到集成电路芯片的顶表面，其中顶表面由第一电介质材料组成；在集成电路芯片的顶表面顶上淀积第二材料，其中第二材料包括含硅的保形密封剂前体；以及处理淀积的第二材料，以引起前体的反应来形成第二电介质材料。
附图说明
发明的特点相信是新颖的以及在附加权利要求中详细阐述发明的元件性能。附图仅仅用于说明性目的且不按比例绘制。此外，在图中相同数字表示相同部件。但是，通过结合附图参考随后的详细描述，可以很好的理解作为操作的构成和方法的发明本身，其中：
图1A和1B图示了半导体芯片上的键合垫的平面图，具有连接到键合垫的引线键合和邻近引线键合的微裂纹；
图2A和2B图示了半导体芯片上的键合垫的剖面图，具有连接到键合垫的引线键合和邻近引线键合的微裂纹；以及
图3A和3B图示了图2A和2B的键合垫的剖面图，具有本发明的表面改进。
具体实施方式
现在参考附图详细描述本发明。在图中，示出了结构的各个方面且以简单的方式示意地表示，以更清楚地描述和说明发明。例如，该图没有按比例。此外，结构的各个方面的垂直截面被图示为矩形形状。但是，所属领域的技术人员将理解，对于实际结构，这些方面将很可能引入更多的锥形特征。而且，该发明不局限于任意特定形状的结构。
在一个方面，本发明是修复和密封由于引线键合或其他电连接在典型的损伤中发现的微裂纹和层离的方法。损伤部分可以是例如在芯片载体或内插器上安装的集成电路芯片，其中芯片包含损伤，该损伤包括芯片的钝化层内的微裂纹、裂缝、层离等。
图1A和1B图示了半导体芯片上的典型键合垫的平面图，具有连接到键合垫的引线键合。键合垫10一般由铝形成，但是可以由任意适当的导电材料形成。电介质材料30围绕键合垫10。引线键合20在其端部22处连接到键合垫10。在图1A和1B中，示出了引线键合20的端部22偏心地连接到键合垫10。当引线键合偏心地连接到键合垫时，在铝键合垫10中和围绕电介质材料30可能出现微裂纹40。观察到微裂纹具有约20微米的长度。
图2A和2B图示了半导体芯片上的典型键合垫的剖面图，具有连接到键合垫的引线键合。在导体12上形成键合垫10，键合垫10一般是铝，导体12一般是铜。导体12被电介质材料31围绕，电介质材料31可以是任意适当的电介质材料，如聚合的低k电介质材料。电介质31一般覆有一个或多个电介质层，如二氧化硅(SiO2)层32和氮化硅(SiN)层33。在图2A中，示出在帽盖层32和33上形成的键合垫10，以及在键合垫10和帽盖层33上淀积的两个附加帽盖层34，35。帽盖层34和35可以与帽盖层32和33相同或不同于帽盖层32和33。例如，帽盖层34可以是SiO2，以及帽盖层35可以是SiN。在最后的帽盖层之上，可以淀积保护材料层36，如光敏聚酰亚胺材料。示出了引线键合20在其端部22连接到键合垫10。也示出了微裂纹40延伸穿过铝键合进入帽盖层。注意即使当键合垫10上引线键合20位于中心时也可能发生这种微裂纹。在任意帽盖层32、33、34和35之间或底下也可以产生层离(未示出)。
图2B示出了替代键合垫结构，其中键合垫10形成在帽盖层32-35之上，以及在键合垫10的垂直侧面上淀积保护材料36。即使用这种聚酰亚胺保护材料36覆盖铝键合垫10，也观察到微裂纹40延伸穿过保护材料36、键合垫10并进入下面的电介质材料31-35。此外，在任意帽盖层32-35之间或底下也可能发生层离(未示出)。
使用本发明的方法可以修复或密封这种微裂纹，该方法包括在键合操作之后和后键合封装和包封工序之前涂敷反应液体试剂到损伤部分。图3A和3B图示了图2A和2B的键合垫结构，具有在损伤的半导体芯片上涂敷的反应液体试剂层50。液体试剂填充并浸湿芯片上的损坏区域，如微裂纹40。
液体试剂可以包括下列反应材料的一种或多种：烷氧基硅烷、硅氧烷、硅氮烷、环氧硅氧烷(包括烷氧基-环氧硅氧烷)、环氧硅氮烷、尿素-硅氮烷、碳硅氮烷、尿素-硅氧烷、碳硅氧烷、及其他类似的反应材料，包括这些化合物，如TEOS(正硅酸乙酯、四乙基正硅酸酯)、HMDS(六甲基二硅氮烷)、TMCTS(四甲基环四硅氧烷)以及3MC3S(三甲基环三硅氧烷)。或者，液体试剂可以包括无机聚合物，包括聚硅氮烷、聚脲硅氮烷、聚碳硅氮烷、聚硅氧烷、聚脲硅氧烷、聚碳硅氧烷及相关的含硅聚合物。这些聚合物可以具有低分子量和/或可以用溶剂稀释，以减小粘滞度。
优选，在暴露于湿气时，液体试剂与水起反应，形成固体电介质材料。例如，TEOS可以涂敷到损伤部分，以密封在芯片的接线端绝缘体水平面处的微裂纹。TEOS与湿气起反应，以形成阻挡湿气进入的TEOS氧化物。特别优选液体试剂与已经存在于损伤区域中的湿气污染物起反应，以脱水或束缚这些湿气，以便它对作为电子器件的半导体芯片的性能没有害处。
或者，液体试剂可以与第二引发剂起反应，以将半导体衬底和本身键合以密封损伤区域防止湿气入侵。一般，第二引发剂取决于使用的二元系统类型。对于湿气激活的系统，有机酸类或乙醇可以增强化学反应。一般的有机酸类包括醋酸、甲酸和丙酸。一般的乙醇包括甲醇、乙醇和异丙醇。水在乙醇中的溶解，如甲醇中25％w/w水，可以改善乙醇或水单独时的性能，因为乙醇降低粘滞度和改进水的润湿作用，同时硅氧烷和硅氮烷与乙醇相比一般更易于与水反应。此外，较低分子量的有机引发剂是优选的，因为他们一般更活跃和具有更低的粘滞度。
对于二元系统如环氧硅烷、环氧硅氧烷和环氧硅氮烷，可以使用氧化剂，如二甲苯或己烷中含过氧化物(如过氧化苯甲酰)的溶液。或者，醚如二乙醚或四氢呋喃(THF)中的过氧化物溶液可以用作二元引发剂。过氧化物溶液也可以用于湿气激活的二元系统。由于这些过氧化物溶液可能是不稳定的，优选使用之前他们小量混合。
当较高分子量碳氢化合物溶剂如矿物油作为用于过氧化物溶液的溶剂时会更稳定，这种溶剂的较高粘滞度是主要的缺点。某些矿物油可以被添加到有机过氧化物的己烷或二甲苯溶液，如过氧化苯甲酰(benzyl peroxide)，以降低闪点(flashpoint)，但是较低粘滞度的溶液是最优选的。
其他氧化引发剂如臭氧不被排除以及在某些情况下臭氧引发可能是优选的，例如当通过臭氧使冶金和封装抵抗退化时。
液体试剂应该是活性的、低粘度、含硅液体前体。来自下列组的材料在芯片的接线端绝缘体水平面处进行微裂纹的密封和修复是有效的：烷氧基硅烷、硅氧烷、硅氮烷、环氧硅氧烷(包括烷氧基环氧硅氧烷)、环氧硅氮烷、尿素-硅氮烷、碳硅氮烷、尿素-硅氧烷、碳硅氧烷、TEOS(正硅酸乙酯、四乙基正硅酸酯)、HMDS(六甲基二硅氮烷)、TMCTS(四甲基环四硅氧烷)以及3MC3S(三甲基环三硅氧烷)、聚硅氮烷、聚脲硅氮烷、聚碳硅氮烷、聚硅氧烷、聚脲硅氧烷、聚碳硅氧烷、相关的含硅聚合物及其他类似的材料。
液体试剂应该具有低粘滞度，以便流体将进入并填充细微裂纹或裂隙，以及试剂也应该很好的浸润导体和电介质的接线端绝缘体结构，以避免待修复的缺陷区域的桥接或未涂敷。液体试剂应该能与这些结构形成化学键，以及应该能反应形成栓塞或薄膜，产生阻止湿气进入的阻挡层。
液体试剂，例如烷氧基硅烷或其他的反应硅氧烷或硅氮烷应该足量地涂敷到芯片，以填充所有损伤区域。液体试剂可以仅仅涂敷到芯片的损伤区域，或可以横跨芯片的整个表面涂敷，如图3A和3B所示，以包封半导体衬底，提供抵抗湿气进入的额外阻挡层。
反应试剂例如如上所述的试剂是特别优选的，因为在这些材料的反应和固化过程中它们不产生不合需要的副产品，例如强矿物酸类或腐蚀的盐。因为这些材料是绝缘体或电介质材料并因此不降低芯片封装互连的性能，从而如上所述的试剂也是优选的。
尽管图1和2图示了连接到芯片的引线键合，但是在工业中通常使用焊球阵列以形成连接到完成的芯片的高速输入/输出。焊球阵列可以将芯片连接到芯片载体、内插器或陶瓷封装。在本发明的替代实施例中，在划片、晶片级探针探测或后回流和芯片连接的操作之后，在钝化层内可以存在微裂纹或层离或类似的损伤。在本实施例中，在回流和芯片连接操作之后，接着将液体试剂涂敷到安装在芯片载体、内插器或陶瓷封装上的芯片。然后可以涂敷第二引发剂。
在优选实施例中，修复和密封损伤芯片的方法包括：使半导体芯片经历真空、例如约10×10-3托的真空，涂敷液体试剂或密封剂到芯片，以及使芯片受热和/或紫外(UV)光固化。优选芯片经受热固化，以及封装中在最低焊接(铜焊)液相线下的优选温度范围约为20℃。最优选的温度范围约为150至220℃。约1分钟至1小时的固化时间是优选的，约5分钟至30分钟最优选。
或者，芯片可以经受UV固化。优选的UV光源是高压Hg或Xe/Hg灯。最优选UV固化与热处理结合使用，在约150至220℃范围的温度下。约5分钟至30分钟的固化时间是最优选的。
在另一实施例中，该方法包括：使半导体芯片经历约10×10-3托的真空，涂敷液体试剂或密封剂到芯片，增加压力到约5个大气压，以及使芯片受热和/或UV光固化。
在又一个实施例中，该方法包括：在环境压力下涂敷液体试剂或密封剂，以及使芯片受热和/或UV光固化。
在又一个实施例中，该方法包括：在环境压力下涂敷液体试剂或密封剂，增加压力到约5个大气压，以及使芯片受热和/或UV光固化。
在又一个实施例中，该方法包括使半导体芯片经历约10×10-3托的真空，涂敷液体试剂或密封剂到芯片，以及涂敷第二引发剂或化学固化剂。
在又一个实施例中，该方法包括使半导体芯片经历约10×10-3托的真空，涂敷液体试剂或密封剂到芯片，增加压力到约5个大气压，然后涂敷第二引发剂或化学固化剂。
在又一个实施例中，该方法包括：在环境压力下涂敷液体试剂或密封剂，以及涂敷第二引发剂或化学固化剂。
在又一个实施例中，该方法包括：在环境压力下涂敷液体试剂或密封剂，增加压力到约5个大气压，以及涂敷第二引发剂或化学固化剂。
尽管结合具体优选实施例及其他替代实施例具体描述了本发明，但是对于所属领域的技术人员来说，根据上述描述，多种替代方案、改进和改变都是显而易见的。因此打算包含所有落入本发明的真正范围和精神的这些替代方案、改进和改变在附加权利要求中。

Claims (21)

1、一种集成电路芯片，包括：
在所述集成电路芯片的顶表面处的第一电介质材料(35)；
连接到所述集成电路芯片的顶表面的电连接(20)；以及
在所述集成电路芯片的顶表面顶上的第二电介质材料(50)层，其中所述第二电介质材料是含硅的保形密封剂。
2、根据权利要求1的集成电路芯片，其中所述电连接(20)是引线键合。
3、根据权利要求1的集成电路芯片，其中所述电连接(20)是将芯片连接到芯片载体、内插器或陶瓷封装的焊接连接。
4、根据权利要求1的集成电路芯片，其中所述第一电介质材料(35)在包含微裂纹(40)的顶表面，以及所述第二电介质材料(50)保形地填充微裂纹(40)。
5、根据权利要求4的集成电路芯片，其中微裂纹(40)具有1微米以下的宽度，以及10微米以下的深度。
6、根据权利要求4的集成电路芯片，其中微裂纹(40)具有约0.5微米的宽度，以及约1至约5微米的深度。
7、根据权利要求1的集成电路芯片，其中集成电路芯片包含所述第一电介质材料(35)底下的层离，以及所述第二电介质材料(50)保形地填充该层离。
8、根据权利要求1的集成电路芯片，其中第二电介质材料(50)包括活性的、低粘度、含硅材料，该材料选自由烷氧基硅烷、硅氧烷、硅氮烷、环氧硅氧烷(包括烷氧基环氧硅氧烷)、环氧硅氮烷、尿素-硅氮烷、碳硅氮烷、尿素-硅氧烷、碳硅氧烷、聚硅氮烷、聚脲硅氮烷、聚碳硅氮烷、聚硅氧烷、聚脲硅氧烷、聚碳硅氧烷、相关的含硅聚合物、TEOS(正硅酸乙酯、四乙基正硅酸酯)、HMDS(六甲基二硅氮烷)、TMCTS(四甲基环四硅氧烷)以及3MC3S(三甲基环三硅氧烷)构成的组。
9、一种用于包封集成电路芯片的方法，该方法包括以下步骤：
将电连接(20)连接到集成电路芯片的顶表面，其中顶表面由第一电介质材料(35)组成；
在所述集成电路芯片的顶表面顶上淀积第二材料(50)，其中该第二材料(50)包括含硅的保形密封剂前体；以及
处理淀积的第二材料，以引起前体的反应从而形成第二电介质材料。
10、根据权利要求9的方法，其中所述电连接(20)是引线键合。
11、根据权利要求9的方法，其中第二材料(50)包括活性的、低粘度、含硅材料，该材料选自由烷氧基硅烷、硅氧烷、硅氮烷、环氧硅氧烷(包括烷氧基环氧硅氧烷)、环氧硅氮烷、尿素硅氮烷、碳硅氮烷、尿素硅氧烷、碳硅氧烷、聚硅氮烷、聚脲硅氮烷、聚碳硅氮烷、聚硅氧烷、聚脲硅氧烷、聚碳硅氧烷、相关的含硅聚合物、TEOS(正硅酸乙酯、四乙基正硅酸酯)、HMDS(六甲基二硅氮烷)、TMCTS(四甲基环四硅氧烷)以及3MC3S(三甲基环三硅氧烷)构成的组。
12、根据权利要求9的方法，其中通过加热所述第二材料处理第二材料(50)。
13、根据权利要求12的方法，其中在真空中加热第二材料(50)。
14、根据权利要求12的方法，其中在真空中淀积第二材料(50)，以及其中该方法还包括在处理淀积的第二材料(35)之前增加压力的步骤。
15、根据权利要求12的方法，其中在水蒸汽存在的情况下加热第二材料(50)。
16、根据权利要求9的方法，其中第二材料(50)还包括试剂。
17、根据权利要求9的方法，其中所述第一电介质材料(35)在包含微裂纹(40)的顶表面处，以及第二电介质材料(50)保形地填充该微裂纹。
18、根据权利要求13的方法，其中在真空中淀积第二材料(50)。
19、根据权利要求17的方法，还包括在淀积第二材料(50)之后增加压力至大气压的步骤。
20、根据权利要求14的方法，还包括在淀积第二材料(50)之后增加压力到约5个大气压的步骤。
21、根据权利要求9的方法，其中集成电路芯片包含第一电介质材料(35)底下的层离，以及第二电介质材料(50)保形地填充该层离。
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