CN1619325A - Boundary scanning testing controller and boundary scanning testing method - Google Patents
Boundary scanning testing controller and boundary scanning testing method Download PDFInfo
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- CN1619325A CN1619325A CN 200310115353 CN200310115353A CN1619325A CN 1619325 A CN1619325 A CN 1619325A CN 200310115353 CN200310115353 CN 200310115353 CN 200310115353 A CN200310115353 A CN 200310115353A CN 1619325 A CN1619325 A CN 1619325A
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Abstract
The present invention relats to a boundary scanning test controller. It is characterized by that it includes PCI slave interface module and memory control interface module, the boundary scanning control interface module and memory control interface module are connected with PCI slave interface module by means of data wire. Said invention also provides its boundary scanning test method.
Description
Technical field
The present invention relates to the measuring technology of the electronics or the communications field, especially a kind of Boundary Scan Controller and boundary scanning test method.
Technical background
Boundary scan testing is the method that a kind of boundary scan register unit that utilizes device inside is tested.By the visit of test storage port (Test Access Port) to boundary scan register, can deposit by the sign of device inside and test, also can realize the interconnecting test of the I/O pin between the device and programming operation etc.As shown in Figure 1, be the structural representation of boundary scanning device.
Along with the continuous development of integrated circuit and application thereof, boundary scan technique is used in the test of single-plate grade, device level more and more widely, also arises at the historic moment based on the tester of boundary scan technique.One typically based on the structure of the tester of boundary scan technique as shown in Figure 2.
Though the application of boundary scan testing more and more widely, the application of boundary scan testing instrument has very big dependence to boundary scan controller.Boundary scan controller with the VXI interface is an example, this interface is common in ICT (In-Circuit Test) testing apparatus, though can realize boundary scan testing on this special test equipment, this interface can't be applied to portable testing apparatus or maintenance of equipment; The test controller of parallel port type utilizes the parallel interface of computing machine as input/output interface, have and use simple, reliable characteristics, but because signaling rate is lower, when carrying out the test of interconnection line between components and parts, perhaps carry out the occasion of big data quantities such as storer (as RAM) unit testing, test speed is slower, can not satisfy testing requirement.
The basic function of Boundary Scan Controller is to cooperate the test terminal, sends test data to tested scan chain, and sends the test terminal to after the output signal sampling preservation with measured piece (veneer or chip).The functional schematic of a typical test controller as shown in Figure 3.
The Boundary Scan Controller of parallel port form, owing to be output and the input that realizes test data by the method for software simulation, it realizes that principle is simple relatively, and, because general computing machine all has parallel interface, so the controller applicability of this form is better.
But the test controller of parallel port form is owing to be subjected to the restriction of the data rate of parallel port, and the signal rate of the speed of its test output signal and the test of permission input is lower.With common and port transmission rate 1Mbits/ second be example, use software simulation, during with byte mode read-write parallel port, the maximum rate of change of each output signal is 125K time in the per second kind, the maximum frequency that clock (TCK) is exported in test is 62.5KHz.Than under the complicated situation, perhaps under the situation of carrying out the memory cell test, this signal speed far can not satisfy testing requirement at the circuit-under-test plate.
Test controller with VXI interface, its test output and test input are to realize by the circuit of special use, therefore, the signal rate of its test output can design by testing requirement.But, because the VXI interface is the interface of an instrument, only be applicable on some special-purpose testing apparatuss, some application scenario, as, debugging single board or veneer maintenance do not have such condition.
Summary of the invention
The invention provides a kind of Boundary Scan Controller and boundary scanning test method, to solve the slow problem of test speed that exists in the prior art.
For addressing the above problem, the invention provides following solution:
A kind of Boundary Scan Controller comprises:
PCI slave unit interface module is used for the configuration and the read-write operation of pci bus;
Storer control interface module links to each other by data line with PCI slave unit interface module, is used for the read-write operation to memory data;
Boundary scan control interface module links to each other by data line with PCI slave unit interface module with storer control interface module, is used for the data of storer are outputed to the test interface of Board Under Test, and will be saved in the storer from the data that Board Under Test samples.
Described PCI slave unit interface module is a pci interface chip.
Described PCI slave unit interface module is a programmable logic device (PLD).
Described memory control module has a port memory at least.
A kind of boundary scanning test method may further comprise the steps:
A, test terminal are stored test data in the storer into;
B, boundary scan control interface become the signal of jtag interface correspondence with the test data conversion in the storer and output to the test interface of Board Under Test;
C, boundary scan control interface will be saved in the storer from the data of Board Under Test sampling;
D, judge whether data to be scanned are exported and finish, if enter step e; If not, return step b;
Return data is read in e, test terminal from storer.
The signal of described jtag interface correspondence comprises: the data input TDI of TRST, TCK, TMS and measurand.
Described boundary scanning test method also is included in each TCK in the cycle, and the TDO of sampling measurand exports, and this signal condition is saved in the storer as test response.
Described steps d is returned end of scan signal by the boundary scan control interface to pci interface and is finished.
Described boundary scanning test method, the data of transmission once before the test data of being transmitted is compared, it is different having only partial data, then in described step b, only transmits the data of this different piece, among the step e, reading of data in the same way.
Boundary Scan Controller of the present invention is because the employing pci interface carries out data transmission, and pci interface is implemented on the multi-purpose computer widely, so sort controller can be adapted to multi-purpose computer; Simultaneously, adopt the method test signal speed height of design test instrument of the present invention, help improving test speed.Owing to adopt the pci interface transmitting test data, and realize the output and the input of boundary scan signal, so the speed of design test signal is with the adaptive testing demand neatly by programmable logic device (PLD).
Description of drawings
Fig. 1 is a boundary scanning device structural representation in the prior art;
Fig. 2 is based on the typical synoptic diagram of the test of boundary scan technique in the prior art;
Fig. 3 is the illustrative view of functional configuration of boundary scan controller in the prior art;
Fig. 4 is the structural representation of being with the Boundary Scan Controller of pci interface that the present invention designs;
Fig. 5 is the synoptic diagram of pci interface signal definition in the prior art;
Fig. 6 is a boundary scan interface output signal sequential synoptic diagram of the present invention;
Fig. 7 is the method for testing process flow diagram of practical this Boundary Scan Controller of the present invention;
Fig. 8 is among the present invention program, a data transfer mode synoptic diagram.
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is described.
As shown in Figure 4, be the Boundary Scan Controller that the present invention designs, it mainly comprises 3 parts, is respectively PCI slave unit interface module, boundary scan control interface module and storer control interface module, links to each other by data line between 3 modules.Wherein:
PCI slave unit interface module is connected with the pci interface of test terminal, realizes configuration, the read/write operation of pci bus.The read-write operation of pci bus interface is realized two functions: to the visit of storer; Control to boundary scan interface.PCI slave unit interface can be realized with special-purpose pci interface chip, as the FW21154AE of Intel Company, also can realize by programmable logic device (PLD), as FPGA.
Among the present invention, PCI slave unit interface is followed PCI local bus specification 2.1 (PCI Local BusSpecification, Rev 2.1).The signal of pci interface comprises prerequisite signal (Required Pins) and optional signal (Optional Pins).The pci interface signal definition is illustrated in fig. 5 shown below, and controller described in the invention has been realized PCI slave unit interface function, and does not have defined optional signal in the operating specification.
The pci interface module control of boundary scan interface is comprised the startup that scans output/input and stop, the size of invisible scanning data volume, scanning output signal frequency etc.These control operations can realize by the I/O write operation of PCI.
Boundary scan control interface module links to each other with the scanning input/output interface of Board Under Test at work, under the control of pci bus, data in the storer are outputed to the test interface of Board Under Test, from the Board Under Test sampled signal and be kept at the storer, its input and output realize by programmable logic device (PLD).According to the related specifications of JTAG, the output signal of boundary scan control interface module is illustrated in fig. 6 shown below, as can be seen from the figure, when not starting scanning output ,/TRST output low level; When starting scanning ,/TRST exports high level.TCK exports test clock, and TMS and TDI change at the negative edge of TCK.
The boundary scan testing interface module is in each TCK value of TDO of sampling in the cycle, and is saved in the storer by turn.Behind the end of scan, the TDO data are read in the test terminal from storer.
When test data was outputed to test interface, boundary scan interface at first read the content in the storer, and the content in this unit is exported by turn.In output data by turn, boundary scan interface reads the data that the next one will be output again from storer, and preserves current TDO, and so circulation is up to the end of scan.
The boundary scan control interface of being realized among the present invention does not make an explanation to data, and which is not a steering order to measured piece in the differentiating measurement data, and which is data, and, also in inner control and the judgement that realizes the measured piece state of scan control interface.The data way of output of this transparent transmission has the realization characteristic of simple.At concrete test process, the State Control of Board Under Test (or device) is realized that by software this method provides bigger dirigibility for practical application fully.
The TCK frequency of boundary scan output is controlled by the read-write operation of pci interface.To in the boundary scan interface control, the signal delay time of the input signal of test interface with respect to TCK output can also be set.
Be connected with storer in the memory interface module work, each data that produces are preserved, because boundary scan interface and PCI slave unit interface all will be operated storer, so, read-write operation to storer need carry out timesharing control, that is,, then do not allow these two interfaces reference-to storage simultaneously if select the storer of single port for use; If when using dual-ported memory, these two interfaces need independent connection control signal line to storer.
With the one-port memory is example, when boundary scan interface scanning when output, do not allow the pci interface reference-to storage.
The control section of storer can design in boundary scan control logic, and when using FPGA (Field Programmable Gate Array) to realize PCI slave unit interface, the read-write control of storer also can design in PCI slave unit interface logic.
As shown in Figure 7, be to use the boundary scanning test method of Boundary Scan Controller of the present invention, as can be seen from the figure, it may further comprise the steps:
A, test terminal are stored test data in the storer into by the write operation of pci bus;
When carrying out boundary scan testing, at first to test data be stored in the storer by the write operation of test terminal by pci bus on it, because aforesaid Boundary Scan Controller has pci interface, so can carry out the various operations of data easily by this pci interface.
B, boundary scan control interface become the signal of jtag interface correspondence with the test data conversion in the storer and output to the test interface of Board Under Test;
Test data in the storer is loaded into the test interface of Board Under Test, has promptly begun test the inner boundary scanning device of Board Under Test.
Here need the data-switching that writes is become the signal output of jtag interface correspondence, these signals comprise/the data input TDI of TRST, TCK, TMS and measurand, simultaneously, at the TCK of each output in the cycle, the TDO output of sampling measurand, and this signal condition is saved in the storer in the controller as test response;
When test data was outputed to test interface, scan interface at first read the content in the storer, and the content in this unit is exported by turn.In output data by turn, boundary scan interface reads the data that the next one will be output again from storer, and preserves current TDO, and so circulation is up to the end of scan.
The boundary scan control interface of being realized among the present invention does not make an explanation to data, and which is not a steering order to measured piece in the differentiating measurement data, and which is data, and, also in inner control and the judgement that realizes the measured piece state of scan control interface.The data way of output of this transparent transmission has the realization characteristic of simple.At concrete test process, the State Control of Board Under Test is realized that by software this method provides bigger dirigibility for practical application fully.
C, boundary scan control interface will be saved in the storer from the data of Board Under Test sampling;
To being stored to earlier the storer, when the end of scan,, send the test terminal to and analyze in reading of data from storer from the Board Under Test sampled data.
The TCK frequency of boundary scan output is controlled by the read-write operation of pci interface.To in the boundary scan interface control, the signal delay time of the input signal of test interface with respect to TCK output can also be set.
D, judge whether data to be scanned are exported and finish, if enter step e; If not, return step b;
This step is returned end of scan signal by the boundary scan control interface to pci interface and is finished.When storer data output to be scanned finished, the boundary scan control interface returned end of scan signal to pci interface, and return data is read after receiving this signal again in the test terminal from storer.
Return data is read in e, test terminal from storer.
Carrying out the test of interconnecting test, memory cell, when perhaps utilizing the test interface of Board Under Test to programme, pci interface need transmit lot of data.Characteristics according to boundary scan testing, in the data of each transmission, have only partial data to change, therefore, can when the first time, data transmitted, transmit complete data, only transmit the data of those variations later on, this method can reduce volume of transmitted data at every turn, improves the travelling speed of test controller.Utilize process that this mode carries out the test data write operation as shown in Figure 7.
As can see from Figure 8, when the memory write data, the data of all storage unit are all write one time for the first time; From for the second time, if having only the 3rd group of data to change, and the data of other group are not when changing, just can be only to the 3rd group of data cell execution refresh operation, and other storage unit is not conducted interviews.
Because the quantity of boundary scan output data equals the quantity of boundary scan input data, therefore, if test refreshing of output data with said method, among the above-mentioned steps e, also must read rreturn value from storage unit with identical method.
Boundary Scan Controller of the present invention is because the employing pci interface carries out data transmission, and pci interface is implemented on the multi-purpose computer widely, so sort controller can be adapted to multi-purpose computer; Simultaneously, adopting the present invention is the method test signal speed height of equipment, helps improving test speed.Owing to adopt the pci interface transmitting test data, and realize the output and the input of boundary scan signal, so the speed of design test signal is with the adaptive testing demand neatly by programmable logic device (PLD).
Claims (9)
1, a kind of Boundary Scan Controller is characterized in that comprising:
PCI slave unit interface module is used for the configuration and the read-write operation of pci bus;
Storer control interface module links to each other by data line with PCI slave unit interface module, is used for the read-write operation to memory data;
Boundary scan control interface module links to each other by data line with PCI slave unit interface module with storer control interface module, is used for the data of storer are outputed to the test interface of Board Under Test, and will be saved in the storer from the data that Board Under Test samples.
2, Boundary Scan Controller as claimed in claim 1 is characterized in that described PCI slave unit interface module, is pci interface chip.
3, Boundary Scan Controller as claimed in claim 1 is characterized in that described PCI slave unit interface module, is programmable logic device (PLD).
4, Boundary Scan Controller as claimed in claim 1 is characterized in that described memory control module, has a port memory at least.
5, a kind of boundary scanning test method is characterized in that may further comprise the steps:
A, test terminal are stored test data in the storer into;
B, boundary scan control interface become the signal of jtag interface correspondence with the test data conversion in the storer and output to the test interface of Board Under Test;
C, boundary scan control interface will be saved in the storer from the data of Board Under Test sampling;
D, judge whether data to be scanned are exported and finish, if enter step e; If not, return step b;
Return data is read in e, test terminal from storer.
6, boundary scanning test method as claimed in claim 5 is characterized in that the signal of described jtag interface correspondence comprises: the data input TDI of TRST, TCK, TMS and measurand.
7, boundary scanning test method as claimed in claim 5 is characterized in that also being included in each TCK in the cycle, and the TDO of sampling measurand exports, and this signal condition is saved in the storer as test response.
8, boundary scanning test method as claimed in claim 5 is characterized in that described steps d, returns end of scan signal by the boundary scan control interface to pci interface and finishes.
9, boundary scanning test method as claimed in claim 5, it is characterized in that before working as the test data of being transmitted compares the once data of transmission, it is different having only partial data, then in described step b, only transmit the data of this different piece, among the step e, reading of data in the same way.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097242B (en) * | 2006-06-27 | 2010-04-21 | 中兴通讯股份有限公司 | Boundary scan testing controller and testing method thereof |
| CN102183727A (en) * | 2011-06-01 | 2011-09-14 | 浙江大学 | Boundary scanning test method with error detection function |
| CN102540046A (en) * | 2010-12-14 | 2012-07-04 | 苏州工业园区谱芯科技有限公司 | Test method of reduced board-level physical test points |
| CN103163451A (en) * | 2013-03-06 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Super computing system oriented self-gating boundary scan test method and device |
| CN103884949A (en) * | 2010-12-14 | 2014-06-25 | 苏州工业园区谱芯科技有限公司 | Test method for reducing board level physical test points |
| CN112305396A (en) * | 2019-07-23 | 2021-02-02 | 株洲中车时代电气股份有限公司 | Test system and test method |
| CN112462245A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Method and device for generating boundary scanning interconnection line |
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| US5544309A (en) * | 1993-04-22 | 1996-08-06 | International Business Machines Corporation | Data processing system with modified planar for boundary scan diagnostics |
| US5809036A (en) * | 1993-11-29 | 1998-09-15 | Motorola, Inc. | Boundary-scan testable system and method |
| US5631912A (en) * | 1995-12-19 | 1997-05-20 | Samsung Electronics Co., Ltd. | High impedance test mode for JTAG |
| US6324663B1 (en) * | 1998-10-22 | 2001-11-27 | Vlsi Technology, Inc. | System and method to test internal PCI agents |
| GB2370364B (en) * | 2000-12-22 | 2004-06-30 | Advanced Risc Mach Ltd | Testing integrated circuits |
| US6738939B2 (en) * | 2001-05-21 | 2004-05-18 | Intel Corporation | Method and apparatus for fault tolerant and flexible test signature generator |
| CN1369714A (en) * | 2001-07-18 | 2002-09-18 | 中国人民解放军第二炮兵工程学院技术开发中心 | Boundary scan and test system for large-scale integrated circuit |
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2003
- 2003-11-19 CN CNB2003101153538A patent/CN100370269C/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097242B (en) * | 2006-06-27 | 2010-04-21 | 中兴通讯股份有限公司 | Boundary scan testing controller and testing method thereof |
| CN102540046A (en) * | 2010-12-14 | 2012-07-04 | 苏州工业园区谱芯科技有限公司 | Test method of reduced board-level physical test points |
| CN103884949A (en) * | 2010-12-14 | 2014-06-25 | 苏州工业园区谱芯科技有限公司 | Test method for reducing board level physical test points |
| CN102540046B (en) * | 2010-12-14 | 2014-09-10 | 苏州工业园区谱芯科技有限公司 | Test method of reduced board-level physical test points |
| CN103884949B (en) * | 2010-12-14 | 2016-08-24 | 盛科网络（苏州）有限公司 | The method of testing of reduced board-level physical test points |
| CN102183727A (en) * | 2011-06-01 | 2011-09-14 | 浙江大学 | Boundary scanning test method with error detection function |
| CN103163451A (en) * | 2013-03-06 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Super computing system oriented self-gating boundary scan test method and device |
| CN112305396A (en) * | 2019-07-23 | 2021-02-02 | 株洲中车时代电气股份有限公司 | Test system and test method |
| CN112462245A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Method and device for generating boundary scanning interconnection line |
| CN112462245B (en) * | 2019-09-09 | 2022-08-19 | 英业达科技有限公司 | Method and device for generating boundary scanning interconnection line |
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