CN102540046B - Test method of reduced board-level physical test points - Google Patents
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- CN102540046B CN102540046B CN201010587165.5A CN201010587165A CN102540046B CN 102540046 B CN102540046 B CN 102540046B CN 201010587165 A CN201010587165 A CN 201010587165A CN 102540046 B CN102540046 B CN 102540046B
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Abstract
The invention discloses a test method of reduced board-level physical test points, comprising the following steps of: providing a circuit board to be tested, wherein the circuit board to be tested is provided with a plurality of electronic components and a plurality of corresponding physical test points; screening the physical test points on the circuit board to be tested to select a plurality of the physical test points which can be reduced; applying an online test machine to testing the physical test points which are not reduced; and furthermore, testing the physical test points which can be reduced with the assistance of a boundary scanning test. By optimizing and reducing one part of the physical test points on the circuit board to be tested, a circuit which can be detected by the part of the reduced physical test points is detected by the boundary scanning test with a lower cost, so that the whole test cost and the whole test time are reduced.
Description
Technical field
The present invention relates to a kind of method of testing of reduced board-level physical test points, belong to integrated circuit board electrodes production test field.
Background technology
On-line testing (In-Circuit Test, ICT) be widely used in electronics manufacturing enterprise, its effect is mainly by fixture, taking the test point on PCB as interface, electronic devices and components on PCB are carried out to electric test, to diagnose electronic devices and components whether intact.
Boundary scan testing (Boundary Scan Test) is another kind of method of testing, it has defined TAP (Test Access Port, test access port) 5 pin: TDI (Test Data Input, test data input), TDO (Test Data Output, test data output), TCK (test clock), TMS (test pattern selection) and TRST (test reset, optional), wherein, TMS is used for Loading Control information; In addition, boundary scan testing has also defined several test patterns that TAP controller is supported, mainly contains outer test (EXTEST), operation test (RUNTEST) and build-in test (INTEST).When use, the scan chain of multiple scanning devices is connected together by their TAP, just can form a continuous boundary register chain, load test signal at TDI and just can control and test all pins that are connected.The virtual pin of boundary scan testing can replace the physical contact of ICT fixture to the each pin of device.
Because requiring each circuit node, traditional on-line testing has a test point at least, along with circuit scale is increasing, required test point is more and more, so corresponding fixture making complexity is also more and more higher, test duration is more and more longer, and testing cost is more and more higher.
Therefore, be necessary existing method of testing to improve, a kind of method of testing that has efficiency and cost concurrently is provided.
Summary of the invention
Technical matters to be solved by this invention is to provide the method for testing of the reduced board-level physical test points that a kind of testing cost is low, the test duration is short.
For solving the problems of the technologies described above, the present invention adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprise the steps: S1, circuit board under test is provided, some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device, storage component part and one or more resistance between boundary scanning device and storage component part; S2, screens the physical testing point on circuit board under test, filters out the physical testing point between physical testing point, resistance and the storage component part between boundary scanning device and resistance in the above-mentioned electronic devices and components that can be subdued; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
For solving the problems of the technologies described above, the present invention also adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprise the steps: S1, circuit board under test is provided, some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective two boundary scanning devices and parallel resistance; S2, screens the physical testing point on circuit board under test, filters out in the above-mentioned electronic devices and components that can be subdued between these two boundary scanning devices with the connected physical testing point of parallel resistance; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
For solving the problems of the technologies described above, the present invention also adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprise the steps: S1, circuit board under test is provided, some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device, storage component part and middle interval pull-up resistor; S2, screens the physical testing point on circuit board under test, filters out the physical testing point between boundary scanning device and middle interval pull-up resistor in the above-mentioned electronic devices and components that can be subdued; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
For solving the problems of the technologies described above, the present invention also adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device and middle interval pull-up resistor or middle interval pull down resistor; S2, screens the physical testing point on circuit board under test, filters out the physical testing point between boundary scanning device and middle interval pull-up resistor or middle interval pull down resistor in the above-mentioned electronic devices and components that can be subdued; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
For solving the problems of the technologies described above, the present invention also adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprise the steps: S1, circuit board under test is provided, some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise two boundary scanning devices that link together, two pull down resistors and two electric capacity; S2, physical testing point on circuit board under test is screened, filter out in the above-mentioned electronic devices and components that can be subdued between boundary scanning device and pull down resistor with the connected physical testing point of differential lines, be connected the physical testing point between pull down resistor and electric capacity; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
For solving the problems of the technologies described above, the present invention also adopts following technical scheme: a kind of method of testing of reduced board-level physical test points, comprise the steps: S1, circuit board under test is provided, some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise two boundary scanning devices, pull down resistor and electric capacity linking together; S2, screens the physical testing point on circuit board under test, filters out the physical testing point that connects pull down resistor and electric capacity in the above-mentioned electronic devices and components that can be subdued; S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
Compared to prior art, the present invention is by being optimized and subduing part physical testing point on circuit board under test, the circuit that the physical testing point that this part is subdued can measure completes by lower-cost boundary scan testing, thereby reduces whole testing cost and time.
Brief description of the drawings
Fig. 1 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point on the direct-connected netting twine of two boundary scanning device pins can be subdued.
Fig. 2 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point between boundary scanning device-storage component part can be subdued.
Fig. 3 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point between boundary scanning device-single or multiple resistance-storage component parts can be subdued.
Fig. 4 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point between boundary scanning device-impact damper-boundary scanning device can be subdued.
Fig. 5 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point (being connected with differential lines) between boundary scanning device-electric capacity-boundary scanning device can be subdued.
Fig. 6 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point (being connected with differential lines) between boundary scanning device-boundary scanning device can be subdued.
Fig. 7 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point (being connected with parallel resistance) between boundary scanning device-boundary scanning device can be subdued.
Fig. 8 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, between boundary scanning device-boundary scanning device, the test point of (middle interval pull-up resistor) can be subdued.
Fig. 9 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, between boundary scanning device-storage component part, the test point of (middle interval pull-up resistor) can be subdued.
Figure 10 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point of boundary scanning device-pull-up resistor can be subdued.
Figure 11 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, between boundary scanning device-boundary scanning device, the test point of (middle interval pull down resistor) can be subdued.
Figure 12 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point of boundary scanning device-pull down resistor can be subdued.
Figure 13 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point that (connects pull down resistor and electric capacity, be connected with differential lines) between boundary scanning device-boundary scanning device can be subdued.
Figure 14 is the physical testing point that can be subdued in method of testing of the present invention, and wherein, the test point that (connects pull down resistor and electric capacity) between boundary scanning device-boundary scanning device can be subdued.
Embodiment
On the circuit board under test (not shown) that utilizes method of testing of the present invention to detect, some electronic devices and components are installed, such as boundary scanning device, storage component part, resistance and electric capacity etc., and on circuit board under test, form the physical testing point of some these electronic devices and components of correspondence.These electronic devices and components link together by the conductive path on circuit board under test (connecting line in ginseng Fig. 1 to Figure 14) correspondence, make circuit board have specific function.
The method of testing of reduced board-level physical test points of the present invention, comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and physical testing point are installed on described circuit board under test;
S2, screens the physical testing point on circuit board under test, to choose the some physical testing points that can be subdued;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
Shown in please refer to the drawing 1 to Figure 14, the physical testing point TPR that can be subdued in the method for testing of reduced board-level physical test points of the present invention represents, is described as follows.
Shown in please refer to the drawing 1, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), wherein, the physical testing point on the direct-connected netting twine of this two boundary scanning devices (BSD1, BSD2) pin can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 2, a boundary scanning device (BSD) and a storage component part (MEM) are installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD) and storage component part (MEM) can be subdued,, the physical testing point between boundary scanning device (BSD)-storage component part (MEM) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 3, a boundary scanning device (BSD) is installed on circuit board under test (not shown), a storage component part (MEM), and be positioned at one or more resistance (R) between boundary scanning device (BSD) and storage component part (MEM), wherein, physical testing point between boundary scanning device (BSD) and resistance (R) can be subdued, and, physical testing point between resistance (R) and storage component part (MEM) also can be subdued, , physical testing point between boundary scanning device (BSD)-single or multiple resistance (R)-storage component part (MEM) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 4, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown) and are positioned at the impact damper (BUF) between these two boundary scanning devices (BSD1, BSD2), wherein, physical testing point between each boundary scanning device (BSD1, BSD2) and impact damper (BUF) all can be subdued,, the physical testing point between boundary scanning device (BSD1)-impact damper (BUF)-boundary scanning device (BSD2) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 5, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown) and are positioned at this two boundary scanning device (BSD1, BSD2) two electric capacity (being respectively C1 and C2) between, wherein, with the connected electric capacity (C1 of differential lines, C2) with boundary scanning device (BSD1, BSD2) the physical testing point between all can be subdued, , with the connected boundary scanning device of differential lines (BSD1)-electric capacity (C1, physical testing point between C2)-boundary scanning device (BSD2) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 6, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), wherein, between these two boundary scanning devices (being respectively BSD1 and BSD2), all can be subdued with the connected physical testing point of differential lines,, can be subdued with the physical testing point between the connected boundary scanning device of differential lines (BSD1)-boundary scanning device (BSD2).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 7, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), wherein, between these two boundary scanning devices (being respectively BSD1 and BSD2), all can be subdued with the connected physical testing point of parallel resistance (R),, can be subdued with the physical testing point between connected boundary scanning device (the BSD1)-boundary scanning device (BSD2) of parallel resistance (R).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 8, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD1) and middle interval pull-up resistor (R) all can be subdued,, can be subdued with the physical testing point between boundary scanning device (the BSD1)-boundary scanning device (BSD2) of middle interval pull-up resistor (R).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 9, a boundary scanning device (BSD1) and a storage component part (MEM) are installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD1) and middle interval pull-up resistor (R) all can be subdued,, can be subdued with the physical testing point between boundary scanning device (the BSD1)-storage component part (MEM) of middle interval pull-up resistor (R).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 10, a boundary scanning device (BSD) is installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD) and middle interval pull-up resistor (R) all can be subdued,, the physical testing point between boundary scanning device (BSD)-pull-up resistor (R) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 11, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD1) and middle interval pull down resistor (R) all can be subdued,, can be subdued with the physical testing point between boundary scanning device (the BSD1)-boundary scanning device (BSD2) of middle interval pull down resistor (R).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 12, a boundary scanning device (BSD) is installed on circuit board under test (not shown), wherein, physical testing point between boundary scanning device (BSD) and middle interval pull down resistor (R) all can be subdued,, the physical testing point between boundary scanning device (BSD)-pull down resistor (R) can be subdued.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 13, two boundary scanning devices (being respectively BSD1 and BSD2) are installed on circuit board under test (not shown), two pull down resistor (R1, and electric capacity (C1 R2), C2), wherein, boundary scanning device (BSD1, BSD2) with pull down resistor (R1, R2) between, all can be subdued with the connected physical testing point of differential lines, in addition, connect pull down resistor (R1, and electric capacity (C1 R2), C2) the physical testing point between also can be subdued, , between boundary scanning device (BSD1)-boundary scanning device (BSD2), connect pull down resistor (R1, R2) with electric capacity (C1, C2), and can be subdued with the connected physical testing point of differential lines.The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Shown in please refer to the drawing 14, two boundary scanning devices (being respectively BSD1 and BSD2), pull down resistor (R) and electric capacity (C) are installed on circuit board under test (not shown), wherein, the physical testing point that connects pull down resistor (R) and electric capacity (C) can be subdued,, between boundary scanning device (BSD1)-boundary scanning device (BSD2), connect pull down resistor (R) and can be subdued with the physical testing point of electric capacity (C).The circuit that this part physical testing point can be measured completes by lower-cost boundary scan testing.
Compared to prior art, the present invention tests electronic devices and components on circuit board under test by on-line testing, in addition, part physical testing point on circuit board under test is optimized and is subdued, the circuit that the physical testing point that this part is subdued can measure completes by lower-cost boundary scan testing, thereby reduces whole testing cost and time.
In sum, these are only preferred embodiment of the present invention, should not limit the scope of the invention with this, i.e. every simple equivalence of doing according to the claims in the present invention book and description of the invention content changes and modifies, and all should still remain within the scope of the patent.
Claims (6)
1. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device, storage component part and one or more resistance between boundary scanning device and storage component part;
S2, screens the physical testing point on circuit board under test, filters out the physical testing point between physical testing point, resistance and the storage component part between boundary scanning device and resistance in the above-mentioned electronic devices and components that can be subdued;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
2. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective two boundary scanning devices and parallel resistance;
S2, screens the physical testing point on circuit board under test, filters out in the above-mentioned electronic devices and components that can be subdued between two boundary scanning devices with the connected physical testing point of parallel resistance;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
3. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device, storage component part and middle interval pull-up resistor;
S2, screens the physical testing point on circuit board under test, filters out the physical testing point between boundary scanning device and middle interval pull-up resistor in the above-mentioned electronic devices and components that can be subdued;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
4. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise interconnective boundary scanning device and middle interval pull-up resistor or middle interval pull down resistor;
S2, screens the physical testing point on circuit board under test, filters out the physical testing point between boundary scanning device and middle interval pull-up resistor or middle interval pull down resistor in the above-mentioned electronic devices and components that can be subdued;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
5. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise two boundary scanning devices that link together, two pull down resistors and two electric capacity;
S2, physical testing point on circuit board under test is screened, filter out in the above-mentioned electronic devices and components that can be subdued between boundary scanning device and pull down resistor with the connected physical testing point of differential lines, be connected the physical testing point between pull down resistor and electric capacity;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
6. a method of testing for reduced board-level physical test points, is characterized in that, the method comprises the steps:
S1, provides circuit board under test, and some electronic devices and components and corresponding some physical testing points are installed on described circuit board under test; Some electronic devices and components comprise two boundary scanning devices, pull down resistor and electric capacity linking together;
S2, screens the physical testing point on circuit board under test, filters out the physical testing point that connects pull down resistor and electric capacity in the above-mentioned electronic devices and components that can be subdued;
S3, uses on-line testing to test the physical testing point of not subdued, and in addition, assists and utilizes boundary scan testing to test the physical testing point that can be subdued.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010587165.5A CN102540046B (en) | 2010-12-14 | 2010-12-14 | Test method of reduced board-level physical test points |
| CN201410152611.8A CN103884949B (en) | 2010-12-14 | 2010-12-14 | The method of testing of reduced board-level physical test points |
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| CN201010587165.5A CN102540046B (en) | 2010-12-14 | 2010-12-14 | Test method of reduced board-level physical test points |
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| CN201410152611.8A Division CN103884949B (en) | 2010-12-14 | 2010-12-14 | The method of testing of reduced board-level physical test points |
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| CN102540046B true CN102540046B (en) | 2014-09-10 |
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| TWI449927B (en) * | 2012-10-18 | 2014-08-21 | Inventec Corp | Testing system using single short group for testing boards and method thereof |
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| CN101398465A (en) * | 2007-09-28 | 2009-04-01 | 德律科技股份有限公司 | Electron component detection system and method thereof |
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| US20070032999A1 (en) * | 2005-08-05 | 2007-02-08 | Lucent Technologies Inc. | System and method for emulating hardware failures and method of testing system software incorporating the same |
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| CN1619325A (en) * | 2003-11-19 | 2005-05-25 | 华为技术有限公司 | Boundary scanning testing controller and boundary scanning testing method |
| CN101398465A (en) * | 2007-09-28 | 2009-04-01 | 德律科技股份有限公司 | Electron component detection system and method thereof |
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Effective date of registration: 20160201 Address after: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Patentee after: Centec Networks (Suzhou) Inc. Address before: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215000 B No. 5 Building 4 Building 16 unit Patentee before: Suzhou Industrial Park ICP Technologies Co., Ltd. |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215021 unit 13 / 16, floor 4, building B, No. 5, Xinghan street, Suzhou Industrial Park, Suzhou, Jiangsu Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |