CN1570877A - Universal serial communication interface debugging device and method - Google Patents
Universal serial communication interface debugging device and method Download PDFInfo
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- CN1570877A CN1570877A CN 200410037316 CN200410037316A CN1570877A CN 1570877 A CN1570877 A CN 1570877A CN 200410037316 CN200410037316 CN 200410037316 CN 200410037316 A CN200410037316 A CN 200410037316A CN 1570877 A CN1570877 A CN 1570877A
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Abstract
It's a kind of common serial communication interface commission apparatus. It comprises computer module (101), micro controller small system (102), the first communication module (105), the second communication module (106), the N communication module (107), programmed logical module (103), clock module (104); the computer module (101) finishes the man-machine interface, and communicates with micro controller small system (102) through RS232 interface, so to finish the issue of deployment command or send and receive data; the micro controller small system (102) responds the control and subsequence to each communication module; the programmed logical module (103) finishes the function that system chip selecting and address decoding; the clock module (104) can synchronize the clock in this apparatus and external clock. This invention makes the commission of common serial communication programmed and modularized.
Description
Technical field
The present invention relates to computer realm and communication field, relate in particular to the communication interface debugging of multiple serial communication mode in electronic information and the industrial control field.
Background technology
In electronic information and industrial control system, usually pass through the serial communication mode exchange message between each veneer of same system inside or between the different system.Relatively Chang Yong serial communication form has HDLC (High level Data Link Control, high-level data link control procedure), HW (HighWay, PCM pulse code modulation (PCM) transmission line), RS232, RS485, I
2C (Inter-IC, internal integrate circuit bus), SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) etc., in exploitation electronic information or industrial control system process, the hardware development personnel need debug with test macro in all kinds of serial communication interfaces, but existing computer system only provides the RS232 interface of standard to be used for and external interface, but for HDLC, HW, RS485, I
2Serial communication such as C, SPI form does not all have general debugging interface device, and the corresponding communication interface that can only use other embedded device usually carries out interface debugging, uses extremely inconvenient.
Chinese patent 01274652.5 " RS232-485 chromacoder " has been realized the automatic conversion of RS232 and RS485 communication receiving/transmission signal, make equipment can adopt the RS232 mouth of computing machine to debug or communicate by letter, but still can't debug by computing machine for the serial communication of other interface levels or protocol form with RS485 interface.
Chinese patent 95231758.3 " intelligent communication interface plate " relates to computing machine multiplex communication interface, and the intelligent communication interface that provides uses the discrete information of sending here of serial ports to collect earlier its smart machine and converges, once give computing machine with parallel mode then.The described technology of this patent has mainly improved the rate of information throughput, but total system also is only limited to TTL (Transistor-TransistorLogic with the communication form in the external world, transistor-transistor logic) UART of level (Universal Asynchronous Receiverand Transmitter, UART Universal Asynchronous Receiver Transmitter).
Through patent searching document and scientific and technical literature, do not find a kind of general, that have unified software and hardware architecture, debugging apparatus that serial communication interface mode commonly used can be provided at present as yet.
Summary of the invention
The objective of the invention is to overcome in the debugging of existing computer system serial communication interface need be according to the difference of serial communication interface form, take method complexity that different modes test brings, use inconvenient shortcoming, can make in the hope of providing a kind of that serial communication interface is easy to use, have the general serial communication interface debugging apparatus and the method for stronger versatility.
For achieving the above object, the present invention has constructed a kind of general serial communication interface debugging apparatus, it is characterized in that, comprise with lower module: computer module, MCU (Micro Controller Unit, microcontroller) mini system, first communication module, second communication module ... N communication module, programmed logical module, clock module.
Described computer module is finished the man-machine interface interface, carries out communication by RS232 interface and described MCU mini system module, finishes issuing or the transmitting-receiving of data of configuration order; Described MCU mini system is finished the control of each communication module and is continued; Described programmed logical module is finished functions such as the sheet choosing of total system and address decoding; Needs and external clock are synchronous and not essential according to selected communication form for described clock module, make this device clock and external clock synchronous.
Described first communication module, second communication module ... the N communication module can be with DLC, HW, RS485, I according to actual needs
2The combination of one or more in communication such as C, the SPI form.
Described computer module has the control interface of high level language, is used for the communication interface form of the selected needs of user, and correlation parameter is set; Described correlation parameter comprises data transmission direction, data length, data rate, interface level form etc., and the RS232 interface by described computer module is passing to debugging apparatus, to finish the debugging configuration under these information.After debugging apparatus configured, can fill in the data that will send and start in the host computer interface and send, perhaps the data that slave computer is received show in the host computer interface, finish interface debugging or test.
The present invention also provides a kind of general serial communication interface adjustment method, it is characterized in that, may further comprise the steps:
The first step: power up the operation of starter gear hardware to device;
Second step: start operation computer module operation interface;
The 3rd step: the selected communication modes that will debug at the interface;
The 4th step: in the program interface of selected communication modes, set communications protocol parameter etc.;
The 5th step: start computer module and get in touch with the foundation of device hardware;
The 6th step: carry out the debugging of communication interface transceive data;
The 7th step: finish debugging.
The present invention is by the good combination of software and hardware, host computer is finished the control and the communication each other of 8-digit microcontroller down, control and information that following 8-digit microcontroller is finished its peripheral each communication function module continue, realized having the serial communication interface debugging apparatus of strong versatility, made serial communication commonly used (HDLC, HW, RS485, I
2C, SPI etc.) debugging become sequencing and modularization, made things convenient for the debugging and the test of various serial line interfaces in the exploitation of electronic information and industrial control system.
Description of drawings
Fig. 1 is a general serial communication interface debugging apparatus structural drawing of the present invention.
Fig. 2 is the structure drawing of device as the specific embodiment of the invention.
Fig. 3 is a MCU mini system synoptic diagram in the general serial communication interface debugging apparatus of the present invention.
Fig. 4 is a general serial communication interface debugging apparatus workflow diagram of the present invention.
Embodiment
The present invention is a kind of multiple serial communication mode (HDLC, HW, RS232, RS485, I of relating to
2C, SPI etc.) the interface debugging device.In the present invention, realized HDLC, HW, RS232, RS485, I commonly used
2C, SPI communication interface form according to the software and hardware architecture of above-mentioned general serial communication interface debugging apparatus, can be added the interface of serial communication modes such as RS422 easily.
The structured flowchart of the general serial communication interface debugging apparatus that the present invention proposes as shown in Figure 1.Computer module 101 is finished the man-machine interface interface, can carry out communication with MCU mini system 102 by RS232, finishes issuing or the transmitting-receiving of data of configuration order; MCU mini system 102 is control cores of whole serial communication interface debugging apparatus, finishes the control of each communication module and continues; 105,106 ... Unit 107 be respectively first communication module 105, second communication module 106 ... N communication module 107 can be HDLC, HW, RS485, I as required
2The combination of one or more in communication such as C, the SPI form; Programmed logical module 103 is finished functions such as the sheet choosing of total system and address decoding; Needs and external clock are synchronous and not essential according to selected communication form for clock module 104, make this device clock and external clock synchronous.
Computer module 101 has the control interface of C++ high level language, the communication interface form that is used for the selected needs of user, correlation parameter is set, as: data length, data to be sent, data rate, interface level form etc., RS232 interface by computer module 101 is passing to debugging apparatus under these information, to finish the debugging configuration.After debugging apparatus configured, can fill in the data that will send and start in the host computer interface and send, perhaps the data that slave computer is received show in the host computer interface, finish interface debugging or test.
Form in the synoptic diagram (Fig. 2) in serial communication interface debugging apparatus functional module, host computer module 110 is finished the man-machine interface interface; RS232 telecommunication cable 111 couples together host computer module and the next MCU unit; MCU mini system 112 is control cores of whole serial communication interface debugging apparatus, realizes HDLC, HW, RS232, RS485, I
2The control of communication function such as C, SPI and continuing.Programmed logical module 113 is finished functions such as the sheet choosing of total system and address decoding; Clock receiver module 114 is accepted the outside single-ended or differential clocks of sending here, finishes the clock phase adjustment, makes this device clock and external clock synchronous.Communication module (115,116) is finished the HW communication function; Communication module 117 is finished the HDLC communication function; A DUART (Dual UART) communication module has been formed in Unit 118, Unit 119 and Unit 120, finishes RS232 and RS485 communication function.
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme.
1,8051 MCU mini systems
8051 MCU mini systems are control cores of serial communication interface debugging apparatus slave computer, accept the steering order of host computer module, set correct communication modes and communications protocol, control other peripheral components and between computer module and external communication interface, carry out data forwarding and level conversion.
8051 MCU mini systems are by the compatible MCU of 8051 series, compositions such as peripheral crystal oscillating circuit, indicator light circuit, supervisory circuit, SRAM expanded circuit, RS232 interface circuit, and its block diagram is as shown in Figure 3.For reflection MCU system running state directly perceived, design two pilot lamp at least, use green LED for one, i.e. run indicator RUN; Another is alarm indicator ALARM, uses red light emitting diodes.Monitoring can be selected the monitoring management IC of MAXIM company or ADI company with chip, and the present invention adopts MAX813, and finishing powers on automatically resets, hand-operated forcedly reset, supply voltage is crossed low monitoring and reset, 4 functions of watchdog reset.In control and communication debugging, store data for convenient, also make things convenient for when adopting 80C51 language compilation program simultaneously and open up external variable and data field, in system, expanded external data RAM.Generally be designed to the external RAM of 32KB byte, preferred SMD device gets final product as CY62256, IDT71256, HY62256 etc.The RS232 interface circuit is that the UART mouth that MCU is carried adopts the MAX202 family device of MAXIM company to carry out after the TTL/RS232 level conversion and the host computer module communication.
Adopted the P89C668 of Philips company among the present invention, this controller has the program Flash of 64KB, both can adopt hardware multiple programming (employing universal programmer) mode with the 87C51 compatibility, can adopt its ISP/IAP serial programming mode that shows unique characteristics simultaneously, flexible.Carry 8KB RAM in its sheet, possess I
2C interface.The outside data SRAM that expands 32KB again.
2, HW communication part
HW communication part speed can be 2M, 4M and 8M, and the existing LVDS level of the physical interface that externally provides has Transistor-Transistor Logic level again, and loopback self diagnosis and radiodiagnosis function are provided.
The HW communication part is realized by Unit 115 many speed numerals exchange chip MT8986, MT8986 has the exchange network of obstruction chip clog-free or 512 * 256 time-divisions MITEL company 256 * 256 time-divisions of producing, the Motorola cpu i/f can be provided, also can provide the Intel cpu i/f.
Control by the host computer order, HW speed can be 8M, 4M and 2M, by with device in the cooperation of HDLC protocol processes chip, the HW communication can also realize HDLC agreement communication function, its physical interface that externally provides can be LVDS (low-voltage differential signal) or Transistor-Transistor Logic level.At electronic information field, in order to improve signal transfer quality, improve the antijamming capability of signal, used the LVDS level to transmit in a large number.Before and after MT8986 input and output HW signal, increase by 116 unit LVDS transceivers (as DS90C031/DS90C032), just can realize the LVDS electric level interface.
Corresponding bit position by host computer transmission command configuration MT8986 register can provide loopback self-diagnostic function and radiodiagnosis function.
3, HDLC communication part
The HDLC communication part provides two-way HDLC communication interface, and one the tunnel works in slotted mode, and another road works in non-slotted mode, and HDLC speed can be set to 2M or 4M.This part has inner self-ring mode provides self-diagnostic function, and outwards reflective-mode provides the diagnostic function of the HDLC link of butt joint with it.
The HDLC communication part has realized 2 road HDLC communications by the extendible senior serial communication control SAB82525 in Unit 117, and one the tunnel works in slotted mode, and another road works in non-slotted mode.SAB82525 works in the INTEL mode of operation, can individual reset, the high level reset signal need be provided, and the retention time of reset level is no less than 1.8us.
The A channel of SAB82525 works in slotted mode, and the STi2 of MT8986 chip is delivered in its output, and it imports the STo3 of MT8986.The B passage of SAB82525 works in non-slotted mode, and its input and output drive to be isolated through 16244 respectively, after level conversion is TTL with external interface.
4, RS485/RS232 communication part
This part is made up of the two serial port chip 16C2552 in Unit 118 and 119 unit R S232 conversion chips, 120 unit R S485 conversion chips.16C2552 has two independently UART passages, the transmitting-receiving of each passage all has the FIFO of 16 bytes, has reduced and both can use inquiry mode also can use interrupt mode to the bandwidth demand of control CPU and the interface of CPU, for improving response speed, interrupt mode is adopted in suggestion.
The passage 1 of 16C2552 expands to the RS232 passage after the RS232 level transferring chip, the baud rate of its communication, character length, parity checking etc. are to send order for 8051 MCU by host computer to set.
The passage 2 of 16C2552 expands to the RS485 passage after the RS485 level transferring chip, the baud rate of its communication, character length, parity checking etc. also are to send order for 8051 MCU by host computer to set.
5, I
2The C/SPI interface section
Unit 121 in the frame of broken lines among Fig. 2.I
2The C/SPI interface section does not need to increase extra device on hardware, can be used as this general serial communication interface debugging apparatus additional function when using function such as HDLC, HW, RS485, RS232.
The SPI interface adopts three lines (CLK, SI, SO) of 3 IO pin simulation SPI interfaces of MCU parallel interface P1 mouth to transmit data and synchronous clock.I
2C interface both can adopt self band I
2The corresponding interface of the microcontroller of C interface also can adopt and not be with I
2The micro controller I O pin simulation of C interface in order to reduce the complexity of software, improves system reliability, and suggestion is adopted and carried I
2The microcontroller of C interface, the P89C668 that recommends previously carries I exactly
2The microcontroller of C interface.
6, CPLD part
Its FPGA (Field Programmable Gate Array) mainly contains following components:
1) reset circuit: finish the resetting of single chip in the synchronous reset of each functional chip of back that powers on or the work;
2) clock phase adjustment: in HDLC and HW communication, accept the outside synchronous clock of sending here, finish the clock phase adjustment, make this device clock and external clock synchronous.
3) sheet choosing and address decoding: sheet choosing and the address decoding of finishing each peripheral chip.
4) 8986 sequential control;
5) SAB82525 sequential control;
6) via configuration circuit: HDLC switches to the HW line level form of LVDS, TTL respectively.
6, computer module interface operation control section
Computer module interface operation control section software adopts C++ to write, and its main function has two: send order to slave computer, the selected communication modes that needs is set the related protocol parameter; Fill in the data that will send and start transmission in the host computer interface, the data that slave computer is received show in the host computer interface.
The course of work of whole serial communication interface debugging apparatus is simple and clear, is described below, and its process flow diagram as shown in Figure 4.
The first step: power up the operation of starter gear hardware to device.After device powers on, move the MCU program automatically, finish initialization and basic configuration, be in then and receive upper PC coomand mode, wait for that upper PC finishes further configuration to it MCU mini system and peripheral each communication function module thereof.
Second step: start operation computer module operation interface, eject serial communication interface debugging interface.
The 3rd step: the selected communication modes that will debug at the interface, optionally communication modes has HDLC, HW, RS485, I
2C, SPI etc., the sub-interface of debugging of each communication modes is further ejected in selected back.
The 4th step: in the sub-interface of debugging of selected communication modes, set the communications protocol parameter.For different communication modes, its communications protocol parameter that need set has nothing in common with each other, and this actual needs is selected or setting as long as press during debugging.
The 5th step: start computer module and set up with device hardware and get in touch, computing machine passing to debugging apparatus under selected communication modes in front and the communications protocol parameter information, is finished the debugging configuration by the RS232 interface.
The 6th step: carry out the debugging of communication interface transceive data.Send test data for system under test (SUT) or veneer by debugging apparatus, system under test (SUT) or veneer receive the data that send over, thereby finish the test of communication interface hardware connectedness and software arrangements correctness, also can send data to this debugging interface device, finish the bidirectional transmit-receive test of data by system under test (SUT) or veneer.
The 7th step: finish debugging.Test result perhaps in the transceive data in saving interface when debugging finishes this debugging, and the software interface of shutting down computer, hardware are down.
Claims (6)
1, a kind of general serial communication interface debugging apparatus, it is characterized in that, comprise with lower module: computer module (101), microcontroller mini system (102), first communication module (105), second communication module (106) ... N communication module (107), programmed logical module (103), clock module (104);
Described computer module (101) is finished the man-machine interface interface, carries out communication by RS232 interface and described microcontroller mini system (102) module, finishes issuing or the transmitting-receiving of data of configuration order; Described microcontroller mini system (102) finish to comprise described first communication module (105), second communication module (106) ... N communication module (107) is in the control of each interior communication module and continue; Described programmed logical module (103) is finished functions such as the sheet choosing of total system and address decoding; Needs and external clock are synchronous and not essential according to selected communication form for described clock module (104), make this device clock and external clock synchronous.
2, general serial communication interface debugging apparatus as claimed in claim 1, it is characterized in that, described first communication module (105), second communication module (106) ... N communication module (107) can be one or more the combination in the communication forms such as high-level data link control procedure, PCM pulse code modulation (PCM) transmission line, RS485, internal integrate circuit bus, Serial Peripheral Interface (SPI) according to actual needs;
3, general serial communication interface debugging apparatus as claimed in claim 1, it is characterized in that, described computer module (101) has the control interface of high level language, the communication interface form that is used for the selected needs of user, correlation parameter is set, RS232 interface by described computer module (101) is passing to debugging apparatus under these information, to finish the debugging configuration.
4, general serial communication interface debugging apparatus as claimed in claim 3 is characterized in that, described correlation parameter comprises data transmission direction, data length, data rate, interface level form etc.
5, general serial communication interface debugging apparatus as claimed in claim 3, it is characterized in that, after debugging apparatus configured, in the host computer interface, fill in the data that will send and start and send, perhaps the data that slave computer is received show in the host computer interface, finish interface debugging or test.
6, a kind of general serial communication interface adjustment method is characterized in that, may further comprise the steps:
The first step: power up the operation of starter gear hardware to device;
Second step: start operation computer module (101) operation interface;
The 3rd step: the selected communication modes that will debug at the interface;
The 4th step: in the program interface of selected communication modes, set communications protocol parameter etc.;
The 5th step: start computer module (101) and get in touch with the foundation of device hardware;
The 6th step: carry out the debugging of communication interface transceive data;
The 7th step: finish debugging.
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| CN100454270C (en) * | 2007-03-09 | 2009-01-21 | 广东技术师范学院 | Standard-based real-time logic analysis recording method and system |
| CN100458722C (en) * | 2005-12-12 | 2009-02-04 | 深圳艾科创新微电子有限公司 | System and method for debugging IC interface device by PC |
| CN101980181A (en) * | 2010-11-11 | 2011-02-23 | 四川省绵阳西南自动化研究所 | Multi-channel communication device with time unification interface |
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| CN109688213A (en) * | 2018-12-20 | 2019-04-26 | 惠州Tcl移动通信有限公司 | A kind of regulating system and its method of protocol stack data |
| CN112181753A (en) * | 2020-09-25 | 2021-01-05 | 烽火通信科技股份有限公司 | Debugging method, system and readable storage medium |
| CN112181753B (en) * | 2020-09-25 | 2022-11-04 | 烽火通信科技股份有限公司 | Debugging method, system and readable storage medium |
| CN112666846A (en) * | 2020-12-30 | 2021-04-16 | 西安现代控制技术研究所 | Multifunctional data communication interface debugging method for simulation system debugging |
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