CN1521816A - 半导体芯片封装结构及其制造方法 - Google Patents

半导体芯片封装结构及其制造方法 Download PDF

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CN1521816A
CN1521816A CNA031019528A CN03101952A CN1521816A CN 1521816 A CN1521816 A CN 1521816A CN A031019528 A CNA031019528 A CN A031019528A CN 03101952 A CN03101952 A CN 03101952A CN 1521816 A CN1521816 A CN 1521816A
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substrate
insulating barrier
electrical contact
semiconductor chip
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CN1228825C (zh
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普翰屏
黄建屏
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体芯片封装结构及其制造方法，是在基板上粘接芯片，并在该基板及芯片上布覆绝缘层，使基板焊线垫及芯片电性接点均外露出该绝缘层；之后在该绝缘层表面包括有该焊线垫及电性接点等外露部敷设金属层，经过图案化形成多条电性连接芯片电性接点与基板焊线垫的导电线路，取代传统的焊线技术，避免封装工序中发生导线倾倒或短路等问题；同时，运用线路布设技术的电性连接芯片及基板也能克服芯片尺寸及焊垫间距缩小造成的焊线限制，能符合新一代(如90纳米以下)芯片的封装要求。

Description

半导体芯片封装结构及其制造方法
技术领域
本发明是关于一种半导体芯片封装结构及其制造方法，特别是关于一种配合新一代芯片焊接间距缩小化的趋势，以成批方式(BatchType)在同一片载具上制作出多个高密度封装件的半导体芯片封装结构及其制造方法。
背景技术
球栅阵列式(Ball Grid Array，BGA)半导体封装工序是一种较先进的半导体封装技术，其特点是在基板上粘接半导体芯片并施以焊线，使连接芯片与基板之间的导线形成电性连接关系。
随着芯片集成化(Integration)程度的提高，导线布设数量激增，因此在有限的芯片面积下，只有缩减导线与导线之间的间隔距离(Pitch)，才可能容纳、布设更多的导线；但是，缩小导线间距将使导线与导线之间靠得更近，在随后的模压工序中，常会因焊线偏移(Wire Sweeping)而导致短路(Short)，影响到制成品的品质。
为改善高密度半导体芯片导线数量增加所造成的焊线间距变小的困扰，如图1所示，美国专利第5,581,122号提出了一种在芯片11外围与提供导线110焊接的焊线垫102(Fingers)之间基板10表面上，增设接地环17(Ground Ring)以及电源环18(Power Ring)的半导体封装件，此封装结构在芯片11周围增设接地环17(电源环18)，并以焊线方式将形成在芯片11电路面上为数众多的接地焊垫(电源焊垫)(未图标)，电性连接至该接地环17(该电源环18)上，使接地线112、电源线111以及连接到基板10周围焊线垫(未图标)上的信号线110分布在不同的层次空间中，增加导线之间的间距，减少因导线偏移而发生短路的事情发生。
只是上述结构虽能增加导线之间的间距，但在导线密度愈来愈高而芯片又渐趋微小化的趋势下，芯片电路表面各电性接点的间距(BondPitch)已从60微米逐渐缩减到40微米，甚至新一代芯片更缩小到30微米，这样在同一芯片下可以安置更多的输入/输出端(I/O Connection)，达到降低成本以及提升芯片功效的目标；因此上述结构已无法满足新一代芯片高度集成化的需求。
再有，为配合芯片的焊垫间距不断缩小(Fine Pitch)，基板上提供导线焊接的焊线垫间距(Bond Finger Pitch)也从150微米缩小至125微米，下一代基板的焊线垫间距更会缩小到100微米，以适应焊垫间距缩小的市场主流。而上述结构也无力解决因焊垫间距微小化引发的导线短路问题。
另一方面，若新一代芯片的电性接点间距缩小至30微米，以现有焊线机(Wire Bonder)进行导线的焊接，会受限于机械精密度的极限而遭遇瓶颈；且基板焊线垫形成时又往往因为蚀刻技术的限制，使100微米以下的间距很难再有所突破。此外，当电性接点的间距更加缩小以后，高密度布线更难控制导线之间靠近或倾倒等问题，使后续工序的实施更加困难。
为此采用覆晶技术(Flip-chip Technology)取代导线解决上述焊线问题。但是，使用覆晶技术必须在晶圆工序阶段形成成本极高的焊块；且作为承载芯片用的基板，为配合细小的焊块间距(约100至200微米)，需用增层技术(Build-up)取代传统基板工序，这样会明显提高基板的成本，无法为市场所接受(增层基板成本通常为传统基板成本的五倍以上)。
发明内容
为克服上述现有技术的缺点，本发明的主要目的在于提供一种可突破传统焊线机(Wire Bonder)限制，使芯片与基板之间毋须借由焊线电性连接，避免模压制程导致焊线短路的半导体芯片封装结构及其制法。
本发明的另一目的在于提供一种毋须使用高成本的基板增层或焊块形成技术，即可为电性接点间距缩减的新一代芯片提供电性连接的半导体芯片封装结构及其制法。
本发明的再一目的在于提供一种克服焊线极限，符合新一代芯片(如90纳米以下的芯片)封装的半导体芯片封装结构及其制法。
为达成上述目的，本发明的半导体芯片封装结构的制造方法包括下列步骤：预制-一基板，该基板具有正面及背面，在该基板正面上预先定义出芯片接置区，并在该芯片接置区外的基板正面上形成多条焊线垫；在该芯片接置区上粘接至少一个芯片，该芯片具有电路面及非电路面，在该芯片的电路面上形成多个电性接点，且每一个电性接点各对应一个焊线垫；布覆绝缘层至基板，以覆盖该芯片电路面及基板正面，并外露出各电性接点及各焊线垫；在该绝缘层上形成金属层，用以覆盖并且连接该电性接点及焊线垫；图案化该金属层，以形成多条导电线路，使该导电线路的一端连接该电性接点，另一端连接该电性接点所对应的焊线垫；形成绝缘层，用以覆盖该电性接点、导电线路及焊线垫；以及植设多个焊球至该基板的背面，供该芯片与外界装置电性连接。
本发明的半导体芯片封装结构包括：一基板，其具有正面及背面，在该基板正面上预先定义出芯片接置区，且该芯片接置区外的基板正面上分布有多条焊线垫；至少一个芯片，粘置在该芯片接置区上，该芯片具有电路面及相对的非电路面，在该电路面上形成有多个电性接点，使每一个电性接点各与一个焊线垫相互对应；绝缘层，是布覆到基板上，以覆盖该芯片电路面及基板正面，并外露出各电性接点及各焊线垫；多条导电线路，形成在该绝缘层上，用以电性连接该电性接点及焊线垫；绝缘层，用以覆盖该电性接点、导电线路及焊线垫；以及多个焊球，是植设在该基板背面，供该芯片电性连接至外界装置。
本发明的半导体芯片封装结构及其制造方法，是在封装阶段形成多个电性连接芯片的电性接点及基板焊线垫的导电线路，取代导线用于芯片与基板形成电性导接关系，借此突破焊线机(Bonder)的机械极限，避免模压时产生导线倾倒及短路等问题，从而解决新一代芯片(如90纳米以下的芯片)尺寸及间距缩减所产生的导线焊接的困难；同时又无须采用高成本的焊块形成工序(覆晶作业)或增层技术，达到降低封装成本的功效。
附图说明
图1是美国专利第5,581,122号案的半导体封装件的上视示意图；
图2是本发明的半导体芯片封装结构实施例1的剖面示意图；
图3A至图3E是图2的半导体芯片封装结构的整体制作流程图；
图4是本发明的半导体芯片封装结构的实施例2的剖面示意图；
图5是本发明的半导体芯片封装结构的实施例3的剖面示意图；
图6是本发明的半导体芯片封装结构实施例4的剖面示意图。
具体实施方式
以下配合图2至图6，详细说明本发明的半导体芯片封装结构及制法的实施例。需注意的是，图2至4均为简化的示意图式，仅以示意的方式说明本发明的基本构想，附图中仅显示与本发明有关的组件，而不是按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可以随意变更，且其组件布局形态可能更为复杂。
实施例1
如图2所示，本发明的半导体芯片封装结构2包括基板20；粘接在该基板20上的半导体芯片21，该芯片21上形成有多个电性接点212，与形成在该基板20上的多条焊线垫202互相对应；覆盖在基板20上的绝缘绝缘层22，是外露出该电性接点212及焊线垫202；多条形成在该绝缘绝缘层22上的导电线路23，用来电性连接该电性接点212及焊线垫202；覆盖该电性接点212、导电线路23及焊线垫202的绝缘层24；以及多个植设在该基板20底部的焊球25。
以下通过图3A至图3E，详细说明上述半导体芯片封装结构的整体制作流程。
首先，请参阅图3A。准备基板20及至少一个半导体芯片21，该基板20一般是双马来酰亚胺·三嗪树脂(Bismaleimide Triazine，BT)基板、FR-4基板或陶瓷基板等，其具有正面200及相对的背面201，该基板20正面200上预先定义出芯片接置区200a，以及位于该芯片接置区200a之外，供多条焊线垫202(Fingers)分布的焊线垫聚集区200b，各焊线垫202借由贯穿基板20的导电迹线203，连通到基板20背面201的焊球垫204(Ball Pads)，使芯片21的信号能够通过该焊线垫202传递至基板20及焊球(未图标)后，再传递到外界。
接着，如图所示，先将晶圆的厚度研磨至3密耳(mil)以下，切割成多条单一的半导体芯片21后，借胶粘剂26(如银胶)，将该芯片21粘接到芯片接置区200a上。该芯片21具有电路面210及非电路面211，在该电路面210上形成有多个电性接点212(Electric Contacts)，且每一个电性接点212皆与一个焊线垫202相互对应。
其次，请参阅图3B，在该基板20的正面200及芯片21上布覆绝缘层22，该绝缘层22可选由聚酰亚胺(Polyimide)或环氧树脂(Epoxy)等材质制成，借由印刷(Screen Printing)或旋转涂布(Spin Coating)等方式，将绝缘材料布覆到基板20正面200以及芯片21电路面210上，并使该电性接点212及该焊线垫202外露，基板20的其它区域则被该绝缘层22遮覆。
接着，请参阅图3C，利用溅镀(Sputtering)或无电镀镀膜(ElectrolessPlating)等方式，在包含该焊线垫202及芯片21电性接点212等露出部的绝缘层22上，敷镀一层如钛、镍钒化合物、钛钨化合物、铬、镍或铜等材料形成的薄层金属层230，作为镀层的接合层；之后在该薄层金属层230上镀设一层如镍层、铜层或镍合金、铜合金等金属材质的电路形成层231，使该芯片21电性接点212能借由两金属层230，231电性连接至基板20的焊线垫202上。
之后，请参阅图3D。在该电镀金属层231以及基板20背面上分别涂布光阻层27(Photoresist Layer)，并用光罩28覆盖以进行曝光(Exposure)、显影(Development)及蚀刻(Etching)等作业，借由图案化(Pattern)该薄层金属层230以及电路形成层231的技术，形成多条一端连接该芯片21电性接点212，另一端连接基板20焊线垫202的导电线路23，使每一个芯片21电性接点212均能通过导电线路23电性连接至相对应的基板20的焊线垫202上，以取代传统的焊线工序。
请参阅图3E。在金属层230，231图案化完成后，以常用的湿式剥除法或干式剥除法，去除该电路形成层231及基板20的背面201上的光阻层(未图标)，使该电性接点212敷设金属层后，能够借由该导电线路23电性连接到基板20焊线垫202上。
随后请参阅图2，利用模压或涂布技术，将环氧树脂(Epoxy)或聚酰亚胺(Polyimide)等绝缘材料覆盖到基板20的正面200上，形成一个遮覆该电性接点212、导电线路23及焊线垫202的绝缘层24；并在基板20的背面201植设多个焊球25，形成一个具有连接该电性接点212、导电线路23、焊线垫202、导电迹线203以及焊球25的导电路径的球栅阵列式半导体封装件。
实施例2
图4是本发明的半导体芯片封装结构的实施例2，实施例2采用的工序及结构大致与上述实施例1相同，不同之处在于，该基板30上预先定义供芯片31接置的区域上，也可开设一个面积大于该半导体芯片31的开口300a，在上片时，可借胶粘剂36将芯片31粘固到开口300a内，借由该开口300a的收纳进一步缩减芯片31电路面310与基板30正面300之间的高度差，这样一方面可缩减半导体封装件的整体高度，另一方面也能提升绝缘层布覆操作的便利性。
实施例3
图5是本发明的半导体芯片封装结构的实施例3，该实施例3采用的工序及结构与上述实施例1大致相同，其不同之处在于，该绝缘层44布覆完成后，在该绝缘层44上对应于接地导线43(指用于接地的导电线路)的位置上形成多条外露开口440，使接置在绝缘层44上方的散热件45，可借由该外露开口440电性连接至接地导线43，从而增加封装件的散热效率以及屏蔽电磁干扰的功效。
实施例4
图6是本发明的半导体芯片封装结构的实施例4，该实施例4采用的工序及结构与上述实施例大致相同，不同之处在于，该绝缘层54布覆完成后，在该绝缘层54上对应于该导电线路53的位置上形成多条外露开口540，供另一封装件或芯片55堆栈、并且电性连接到上述实施例的封装结构上，从而形成一个高度积成化的多芯片模块结构(Multi-chip Module，MCM)。
综上所述，利用上述线路布设技术，形成多条电性连接芯片的电性接点及基板焊线垫的导电线路，可解决新一代芯片(如90纳米以下的芯片)因尺寸及间距缩减造成的焊线困难，突破焊线机的机械极限，免除了模压时产生的导线倾倒、短路等问题；同时，用导电线路电性连接芯片及基板也无需采用高成本的焊块形成技术或基板增层技术，比较符合市场的经济效益。

Claims (10)

1.一种半导体封装结构的制造方法，其特征在于，该半导体芯片封装结构的制造方法包括下列步骤：
制备基板，该基板具有正面及背面，在该基板正面上预先定义出芯片接置区，并在该芯片接置区外的基板正面上形成多条焊线垫；
在该芯片接置区上粘接至少一个芯片，该芯片具有电路面及非电路面，在该芯片的电路面上形成多个电性接点，且每一个电性接点各对应一个焊线垫；
布覆绝缘层至基板，以覆盖该芯片电路面及基板正面，并外露出各电性接点及各焊线垫；
在该绝缘层上形成金属层，用以覆盖并且连接该电性接点及焊线垫；
图案化该金属层，形成多条导电线路，使该导电线路的一端连接该电性接点，另一端连接该电性接点所对应的焊线垫；
形成绝缘层，用以覆盖该电性接点、导电线路及焊线垫；以及
植设多个焊球至该基板的背面，供该芯片与外界装置电性连接。
2.如权利要求1所述的半导体芯片封装结构的制造方法，其特征在于，该金属层包括薄层金属层及电路形成层。
3.如权利要求2所述的半导体芯片封装结构的制造方法，其特征在于，该薄层金属层是以溅镀的方式形成在该绝缘层上。
4.如权利要求2所述的半导体芯片封装结构的制造方法，其特征在于，该薄层金属层是以无电镀镀膜的方式形成在该绝缘层上。
5.一种半导体芯片封装结构，其特征在于，该半导体芯片封装结构包括：
基板，其具有正面及背面，在该基板正面上预先定义出芯片接置区，且该芯片接置区外的基板正面上分布有多条焊线垫；
至少一个芯片，粘置在该芯片接置区上，该芯片具有电路面及相对的非电路面，在该电路面上形成有多个电性接点，使每一个电性接点各与一个焊线垫相互对应；
绝缘层，是布覆到基板上，以覆盖该芯片电路面及基板正面，并外露出各电性接点及各焊线垫；
多条导电线路，形成在该绝缘层上，用以电性连接该电性接点及焊线垫；
绝缘层，用以覆盖该电性接点、导电线路及焊线垫；以及
多个焊球，是植设在该基板背面，供该芯片电性连接至外界装置。
6.如权利要求5所述的半导体芯片封装结构，其特征在于，该芯片接置区上形成有一个面积大于芯片且可供芯片收纳的开孔。
7.如权利要求5所述的半导体芯片封装结构，其特征在于，该绝缘层上对应于该导电线路的位置上形成有多个外露开口。
8.如权利要求5或7所述的半导体芯片封装结构，其特征在于，该导电线路是通过该绝缘层的开口与散热件电性连接。
9.如权利要求5或7所述的半导体芯片封装结构，其特征在于，该导电线路是通过该绝缘层开口与芯片电性连接。
10.如权利要求5或7所述的半导体芯片封装结构，其特征在于，该导电线路是通过该绝缘层开口与半导体封装件电性连接。
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