CN1521622A - Recognition method for artwork of integrated circuit - Google Patents
Recognition method for artwork of integrated circuit Download PDFInfo
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- CN1521622A CN1521622A CNA031152422A CN03115242A CN1521622A CN 1521622 A CN1521622 A CN 1521622A CN A031152422 A CNA031152422 A CN A031152422A CN 03115242 A CN03115242 A CN 03115242A CN 1521622 A CN1521622 A CN 1521622A
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Abstract
The invention relates to a method for identification of integrated circuit printed drawing which is realized by computer software control, the method comprises the steps of, placing the raw information of the printed drawing into the computer, translating and editing the raw information, receiving the edit result information and drafting colored printing drawing, extracting circuit components and circuit interconnection table, storing the extracted circuit components and circuit interconnection table information, exporting the circuitry table, drafting circuitry table and exporting visual circuitry table. The invention realizes high versatility and reasonable data organization.
Description
(1) technical field
The invention belongs to the integrated circuit (IC) design technology, particularly relate to a kind of method of domain identification of integrated circuit
(2) background technology
The domain identification and the topology checking (Layout recognition and topologyverification of integrated circuit) of integrated circuit are the gordian techniquies in the integrated circuit (IC) design.In order to realize the innovation of integrated circuit (IC) design technology, must analyze and study existing designing technique, simultaneously, also be necessary ready-made integrated circuit (IC) chip is analyzed and discerned, one of gordian technique of all these work is to discern integrated circuit diagram, extracts circuit theory diagrams (being called the MASK technology) from domain.Whether two of gordian technique is after extracting circuit theory diagrams, need this quasi-circuit diagram of verification correct on principle,, carries out the topology checking (about verification technique, this case is not described in detail, and separate case is applied for a patent) of circuit that is.
The relevant patent of this class prior art has:
The patent of Matsushita Electronics Corp's (Osaka, Japan): the SIC (semiconductor integrated circuit) layout design method (Japanese patent application publication No.: 1102508, application number: 94106710.6).
The prior art only relates to the perpendicular interconnection mesh lines on the interconnection layer and the interconnection wiring problem of horizontal interconnect mesh lines, does not therefore fundamentally relate to the recognition methods in the integrated circuit Butut.
(3) summary of the invention
In view of above situation, the objective of the invention is fundamentally to solve the recognition methods problem in the integrated circuit Butut, a kind of domain recognition methods of integrated circuit has been proposed.
The object of the present invention is achieved like this:
A kind of domain recognition methods of integrated circuit, by the method for computer software control integrated circuit domain identification, described domain recognition methods comprises:
S
1Step: the raw information of in computing machine, putting into domain, the raw information of integrated circuit diagram is the source program of domain, this is a series of programs that are placed in floppy disk or the tape, and it is described to be the whole circumstances of this piece integrated circuit diagram, the source program of the object that this will discern just;
S
2Step: MASK 1 technology is that the raw information to the said integrated circuit domain compiles;
S
3Step: the disk file 1 of storage intermediate result is the result of above-mentioned MASK 1 compiling of storage;
S
4Step: MASK 2 technology are accepted the information of the compiling result of storage in the above-mentioned disk file 1, thereby are drawn out integrated circuit diagram, promptly by original plate-making data, draw out the usefulness of colored domain for analysis;
S
5Step: MASK 3 technology, the compiling result's of storage information from above-mentioned disk file 1 through graphic operation, extracts circuit component and circuit interconnection table with the domain source program;
S
6Step: the disk file 2 of storage intermediate result is the information that the storage said extracted goes out circuit component and circuit interconnection table;
S
7Step: MASK 4 technology with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, are exported the form about circuit theory diagrams;
S
8Step: MASK 5 technology, with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, the protracting circuit schematic diagram is exported circuit theory diagrams intuitively.
Effect of the present invention:
(1) versatility.This technology is not only applicable to the integrated circuit of specific type, but is applicable to polytype integrated circuit.This shows two aspects.At first, the MASK technology can be used for handling the integrated circuit diagram of standard NMOS, PMOS and CMOS technology.Its algorithm suitably improves in addition and also can be used for handling ambipolar integrated circuit diagram.Secondly, because the MASK technical finesse is the layout data file, so it is irrelevant with method for designing, and process object can be to design the layout data that obtains automatically, or the layout data that obtains of semi-automatic design.For layout editing software systems arbitrarily, be easy to convert the treatable data input form of MASK to by interface routine.
(2) high-level efficiency.A distinguishing feature of integrated circuit diagram is that figure quantity is many, and operand is 0 (mn in the MASK technical operation
2), wherein m is a fairlead figure figurate number, and n is the number of the figure that quantity is maximum in all the other various figures, and when figure figurate number more than, it is very long just to become operation time.So the present invention has taked a series of measures: (a) adopted advanced sort algorithm, general quick sorting algorithm is 0 (nlogn) operand, here according to the integrated circuit diagram characteristics, the sort algorithm of a kind of 0 (n) operand has been proposed, wherein the number summation of n for waiting to sort; (b) designed reasonable data structure, with sequence list with collude the method that chained list combines and make operand by 0 (mn
2) reduce to 0 (mn); (c) algorithm that has adopted piecemeal to handle, the MASK technology can be specified by the user by the domain characteristics be divided into piece to domain, treats each piece respectively after computing, and program can couple together electrical information automatically, has improved the efficient of carrying out like this, and has reduced the use amount of internal memory.
(3) dirigibility.The MASK technology can produce a data in magnetic disk file in program operation process, thereby makes arithmetic operation more flexible, through checking when errorless drawing domain, can continue operation and go down; If wrong, then can revise the plate-making original, also can directly revise the intermediate result data file.The piecemeal Processing Algorithm of MASK technology has also been brought convenience to the user, and the user can select certain zone to carry out analytical review according to own needs, because one or two place's mistake is only arranged in the whole sometimes domain, the row check is just passable again in these zonules after revising.When this has save a lot of machine, has certain dirigibility.
(4) intuitive.Total image strip coordinate domain, electrical schematic diagram and the element interconnection table of MASK technology export, the inspection of can checking one against another brings a lot of convenience to the user.
(5) be easy to promote.The MASK technology is moved successfully on polytype computing machine.This technology can extend on the PC and word station hardware of various shelves levels as a kind of software systems.
(6) amphicheirality.This is one of major advantage of MASK technology: (a) on algorithm, the MASK absorption of technology thought of forward design, VLSI (very large scale integrated circuit) all designs with layering and building block idea at present, the zone of each functional block is that experience can be divided on domain, and adopting block algorithm in program is consistent with above-mentioned design philosophy; (b) on function, the MASK technology can be used for forward design and reverse analysis, during the forward design, the MASK technology is exactly a domain connectivity scrutiny program, can check whether the pairing logic connecting relation of domain correct, particularly has or not short circuit, open circuit, mistake such as redundant device and figure, during reverse analysis, the MASK technology can be the deviser electrical schematic diagram is provided, and the visual information of identification circuit is provided.They become forward and reverse resources shared in the bilateral system.
(7) data structure is reasonable.The MASK technical data is rational in infrastructure, and graphic operation is abundant in content, can do " with " (AND), NAND logical operations such as (AND NOT) and " intersecting ", " comprising " and topological analysiss such as " in be contained in ".Therefore, can expand the MASK technology, make it to have the ability of layout design rules inspection (DRC), be easy to do.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
The general diagram of the computer control system method of Fig. 1 .MASK technology;
The logical operation figure of figure in Fig. 2 .MASK technology.
(5) embodiment
With reference to the accompanying drawings the specific embodiment of the present invention is elaborated below.
Understand embodiments of the present invention for clear, at first, the gordian technique content from the layout extraction circuit diagram be described:
So-called integrated circuit diagram is the description of integrated circuit real circuits (physical entity), and real integrated circuit is that the material by specific dimensions constitutes, specifically, it is by diffusion layer, aluminum strip, polycrystalline, fairlead, silicon substrate, the physical entity of certain geometrical shape such as ion implanted region constitutes.
So-called circuit diagram is a connection layout of describing the various symbols compositions of circuit working principle, it is by resistance, electric capacity, transistor, diode, transducer, element such as amplifier and various interconnection line constitute by certain rule, the branch road in these circuit component built-up circuits, node, mesh, loop etc. connect for how much.
These two kinds of graph key of above-mentioned domain and circuit diagram are, its corresponding relation is one by one arranged between its each position, we can be referred to as mapping relations, just, a physical entity on the true integrated circuit diagram, and a symbol on must the corresponding circuits schematic diagram (as resistor symbols, the electric capacity symbol, node symbol, branch road symbol etc.).
So-called compiling or processing are confirmed above-mentioned corresponding relation to get off in essence exactly one by one.Each key element from domain raw information can be confirmed each key element in the corresponding information in the circuit theory diagrams, so, just can be from the layout extraction circuit diagram.
Below, describe integrated circuit diagram identification---Circuit Extraction (hereinafter referred to as the MASK technology) in detail with reference to Fig. 1,
Fig. 1 is the method general diagram of the computer software control system of MASK technology.For stating conveniently,, this a part of content is divided into " MASK technology ingredient " and " MASK workflow " two aspects illustrate at this.
MASK technology ingredient:
S
1Step: the raw information of in computing machine, putting into domain, the raw information of integrated circuit diagram is the source program of domain, this is a series of programs that are placed in floppy disk or the tape, and it is described to be the whole circumstances of this piece integrated circuit diagram, the source program of the object that this will discern just;
S
2Step: MASK 1 technology is that the raw information to the said integrated circuit domain compiles, and the result sends into S compiling
3
S
3Step: the disk file 1 of storage intermediate result is the result of the above-mentioned compiling of storage, and this compiling result exports S to
4And S
5
S
4Step: MASK 2 technology are accepted the information of the compiling result of storage in the above-mentioned disk file 1, thereby are drawn out integrated circuit diagram, promptly by original plate-making data, draw out the usefulness of colored domain for analysis;
S
5Step: MASK 3 technology, the compiling result's of storage information from above-mentioned disk file 1 through graphic operation, extracts circuit component and circuit interconnection table with the domain source program;
S
6Step: the disk file 2 of storage intermediate result is the information that the storage said extracted goes out circuit component and circuit interconnection table, and this information outputs to S
7And S
8
S
7Step: MASK 4 technology with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, are exported the form about circuit theory diagrams;
S
8Step: MASK 5, with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, the protracting circuit schematic diagram is exported circuit theory diagrams intuitively.
From S
1Arrive S
8, be to have reached circuit diagram information step by step from domain information, that is, reached the purpose of domain identification of the present invention.
MASK workflow (being the MASK 1 to MASK 5 among Fig. 1)
(1) MASK 1 is an integrated circuit diagram raw information technique of compiling among Fig. 1, and MASK 1 can allow the user import the integrated circuit plate-making source program of specific format, also can adopt data layout that relevant manufacturer requires, integrated circuit plate-making software dictates;
(2) MASK 2 is the technology of drawing integrated circuit diagram, can draw the usefulness of colored domain for analysis by former plate-making data;
(3) MASK 3 is circuit component and circuit interconnection table extractive technique, the raw information of domain is through compiling back input disk file 1, be that the intermediate result that forms in 3 pairs of above-mentioned disk files 1 of available MASK is handled, by the logical operation of figure, obtain the interconnect information of circuit component table and circuit component at this point.
(4) MASK 4 is circuit component and net sheet format export technique, this software control system is output as a form, its information comprises: transistor number, the node number of each utmost point of pipe in circuit, the breadth length ratio of each pipe, the physical address of each transistor on domain had this table, and the designer just can determine the circuit theory diagrams of chip layout easily;
(5) MASK 5 technology are technology of computer automatic drafting circuit theory diagrams, this software control system can be according to the circuit component net table that extracts, according to its interconnection rule, rationally arrange out each electronic circuit, according to node number each circuit component is coupled together again, for the usefulness of analysis, thereby make deviser's structure of sensing circuit intuitively.
Realize the domain of integrated circuit below with the computer software control system of MASK technology---examples of implementation of circuit extraction.
The input of MASK is the information about domain structure that obtains from integrated circuit (IC) chip, and it can be from the plate-making data file of ready-made integrated circuit (IC) chip.MASK 1 major function is that the input file that the user provides is compiled, with the new intermediate result disk file of direct formation.The colored domain of MASK 2 be divided into black, redness, blueness, green four kinds, black represent diffusion layer, the red aluminum strip of represent, blueness is represented polycrystalline, the blockage of green is represented fairlead.Simultaneously, on the figure of polycrystalline, specially put on coordinate, done two effects like this: the one, be convenient to before integrated circuit is made formal discriminance analysis, carry out trial inspection; The 2nd, for being provided, next step checks the usefulness of the position of element and node by physical address.MASK 3 need obtain the interconnect information of circuit component table and circuit component by means of logical operation as the subsystem that extracts circuit component and circuit component interconnection list.
Referring to Fig. 2 is the logical operation synoptic diagram of figure in the MASK technology, as the A that is illustrated as among the 2a, be illustrated as B among Fig. 2 b, then among the 2c be illustrated as A and B " with " result's (being the result of AANDB), and the result who is illustrated as AAND NOTB NAND among Fig. 2 d.For N ditch Si-gate MOS technology, the depletion mode transistor T in the domain
D, butt hole G
C, enhancement transistor T
EBe respectively:
T
D＝Gp·AND·G
D·AND·Gi
G
C＝Gp·AND·G
D·AND·Gr
T
E＝Gp·AND·G
D·AND?NOT·T
D·AND?NOT·Gc
Wherein: Gp is a polycrystal pattern; G
DBe scatter diagram; Gi is depletion type ion injection figure; Gr is the lead-in wire hole pattern.
On this basis, by the form of MASK 4 subsystems output, its information comprises: relevant transistorized numbering; The node number of each utmost point of transistor in circuit; Each relevant transistorized breadth length ratio; Each relevant transistor physical address on domain obviously, can identify and the corresponding circuit theory diagrams of domain thus.MASK5 of the present invention is the subsystem of automatic blueprint drawing, and its function is that the net table is converted to circuit theory diagrams, to demonstrate the intuitive of the pairing circuit structure of integrated circuit diagram that is identified.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (5)
1, a kind of domain recognition methods of integrated circuit, the method by the identification of computer software control integrated circuit domain is characterized in that described domain recognition methods comprises:
S
1Step: the raw information of in computing machine, putting into domain, the raw information of integrated circuit diagram is the source program of domain, this is a series of programs that are placed in floppy disk or the tape, and it is described to be the whole circumstances of this piece integrated circuit diagram, the source program of the object that this will discern just;
S
2Step: MASK 1 technology is that the raw information to the said integrated circuit domain compiles;
S
3Step: the disk file 1 of storage intermediate result is the result of above-mentioned MASK 1 compiling of storage;
S
4Step: MASK 2 technology are accepted the information of the compiling result of storage in the above-mentioned disk file 1, thereby are drawn out integrated circuit diagram, promptly by original plate-making data, draw out the usefulness of colored domain for analysis;
S
5Step: MASK 3 technology, the compiling result's of storage information from above-mentioned disk file 1 through graphic operation, extracts circuit component and circuit interconnection table with the domain source program;
S
6Step: the disk file 2 of storage intermediate result is the information that the storage said extracted goes out circuit component and circuit interconnection table;
S
7Step: MASK 4 technology with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, are exported the form about circuit theory diagrams;
S
8Step: MASK 5 technology, with the information that extracts circuit component and circuit interconnection table of storage in the above-mentioned disk file 2, the protracting circuit schematic diagram is exported circuit theory diagrams intuitively.
2, the domain recognition methods of integrated circuit as claimed in claim 1, it is characterized in that described MASK1 technology is the integrated circuit plate-making source program that the user imports specific format, or adopt data layout that relevant manufacturer requires, integrated circuit plate-making software dictates.
3, the domain recognition methods of integrated circuit as claimed in claim 1 is characterized in that the graphic operation in described MASK 3 technology is logical operation.
4, the domain recognition methods of integrated circuit as claimed in claim 1, it is characterized in that the form of described MASK 4 technology exports about circuit theory diagrams, its information comprises: transistor number, the node number of each utmost point of pipe in circuit, the breadth length ratio of each pipe, the physical address of each transistor on domain, this form can be determined the circuit theory diagrams of chip layout easily.
5, the domain recognition methods of integrated circuit as claimed in claim 1, it is characterized in that the form of described MASK 5 technology according to the described circuit theory diagrams that extract, according to its interconnection rule, rationally arrange out each electronic circuit, according to node number each circuit component is coupled together again, for the usefulness of analysis, thus the structure of sensing circuit intuitively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031152422A CN1521622A (en) | 2003-01-29 | 2003-01-29 | Recognition method for artwork of integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031152422A CN1521622A (en) | 2003-01-29 | 2003-01-29 | Recognition method for artwork of integrated circuit |
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Cited By (12)
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| CN100433023C (en) * | 2005-12-28 | 2008-11-12 | 华为技术有限公司 | Method and system for drawing schematic diagram design document |
| CN1892661B (en) * | 2005-07-06 | 2011-07-27 | 北京华大九天软件有限公司 | Algorithm based on equivalence class to resolve short-circuit problem in IILVS |
| CN102314530A (en) * | 2010-07-02 | 2012-01-11 | 北京华大九天软件有限公司 | Novel interactive type hierarchical short circuit tracing and dynamic debugging method |
| CN102339342A (en) * | 2010-07-27 | 2012-02-01 | 中国科学院微电子研究所 | Quick materialization method of parameterized device unit |
| WO2012089011A1 (en) * | 2010-12-28 | 2012-07-05 | 炬力集成电路设计有限公司 | Semiconductor device, chip and method for modifying bit data |
| CN101770529B (en) * | 2008-12-31 | 2012-10-03 | 中芯国际集成电路制造(上海)有限公司 | Method for designing analytic layout |
| CN103425812A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Semiconductor device design system and method of using the same |
| CN105631118A (en) * | 2015-12-25 | 2016-06-01 | 深圳市同创国芯电子有限公司 | Programmable logic device graph drawing method and device |
| CN108804724A (en) * | 2017-04-27 | 2018-11-13 | 瑞昱半导体股份有限公司 | The discrimination method of circuit code method and circuit framework |
| CN109829474A (en) * | 2018-12-27 | 2019-05-31 | 北京邮电大学 | A kind of circuit diagram recognition methods |
| CN112347719A (en) * | 2020-11-05 | 2021-02-09 | 深圳市华星光电半导体显示技术有限公司 | Design drawing processing method and device, computer equipment and storage medium |
| CN116736061A (en) * | 2023-05-09 | 2023-09-12 | 珠海妙存科技有限公司 | Triode matching precision detection method, controller and storage medium |
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- 2003-01-29 CN CNA031152422A patent/CN1521622A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1892661B (en) * | 2005-07-06 | 2011-07-27 | 北京华大九天软件有限公司 | Algorithm based on equivalence class to resolve short-circuit problem in IILVS |
| CN100433023C (en) * | 2005-12-28 | 2008-11-12 | 华为技术有限公司 | Method and system for drawing schematic diagram design document |
| CN101770529B (en) * | 2008-12-31 | 2012-10-03 | 中芯国际集成电路制造(上海)有限公司 | Method for designing analytic layout |
| CN102314530B (en) * | 2010-07-02 | 2014-02-05 | 北京华大九天软件有限公司 | Interactive type hierarchical short circuit tracing and dynamic debugging method |
| CN102314530A (en) * | 2010-07-02 | 2012-01-11 | 北京华大九天软件有限公司 | Novel interactive type hierarchical short circuit tracing and dynamic debugging method |
| CN102339342A (en) * | 2010-07-27 | 2012-02-01 | 中国科学院微电子研究所 | Quick materialization method of parameterized device unit |
| CN102339342B (en) * | 2010-07-27 | 2013-06-05 | 中国科学院微电子研究所 | Quick materialization method of parameterized device unit |
| WO2012089011A1 (en) * | 2010-12-28 | 2012-07-05 | 炬力集成电路设计有限公司 | Semiconductor device, chip and method for modifying bit data |
| CN103425812A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Semiconductor device design system and method of using the same |
| CN105631118A (en) * | 2015-12-25 | 2016-06-01 | 深圳市同创国芯电子有限公司 | Programmable logic device graph drawing method and device |
| CN108804724A (en) * | 2017-04-27 | 2018-11-13 | 瑞昱半导体股份有限公司 | The discrimination method of circuit code method and circuit framework |
| CN108804724B (en) * | 2017-04-27 | 2021-12-10 | 瑞昱半导体股份有限公司 | Circuit coding method and circuit architecture identification method |
| CN109829474A (en) * | 2018-12-27 | 2019-05-31 | 北京邮电大学 | A kind of circuit diagram recognition methods |
| CN112347719A (en) * | 2020-11-05 | 2021-02-09 | 深圳市华星光电半导体显示技术有限公司 | Design drawing processing method and device, computer equipment and storage medium |
| CN112347719B (en) * | 2020-11-05 | 2023-10-13 | 深圳市华星光电半导体显示技术有限公司 | Design drawing processing method and device, computer equipment and storage medium |
| CN116736061A (en) * | 2023-05-09 | 2023-09-12 | 珠海妙存科技有限公司 | Triode matching precision detection method, controller and storage medium |
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