CN112347719B

CN112347719B - Design drawing processing method and device, computer equipment and storage medium

Info

Publication number: CN112347719B
Application number: CN202011220134.6A
Authority: CN
Inventors: 吕波
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-11-05
Filing date: 2020-11-05
Publication date: 2023-10-13
Anticipated expiration: 2040-11-05
Also published as: CN112347719A

Abstract

The embodiment of the application discloses a design drawing processing method, a device, computer equipment and a storage medium, and relates to the technical field of data processing. The method comprises the following steps: acquiring a first design diagram and a second design diagram, wherein the first design diagram is one of a circuit schematic diagram and a physical layout, and the second design diagram is the other of the circuit schematic diagram and the physical layout; generating a target design drawing corresponding to the first design drawing according to the first design drawing; and carrying out consistency comparison on the second design drawing and the target design drawing to obtain a design drawing comparison result. Therefore, the target design diagram is automatically generated according to the first design diagram, the efficiency and the accuracy of obtaining the target design diagram are improved, and the second design diagram is compared with the generated target design diagram, so that the consistency of the second design diagram and the first design diagram is further determined, and the efficiency and the accuracy of determining the consistency of the first design diagram and the second design diagram are improved.

Description

Design drawing processing method and device, computer equipment and storage medium

Technical Field

The present application relates to the field of display technologies, and in particular, to a method and apparatus for processing a design drawing, a computer device, and a storage medium.

Background

GOA, gate Driver on Array (Array substrate row driving) technology, namely, a gate driving circuit is manufactured on a substrate by using the existing Array process of a liquid crystal display panel, so as to realize a progressive scanning driving mode of scanning lines. Currently, GOA technology has been widely used in panel design.

The GOA technology corresponds to a GOA circuit, one GOA circuit comprising a plurality of cascaded GOA cells. In the prior art, after a designer obtains a GOA circuit schematic diagram, it is generally necessary to manually draw a physical layout (layout diagram) corresponding to the GOA circuit schematic diagram according to the GOA circuit schematic diagram; or after the physical layout is obtained, manually drawing a GOA circuit schematic according to the physical layout. It will be appreciated that the GOA circuit schematic and the physical layout are one type of design. Whether the physical layout corresponding to the GOA circuit is manually drawn according to the GOA circuit schematic diagram or the corresponding GOA circuit schematic diagram is manually drawn according to the physical layout, the efficiency of obtaining the corresponding design diagram is low, and the accuracy is not guaranteed.

Disclosure of Invention

The embodiment of the application provides a design drawing processing method, a device, computer equipment and a storage medium, which can improve the efficiency and accuracy of obtaining a corresponding design drawing.

The embodiment of the application provides a design drawing processing method, which comprises the following steps:

acquiring a first design diagram and a second design diagram, wherein the first design diagram is one of a circuit schematic diagram and a physical layout, and the second design diagram is the other of the circuit schematic diagram and the physical layout;

generating a target design drawing corresponding to the first design drawing according to the first design drawing;

and carrying out consistency comparison on the second design drawing and the target design drawing to obtain a design drawing comparison result.

The embodiment of the application also provides a device for processing the design drawing, which comprises the following steps:

the device comprises an acquisition unit, a control unit and a control unit, wherein the acquisition unit is used for acquiring a first design drawing and a second design drawing, the first design drawing is one of a circuit schematic diagram and a physical layout, and the second design drawing is the other of the circuit schematic diagram and the physical layout;

the generating unit is used for generating a target design drawing corresponding to the first design drawing according to the first design drawing;

and the comparison unit is used for carrying out consistency comparison on the second design drawing and the target design drawing so as to obtain a design drawing comparison result.

The embodiment of the application also provides a computer device, which comprises: one or more processors; a memory; and one or more computer programs, wherein the processor is coupled to the memory, the one or more computer programs being stored in the memory and configured to perform the design drawing processing method described above by the processor.

The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, the computer program being loaded by a processor to execute the above-mentioned design drawing processing method.

The embodiment of the application provides a design drawing processing method, a device and computer equipment, wherein a first design drawing and a second design drawing are acquired, the first design drawing is one of a circuit schematic diagram and a physical layout, and the second design drawing is the other of the circuit schematic diagram and the physical layout; generating a target design drawing corresponding to the first design drawing according to the first design drawing; and carrying out consistency comparison on the second design drawing and the target design drawing to obtain a design drawing comparison result. Therefore, the target design diagram is automatically generated according to the first design diagram, the efficiency and the accuracy of obtaining the target design diagram are improved, and the second design diagram is compared with the generated target design diagram, so that the consistency of the second design diagram and the first design diagram is further determined, and the efficiency and the accuracy of determining the consistency of the first design diagram and the second design diagram are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a design diagram processing method according to an embodiment of the present application;

FIG. 2 is a schematic sub-flowchart of a design diagram processing method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present application;

FIG. 4 is a schematic sub-flowchart of a design diagram processing method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another sub-flowchart of a method for processing a design chart according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another sub-flowchart of a method for processing a design chart according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another sub-flowchart of a design diagram processing method according to an embodiment of the present application;

FIG. 8 is a schematic block diagram of a schematic diagram of a device for processing a design diagram provided by an embodiment of the present application;

FIG. 9 is a schematic block diagram of a graph generation unit provided by an embodiment of the present application;

FIG. 10 is a schematic block diagram of an identification unit provided by an embodiment of the present application;

fig. 11 is a schematic block diagram of a computer device provided by an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. In addition, the terms "first" and "second" are used to distinguish a plurality of elements from one another. For example, a first constraint may be referred to as a second constraint, and similarly, a second constraint may be referred to as a first constraint, without departing from the scope of the present application. The first constraint and the second constraint are both constraints, but they are not the same constraint.

In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

The embodiment of the application provides a design drawing processing method, a device, computer equipment and a storage medium. The design drawing processing method is operated in the computer equipment, such as an application program in the computer equipment, wherein the application program can be an electronic equipment automation application program (Electronic design automation, EDA), and the design drawing processing method can be understood as a modification scheme of the EDA application program on the computer equipment. The computer device may be a server or a terminal, including a desktop, smart phone, portable computer, palm computer (Personal Digital Assistant, PDA), wearable device, robot, embedded device, etc. The following describes the method, apparatus, computer device and storage medium for processing the design drawing in detail.

Fig. 1 is a schematic flow chart of a design diagram processing method according to an embodiment of the present application. As shown in fig. 1, the method comprises the following specific procedures:

101, acquiring a first design diagram and a second design diagram, wherein the first design diagram is one of a circuit schematic diagram and a physical layout, and the second design diagram is the other of the circuit schematic diagram and the physical layout.

There is a correspondence between the schematic circuit diagram and the physical layout. If the first design drawing is a circuit schematic diagram, the second design drawing is a physical layout; if the first design drawing is a physical layout, the second design drawing is a circuit schematic drawing. The schematic circuit diagram may be a GOA schematic circuit diagram, or may be another schematic circuit diagram.

There may be various ways of obtaining the first design drawing and/or the second design drawing.

The first design drawing and/or the second design drawing are directly obtained. It will be appreciated that the first and/or second design drawing may already exist in the computer device or may be obtained from other devices. Thus, the first design drawing and/or the second design drawing are directly acquired. Further, the first design drawing and/or the second design drawing may be directly obtained by means of import. If the import control on the corresponding import interface in the computer equipment is triggered, the import interface is called by the import control to import the first design drawing and/or the second design drawing.

By drawing the corresponding first and/or second design drawing in the computer device. The corresponding drawing interface is invoked, as on a corresponding drawing interface in a computer device, to draw the first design drawing and/or the second design drawing. And acquiring the drawn first design drawing and/or second design drawing.

And inputting components corresponding to the first design drawing and/or the second design drawing and association relations corresponding to the components into the computer equipment to generate the first design drawing and/or the second design drawing. It can be understood that, on the corresponding input interface in the computer device, the components corresponding to the first design drawing and/or the second design drawing and the association relation corresponding to the components are input, and the first design drawing and/or the second design drawing is automatically generated according to the input components and association relation. The generated first and/or second design drawings are obtained.

It will be appreciated that the first and/or second plans may be obtained in any of the manners described above, as well as in other manners.

102, generating a target design drawing corresponding to the first design drawing according to the first design drawing.

And automatically generating a target design diagram corresponding to the first design diagram, thereby improving the efficiency and the accuracy of generating the target design diagram corresponding to the first design diagram.

Further, step 102 includes: identifying a first design drawing to obtain each component in the first design drawing and the association relation among the components; and generating a target design diagram corresponding to the first design diagram according to each component and the association relation among the components.

The components comprise a signal input end, a signal output end, a thin film transistor, a storage capacitor and the like. If the design diagram is a design diagram corresponding to the GOA circuit, the signal input terminal further includes a clock signal input terminal and the like.

If the first design drawing is a circuit schematic drawing, the second design drawing is a physical layout, and the target design drawing is a target physical layout. Step 102 can be understood as: and generating a target physical layout corresponding to the circuit schematic according to the circuit schematic. Further, step 102 includes: identifying a circuit schematic diagram to obtain components in the circuit schematic diagram and association relations among the components; and generating a target physical layout corresponding to the circuit schematic according to each component and the association relation among the components.

The schematic circuit diagram includes various device symbols, connection symbols and the like. And identifying the schematic circuit diagram, namely identifying various device symbols and connection symbols to obtain each component in the schematic circuit diagram and the association relation among the components. It is understood that the correspondence between the preset device symbols and the components and the correspondence between the preset connection symbols and the association relationships (connection relationships) are stored in the computer device. As shown in table 1, the correspondence between the preset part of the device symbols and the components and the correspondence between the preset part of the connection symbols and the connection relationships are shown. It will be appreciated that a device may correspond to a plurality of device symbols and a connection relationship may correspond to a plurality of connection symbols. The correspondence relationship described in table 1 is only for understanding the content in the embodiment of the present application, and does not limit the content related to the embodiment of the present application.

Table 1 correspondence between preset partial device symbols and components, correspondence between preset partial connection symbols and connection relationships

The schematic circuit diagram can be identified according to the corresponding relation described in table 1, namely, the device symbol and the connection symbol in the schematic circuit diagram are identified, and the corresponding components and the association relation among the components are determined according to the device symbol and the connection symbol in the schematic circuit diagram.

As shown in fig. 2, the steps of generating the target physical layout corresponding to the schematic circuit diagram according to each component and the association relation between components include the following steps 201 to 203.

201, determining the number of levels of the target physical layout, physical components to be generated in each level and connection relations among the physical components to be generated in each level according to each component and the association relations among the components.

The number of levels of the target physical layout can be determined according to a preset level number determining rule. The preset hierarchical number determination rule may be as follows: if the components in the circuit schematic diagram are detected to comprise storage capacitors, the number of the layers is at least two; if the components in the circuit schematic diagram are detected to comprise the thin film transistors, the number of the layers is at least two; or other more complex hierarchical quantity determination rules. If the number of the target physical layout layers is determined to be two layers.

The step of determining the physical component to be generated in each level according to each component and the association relation among the components comprises the following steps: and determining the physical components to be generated corresponding to each level according to each component and the association relation among the components, and determining the physical components to be generated corresponding to each level. And if the physical component to be generated corresponding to each level is determined to comprise a first metal layer and a second metal layer.

Further, the schematic circuit diagram may include a GOA schematic circuit diagram.

Fig. 3 is a schematic diagram of a GOA circuit, in which the resolution of a display panel in an 8K product is 7680x4320, and thus 7680 data lines, 4320 scan lines are included, as an example. The GOA circuit comprises a plurality of cascaded GOA units, wherein the GOA units sequentially comprise a plurality of effective GOA units and a plurality of redundant GOA units from top to bottom, wherein the effective GOA units are denoted by 'GOA units', and the redundant GOA units are denoted by 'Dummy GOA units'. The number of the redundant GOA units may be 6, 12 clock signal lines CK1 to CK12 and 6 redundant GOA units Dummy GOA Unit 1 to Dummy GOA Unit 6, 4320 scan lines are denoted by G1 to G4320, respectively.

Described above is an overall GOA circuit schematic, with a corresponding circuit diagram (not shown in fig. 3) included in each cascaded GOA cell in the GOA circuit schematic. The circuit diagram in each GOA unit comprises a plurality of thin film transistors, at least one storage capacitor, a clock signal input end, a high potential signal input end, a low potential signal input end and other components, and the association relation among the components. Taking a clock signal input end as an example, each GOA unit comprises a clock signal input end, a clock signal line is connected with the clock signal input end, a clock signal is input to drive the GOA unit to work, and a grid driving signal is output to a corresponding scanning line. The circuit diagram in each GOA unit is referred to the corresponding circuit diagram in the prior art and will not be described in detail here.

As shown in fig. 4, if the components include a scanning signal input terminal, the physical component to be generated in each level includes a first metal layer, and the step of determining the physical component to be generated in each level according to each component and the association relationship between components includes steps 301 to 304.

301, the number of scanning signal input terminals and the number of thin film transistors in each GOA unit are obtained.

The number of scan signal inputs is obtained, for example, the number of scan signal inputs obtained is 4320. Typically, the circuitry in each GOA unit is uniform to facilitate uniform processing. If the circuits in each GOA unit are identical, the number of thin film transistors in one GOA unit is acquired, and the number of thin film transistors in the one GOA unit is determined as the number of thin film transistors in each GOA unit. And if the numbers of the thin film transistors in the GOA units are inconsistent, sequentially acquiring the numbers of the thin film transistors in the GOA units. In the embodiment of the present application, circuit uniformity in each GOA unit is taken as an example for illustration.

And 302, determining a physical component to be generated in the first metal layer according to the scanning signal input end and the thin film transistor, wherein the physical component to be generated comprises a scanning line to be generated and a grid electrode of the thin film transistor.

And determining a scanning line to be generated in the first metal layer according to the scanning signal input end, and determining a thin film transistor grid electrode in the first metal layer according to the thin film transistor.

303, determining the number of scanning lines to be generated in the first metal layer according to the number of scanning signal input ends.

The number of scan signal inputs is identical to the number of scan lines to be generated, and if the number of scan signal inputs is 4320, the number of scan lines to be generated is 4320.

304, determining the number of thin film transistor gates in the first metal layer according to the number of the scanning signal input ends and the number of the thin film transistors in each GOA unit.

More specifically, the number of thin film transistor gates in the first metal layer is determined according to the number of scan signal inputs, the number of redundant GOA cells, and the number of thin film transistors in each GOA cell.

The redundant GOA cells and the active GOA cells are set to be identical from the process point of view, and thus the number of thin film transistor gates in each redundant GOA cell is the same as that in each active GOA cell. Since the driving signal output ends of the effective GOA units are sequentially connected with the scanning lines and are in one-to-one correspondence, the number of the scanning signal input ends is the same as that of the effective GOA units. I.e. the number of thin film transistor gates in the first metal layer is determined based on the number of active GOA cells, the number of redundant GOA cells and the number of thin film transistors in each GOA cell. If the thin film transistors in each GOA unit are all single gates, the number of thin film transistor gates in the first metal layer is the sum of the number of effective GOA units and the number of redundant GOA units, and then multiplied by the number of thin film transistors in each GOA unit. If there are double gates for the thin film transistors in each GOA cell, the number of thin film transistor gates in the first metal layer is the sum of the number of active GOA cells and the number of redundant GOA cells, multiplied by (the sum of the number of thin film transistors in each GOA cell and n). Where n refers to the number of double-gate thin film transistors.

The order of step 303 and step 304 is not limited.

In this way, the physical components to be generated in the first metal layer are determined according to steps 301 to 304, wherein the physical components to be generated in the first metal layer include the scan lines to be generated and the thin film transistor gates, and the corresponding numbers.

As shown in fig. 5, if the components include a clock signal input end and a data signal input end, the to-be-generated physical component corresponding to each level of layers includes a second metal layer, and the step of determining the to-be-generated physical component in each level according to each component and the association relationship between components includes steps 401 to 404.

The number of clock signal inputs and the number of data signal inputs are acquired 401.

Wherein each GOA unit (including the active GOA unit and the redundant GOA unit) has a clock signal input, and therefore, the number of clock signal inputs is the same as the number of GOA units. The number of clock signal inputs may be obtained, or the number of GOA units may be obtained. In addition to the number of clock signal inputs, the number of data signal inputs is also obtained.

And 402, determining a physical component to be generated in the second metal layer according to the clock signal input end, wherein the physical component to be generated comprises the clock signal end to be generated, and determining the number of the clock signal ends to be generated according to the number of the clock signal input ends.

And determining clock signal ends to be generated in the second metal layer according to the clock signal input ends, and determining the number of the clock signal ends to be generated according to the number of the clock signal input ends.

403, determining a physical component to be generated in the second metal layer according to the data signal input end and the grid electrode of the thin film transistor, wherein the physical component to be generated also comprises a data line to be generated, a source electrode and a drain electrode of the thin film transistor.

And determining a data line to be generated in the second metal layer according to the data signal input end, and determining a source electrode and a drain electrode of the thin film transistor in the second metal layer according to the grid electrode of the thin film transistor.

404, determining the number of data lines to be generated according to the number of data signal input ends, and determining the number of thin film transistor sources and drains according to the number of thin film transistor gates.

The number of data signal input terminals is the same as the number of data lines to be generated, and the number of thin film transistor gates is the same as the number of thin film transistor sources and drains.

In this way, the physical components to be generated in the second metal layer are determined according to steps 401 to 404, wherein the physical components to be generated in the second metal layer include the data line to be generated, the source electrode and the drain electrode of the thin film transistor, and the corresponding numbers respectively.

As shown in fig. 6, if the component includes a storage capacitor, the physical member to be generated corresponding to each level of layer includes a first metal layer and a second metal layer, and the step of determining the physical member to be generated in each level according to each component and the association relationship between components includes steps 501 to 503.

501, the number of storage capacitors in each GOA unit is obtained.

Since the circuits in all the GOA units are identical, the number of storage capacitors in one GOA unit is acquired, and the number of storage capacitors is determined as the number of storage capacitors in each GOA unit. It will be appreciated that if there is an inconsistency in the circuits in the GOA units, the number of storage capacitors in each GOA unit is obtained.

502, determining a physical component to be generated in the first metal layer according to the storage capacitance, wherein the physical component to be generated further comprises a first polar plate of the storage capacitance, and determining the number of the first polar plate of the storage capacitance according to the number of the storage capacitance in each GOA unit and the number of the scanning signal input ends.

And determining a first polar plate of the storage capacitor in the first metal layer according to the storage capacitor. And determining the number of the first polar plates of the storage capacitor according to the number of the storage capacitors in each GOA unit and the number of the scanning signal input ends. Specifically, the number of the first polar plates of the storage capacitor is determined according to the number of the storage capacitors in each GOA unit, the number of the scanning signal input ends and the number of the redundant GOA units. The number of the first polar plates of the storage capacitor is the sum of the number of the storage capacitors in each GOA unit multiplied by the number of the scanning signal input ends and the number of the redundant GOA units. The number of the scanning signal input ends is the same as the number of the effective GOA units, namely the sum of the number of the scanning signal input ends and the number of the redundant GOA units is the number of all the GOA units, namely the number of the first polar plates of the storage capacitors is the number of the storage capacitors in each GOA unit multiplied by the number of all the GOA units.

503, determining a physical component to be generated in the second metal layer according to the storage capacitor, wherein the physical component to be generated further comprises a second polar plate of the storage capacitor, and determining the number of the second polar plates of the storage capacitor according to the number of the first polar plates of the storage capacitor.

And determining a storage capacitor second polar plate in the second metal layer according to the storage capacitor. The storage capacitor comprises two polar plates, a first polar plate of the storage capacitor and a second polar plate of the storage capacitor, and therefore the number of the second polar plate of the storage capacitor is determined according to the number of the first polar plate of the storage capacitor.

In this way, the to-be-generated physical device further included in the first metal layer and the second metal layer is determined through steps 501 to 503, where the to-be-generated physical device further includes a storage capacitor first polar plate in the first metal layer and a storage capacitor second polar plate in the second metal layer, and corresponding numbers.

Other devices included in the GOA circuit may also be sequentially generated. Such as a gate insulating layer of a thin film transistor over a first metal layer, i.e., over a thin film transistor gate, etc.

It should be noted that the above description is only one embodiment. In other embodiments, the corresponding overall physical layout may also be generated according to an overall GOA circuit schematic diagram, and/or the physical layout corresponding to each GOA unit may be generated according to the circuit schematic diagram of each GOA unit. Thus, the physical layout corresponding to the GOA circuit schematic diagram can be the physical layout corresponding to the whole body or the physical layout corresponding to a single GOA unit. In the corresponding overall physical layout, the individual GOA units may be present as a module, or may be simply understood as a black box.

202, generating a layer structure corresponding to each level according to a preset generation rule corresponding to each level and the physical component to be generated.

The preset generation rules corresponding to the layers comprise preset generation rules corresponding to each layer and preset generation rules corresponding to the layers. Including differences in color of the physical components to be generated between adjacent levels.

If the physical component to be generated is the first metal layer, the corresponding preset generation rule in the first metal layer may include: the color of the physical component to be generated in the first metal layer is color 1, the width of the scanning lines is width 1 (e.g. 5-9 um), the interval between the scanning lines is distance 1, the size of the first polar plate of the storage capacitor is a x b, the size of the grid electrode of the thin film transistor is c x d, and the like. The position and the placement direction of the scanning line, such as the transverse direction, the position and the placement direction of the first polar plate of the storage capacitor, the position and the direction of the grid electrode of the thin film transistor, and the like.

If the physical component to be generated is the second metal layer, the corresponding preset generation rule in the second metal layer may include: the color of the physical component to be generated in the second layer is color 2, the width of the data lines is width 2 (e.g. 5-9 um), the interval between the data lines is distance 2, the size of the second polar plate of the storage capacitor is a×b, the sizes of the source electrode and the drain electrode of the thin film transistor, etc. The position and the placement direction of the data line, such as the longitudinal direction, the position and the placement direction of the first polar plate of the storage capacitor, the position and the placement direction of the source electrode and the drain electrode of the thin film transistor, and the like.

The corresponding preset generation rules among the layers comprise: the placing direction of the scanning lines in the first metal layer is perpendicular to the placing direction of the data lines in the second metal layer; the storage capacitor first polar plate in the first metal layer corresponds to the storage capacitor second polar plate in the second metal layer in position, the placement directions are the same, and meanwhile the size of the storage capacitor first polar plate is the same as that of the storage capacitor second polar plate; the thin film transistor gate in the first metal layer corresponds to the location of the source drain of the thin film transistor in the second metal layer, and so on.

It should be noted that the preset generation rules corresponding to the levels shown above are merely illustrative, and may be set to be different according to the specific schematic circuit diagram.

Because each level is correspondingly provided with a preset generation rule, generating a layer structure corresponding to each level according to the preset generation rule and the physical component to be generated. The layer structure of the second metal layer includes a plurality of data lines (orthographic projection of the data lines on the first metal layer is perpendicular to the scan lines), source and drain electrodes corresponding to the gate electrode of the thin film transistor, and a storage capacitor second plate corresponding to the storage capacitor first plate.

And 203, connecting the layer structures corresponding to the layers according to the connection relation to generate a target physical layout corresponding to the circuit schematic diagram.

According to the connection relation between the physical components to be generated, connecting the layer structures corresponding to each level, for example, the connection relation between the physical components to be generated comprises: one end of the storage capacitor is connected with the drain electrode of one thin film transistor, and the other end of the storage capacitor is connected with the grid electrode of the other thin film transistor. Correspondingly, the second polar plate of the storage capacitor in the second metal layer is connected with the drain electrode of one thin film transistor in the second metal layer, and the first polar plate of the storage capacitor in the first metal layer is connected with the grid electrode of the other thin film transistor in the first metal layer. The other layer mechanisms are correspondingly connected.

When the layer structures corresponding to the layers are connected, the connection can be performed according to the rule of shortest routing, so that waste of resources is avoided during actual production.

And connecting the layer structures corresponding to the layers to generate a target physical layout corresponding to the circuit schematic diagram.

The above parts realize that the target physical layout corresponding to the circuit schematic diagram is generated according to the circuit schematic diagram. It should be noted that the target physical layout corresponding to the generated schematic circuit diagram may be accomplished in other manners.

If the first design drawing is a physical layout, the second design drawing is a circuit schematic diagram, and the target design drawing is a target circuit schematic diagram. Step 102 can be understood as: and generating a target circuit schematic diagram corresponding to the physical layout according to the physical layout. Further, step 102 includes: identifying a physical layout to obtain each component in the physical layout and the association relation among the components; and generating a target circuit schematic diagram corresponding to the physical layout according to each component and the association relation among the components.

As shown in fig. 7, the step of identifying the physical layout to obtain each component in the physical layout and the association relationship between the components includes the following steps:

601, obtaining a layer structure corresponding to each level of the physical layout.

And acquiring a layer structure corresponding to each level of the physical layout, namely acquiring a layer structure corresponding to each level in the physical layout, such as acquiring a layer structure of a first metal layer, a layer structure of a second metal layer and the like.

602, identifying the corresponding physical components and the connection relation between the physical components in the layer structure corresponding to each level according to the preset generation rule corresponding to each level.

The preset generation rule corresponding to each level is the preset generation rule mentioned above. And generating a layer structure corresponding to each level according to the preset generation rule and the physical component to be generated. And identifying the corresponding physical components and the connection relations between the physical components in the layer structure corresponding to each level by utilizing the preset generation rules corresponding to each level. It can be simply understood that B is generated according to a, where a is obtained according to B, and the preset generation rule includes a correspondence between a and B.

If the color of the physical component corresponding to a certain level is identified as color 1, determining that the physical component corresponding to the level is a first metal layer; if a certain structure in the first metal layer is identified as a x b, determining that a physical component corresponding to the structure is a storage capacitor first polar plate in the first metal layer; if the size of a certain structure in the first metal layer is identified as c×d, determining that a physical component corresponding to the structure is a thin film transistor gate; if the width of the plurality of lines is identified as width 1 and the interval is distance 1, the physical member corresponding to the plurality of lines is determined to be a scanning line or the like.

If the color of the physical component corresponding to a certain level is identified as color 2, determining that the physical component corresponding to the level is a second metal layer; if a certain structure in the second metal layer is identified as a x b, determining that a physical component corresponding to the structure is a storage capacitor second polar plate in the second metal layer; if the size of a certain structure in the second metal layer is identified as m x n, determining that a physical component corresponding to the structure is a source electrode and a drain electrode of the thin film transistor; if the width of the plurality of lines is identified as width 2 and the interval is distance 2, the physical component corresponding to the plurality of lines is determined to be a data line or the like.

The physical components corresponding to each level can be obtained in the above manner.

If the fact that a connecting wire is connected between a drain electrode of a thin film transistor in the second metal layer and the second plate of the storage capacitor is identified, determining that an association relationship exists between the drain electrode of the thin film transistor and the second plate of the storage capacitor. And the like, so as to obtain the connection relation between the physical components corresponding to each level.

603, determining each component and the association relation between each component according to the connection relation between the physical components.

If the physical component is determined to respectively comprise a storage capacitor first polar plate in the first metal layer and a storage capacitor second polar plate in the second metal layer, determining that the component corresponding to the physical component is a storage capacitor; if it is determined that the physical component includes a thin film transistor gate electrode in the first metal layer and a thin film transistor source electrode and drain electrode in the second metal layer, respectively, the component corresponding to the physical component is determined to be a thin film transistor.

If the fact that the second polar plate of the storage capacitor in the second metal layer is connected with the drain electrode of a certain thin film transistor is determined, the connection relation between components is determined to be that the storage capacitor and the thin film transistor are in corresponding connection relation.

And similarly, determining each component and the association relation among the components according to the mode. The signal input terminal 1 is connected to the gate of the thin film transistor 1, the signal input terminal 2 is connected to the first plate of the storage capacitor, the signal input terminal 3 is connected to the source of the thin film transistor 1, the drain of the thin film transistor 1 is connected to the gate of the thin film transistor 1, and so on.

After determining the components and the association relations among the components, executing the steps to generate a target circuit schematic diagram corresponding to the physical layout according to the components and the association relations among the components.

The method comprises the steps of generating a target circuit schematic diagram corresponding to a physical layout according to each component and the association relation among the components, and comprises the following steps: acquiring a device symbol corresponding to each preset component and a connection symbol corresponding to a preset association relation; and generating a target circuit schematic diagram corresponding to the physical layout according to each component and the connection relation among the components, the device symbol and the connection symbol.

And connecting the device symbols according to the connection relation among the components, the device symbols and the connection symbols and the shortest connecting line principle to generate a target circuit schematic diagram corresponding to the physical layout.

The above parts realize that the target circuit schematic diagram corresponding to the physical layout is generated according to the physical layout. It should be noted that generating the target circuit schematic corresponding to the physical layout may also be accomplished in other manners.

103, consistency comparison is carried out on the second design drawing and the target design drawing so as to obtain a design drawing comparison result.

If the first design drawing is a circuit schematic drawing, the second design drawing is a physical layout, and the target design drawing is a target physical layout. Step 103 is: and carrying out consistency comparison on the physical layout and the generated target physical layout. The consistency comparison mainly comprises the steps of design size consistency comparison and layout consistency comparison. The comparison of the design size consistency comprises whether the design sizes between the physical layout and the generated target physical layout are consistent, whether the design sizes meet the requirements of process rules, and the like. Layout consistency comparison, including whether the connection relation between each component is completely consistent or not, and the like.

If the first design drawing is a physical layout, the second design drawing is a circuit schematic diagram, and the target design drawing is a target circuit schematic diagram. Step 103 is: and comparing the circuit schematic diagram with the generated target circuit schematic diagram in a consistent way. The consistency comparison comprises layout consistency comparison, namely whether connection relations between corresponding components and components between a comparison circuit schematic diagram and a generated target circuit schematic diagram are completely consistent or not.

After comparison, a design diagram comparison result is obtained, wherein the design diagram comparison result comprises information such as whether the design diagram comparison result is consistent, if not, the design diagram comparison result is inconsistent, and the like.

In one embodiment, as shown in fig. 1, after step 103, the method further includes:

104, if the design diagram comparison result includes inconsistent comparison results, marking the inconsistent comparison results in the second design diagram and/or the target design diagram.

If the second design is a schematic circuit diagram, a color display, a bolded display, or the like different from the schematic circuit diagram may be used. If the second design drawing is a physical layout, a color display different from that in the layer of the physical layout may be used, and so on.

And marking in the second design drawing and/or the target design drawing so as to enable the designer to quickly locate the inconsistent places and improve the efficiency.

On the other hand, it is to be noted that, if there is an unrecognizable portion, the marking may be performed, either during the comparison or during the automatic generation of the target design drawing.

According to the embodiment of the method, the target design diagram is automatically generated according to the first design diagram, the efficiency and the accuracy of obtaining the target design diagram are improved, and the second design diagram is compared with the generated target design diagram, so that the consistency of the second design diagram and the first design diagram is further determined, and the efficiency and the accuracy of determining the consistency of the first design diagram and the second design diagram are improved.

In order to better implement the method for processing a design in the embodiment of the present application, on the basis of the method for processing a design, an apparatus for processing a design in the embodiment of the present application is further provided, as shown in fig. 8, where the apparatus for processing a design includes: an acquisition unit 701, a generation unit 702, and an alignment unit 703.

An obtaining unit 701, configured to obtain a first design diagram and a second design diagram, where the first design diagram is one of a schematic circuit diagram and a physical layout, and the second design diagram is the other of the schematic circuit diagram and the physical layout.

And the generating unit 702 is configured to generate a target design drawing corresponding to the first design drawing according to the first design drawing.

The generation unit 702 includes an identification unit 7021 and a diagram generation unit 7022. The identifying unit 7021 is configured to identify the first design drawing, so as to obtain each component in the first design drawing and an association relationship between components. The diagram generating unit 7022 generates a target design diagram corresponding to the first design diagram from each component and the association relationship between components.

And a comparing unit 703, configured to compare the second design drawing with the target design drawing in accordance to obtain a design drawing comparison result.

In one case, if the first design is a schematic circuit diagram, the second design is a physical layout and the target design is a target physical layout. The identifying unit 7021 is specifically configured to identify the schematic circuit diagram, so as to obtain each component in the schematic circuit diagram and an association relationship between components. The diagram generating unit 7022 is specifically configured to generate a target physical layout corresponding to the schematic circuit diagram according to each component and the association relationship between components.

As shown in fig. 9, the map generation unit 7022 includes: component determining section 7022a, layer structure generating section 7022b, and layout generating section 7022c.

The component determining unit 7022a is configured to determine, according to each component and an association relationship between components, the number of levels of the target physical layout, physical components to be generated in each level, and a connection relationship between the physical components to be generated in each level.

The component determining unit 7022a specifically performs, when performing the step of determining the number of levels of the target physical layout based on each component and the association relationship between components: and determining the number of the levels of the target physical layout according to each component and the incidence relation among the components and a preset level number determining rule.

If the components include a scanning signal input terminal, the physical component to be generated in each level includes a first metal layer, and the component determining unit 7022a specifically performs, when performing the step of determining the physical component to be generated in each level according to each component and the association relationship between components: acquiring the number of scanning signal input ends and the number of thin film transistors in each GOA unit; determining a physical component to be generated in the first metal layer according to the scanning signal input end and the thin film transistor, wherein the physical component to be generated comprises a scanning line to be generated and a grid electrode of the thin film transistor; determining the number of scanning lines to be generated in the first metal layer according to the number of scanning signal input ends; the number of the thin film transistor gates in the first metal layer is determined according to the number of the scanning signal input ends and the number of the thin film transistors in each GOA unit.

If the components include a clock signal input end and a data signal input end, the to-be-generated physical component corresponding to each level layer includes a second metal layer, and the component determining unit 7022a specifically performs, when performing the step of determining the to-be-generated physical component in each level according to each component and the association relationship between each component: acquiring the number of clock signal input ends and the number of data signal input ends; determining a physical component to be generated in the second metal layer according to the clock signal input end, wherein the physical component to be generated comprises clock signal ends to be generated, and determining the number of the clock signal ends to be generated according to the number of the clock signal input ends; determining a physical component to be generated in the second metal layer according to the data signal input end and the grid electrode of the thin film transistor, wherein the physical component to be generated also comprises a data line to be generated, a source electrode and a drain electrode of the thin film transistor; the number of data lines to be generated is determined according to the number of data signal input terminals, and the number of thin film transistor sources and drains is determined according to the number of thin film transistor gates.

If the component includes a storage capacitor, the to-be-generated physical member corresponding to each level of layers includes a first metal layer and a second metal layer, and the member determining unit 7022a specifically performs, when performing the step of determining, according to each component and the association relationship between components, the to-be-generated physical member in each level: acquiring the number of storage capacitors in each GOA unit; determining a physical component to be generated in the first metal layer according to the storage capacitance, wherein the physical component to be generated also comprises a first polar plate of the storage capacitance, and determining the number of the first polar plate of the storage capacitance according to the number of the storage capacitance in each GOA unit and the number of the scanning signal input ends; and determining a physical component to be generated in the second metal layer according to the storage capacitance, wherein the physical component to be generated also comprises a second polar plate of the storage capacitance, and determining the number of the second polar plates of the storage capacitance according to the number of the first polar plates of the storage capacitance.

The layer structure generating unit 7022b is configured to generate a layer structure corresponding to each level according to a preset generating rule corresponding to each level and a physical component to be generated.

The layout generating unit 7022c is configured to connect the layer structures corresponding to the respective levels according to the connection relationship, so as to generate the target physical layout corresponding to the schematic circuit diagram.

In one case, if the first design is a physical layout, the second design is a schematic circuit diagram and the target design is a schematic target circuit diagram. The identifying unit 7021 is specifically configured to identify a physical layout, so as to obtain each component in the physical layout and an association relationship between components. The diagram generating unit 7022 is specifically configured to generate a target circuit schematic diagram corresponding to the physical layout according to each component and the association relationship between components.

As shown in fig. 10, the identification unit 7021 includes: a first acquisition unit 7021a, a component recognition unit 7021b, and a device determination unit 7021c. Wherein,,

the first obtaining unit 7021a is configured to obtain a layer structure corresponding to each level of the physical layout.

The component identifying unit 7021b is configured to identify, according to a preset generation rule corresponding to each hierarchy, a corresponding physical component and a connection relationship between physical components in a layer structure corresponding to each hierarchy.

The device determining unit 7021c is configured to determine each component and an association relationship between components according to the physical component and the connection relationship between the physical components.

Wherein the map generation unit 7022 includes: a second acquisition unit and a circuit diagram generation unit. The second obtaining unit is used for obtaining device symbols corresponding to the preset components and connection symbols corresponding to the preset association relations. And the circuit diagram generating unit is used for generating a target circuit schematic diagram corresponding to the physical layout according to each component and the connection relation among the components, the device symbol and the connection symbol.

In some cases, the design drawing processing device further includes: a marking unit 704. The marking unit 704 is specifically configured to mark the inconsistent comparison result in the second design drawing and the target design drawing if the comparison result of the design drawing includes the inconsistent comparison result.

It should be noted that, as those skilled in the art can clearly understand the specific implementation process and the achieved beneficial effects of the above device and each unit, reference may be made to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is given here.

The embodiment of the application also provides a computer device, which integrates any of the design drawing processing methods provided by the embodiment of the application, and the computer device comprises:

one or more processors;

a memory; and

one or more computer programs, wherein the one or more computer programs are stored in the memory and configured to perform the steps of the design drawing processing method described in any of the embodiments above by the processor.

The embodiment of the application also provides computer equipment which integrates any of the hierarchical data processing devices provided by the embodiment of the application. As shown in fig. 11, a schematic structural diagram of a computer device according to an embodiment of the present application is shown, specifically:

The computer device may include one or more processing cores 'processors 801, one or more computer-readable storage media's memory 802, power supply 803, and input unit 804, among other components. It will be appreciated by those skilled in the art that the computer device structure shown in the figures is not limiting of the computer device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. Wherein:

the processor 801 is a control center of the computer device, connects various parts of the entire computer device using various interfaces and lines, and performs various functions of the computer device and processes data by running or executing software programs (computer programs) and/or modules stored in the memory 802, and calling data stored in the memory 802, thereby performing overall monitoring of the computer device. Optionally, the processor 801 may include one or more processing cores; preferably, the processor 801 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 801.

The memory 802 may be used to store software programs and modules, and the processor 801 executes various functional applications and data processing by executing the software programs and modules stored in the memory 802. The memory 802 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data created according to the use of the computer device, etc. In addition, memory 802 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 802 may also include a memory controller to provide the processor 801 with access to the memory 802.

The computer device also includes a power supply 803 for powering the various components, preferably, the power supply 803 can be logically coupled to the processor 801 via a power management system such that functions such as managing charge, discharge, and power consumption can be performed by the power management system. The power supply 803 may also include one or more of any components, such as a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator, and the like.

The computer device may further comprise an input unit 804, which input unit 804 may be used for receiving input digital or character information and for generating keyboard, mouse, joystick, optical or trackball signal inputs in connection with user settings and function control.

Although not shown, the computer device may further include a display unit or the like, which is not described herein. In particular, in this embodiment, the processor 801 in the computer device loads executable files corresponding to the processes of one or more application programs into the memory 802 according to the following instructions, and the processor 801 executes the application programs stored in the memory 802, so as to implement various functions, as follows:

acquiring hierarchical data of a plurality of different graphic data related in a pre-stored design process of a plurality of display panels; determining general hierarchy data corresponding to the general graphic data according to the hierarchy data of the plurality of different graphic data; and fixing the universal level data corresponding to the universal graphic data.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.

To this end, an embodiment of the present application provides a computer-readable storage medium, which may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like. On which a computer program is stored, which computer program is loaded by a processor for executing the steps of any of the methods for processing a design drawing provided by the embodiments of the present application. For example, the loading of the computer program by the processor may perform the steps of:

In the foregoing embodiments, the descriptions of the embodiments are focused on, and the portions of one embodiment that are not described in detail in the foregoing embodiments may be referred to in the foregoing detailed description of other embodiments, which are not described herein again.

In the implementation, each unit or structure may be implemented as an independent entity, or may be implemented as the same entity or several entities in any combination, and the implementation of each unit or structure may be referred to the foregoing method embodiments and will not be repeated herein.

The specific implementation of each operation above may be referred to the previous embodiments, and will not be described herein.

The foregoing has outlined some of the more detailed description of the method, apparatus, computer device and storage medium for processing a design drawing in accordance with the embodiments of the present application, wherein the detailed description is provided for the purpose of illustrating the principles and embodiments of the present application and is only for the purpose of facilitating the understanding of the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A method of processing a design drawing, comprising:

generating a target design diagram corresponding to the first design diagram according to the first design diagram, including: identifying the first design diagram to obtain each component in the first design diagram and the association relation among the components; generating a target design diagram corresponding to the first design diagram according to the components and the incidence relation among the components;

Consistency comparison is carried out on the second design drawing and the target design drawing so as to obtain a design drawing comparison result;

the first design diagram is a circuit schematic diagram, the second design diagram is a physical layout, the target design diagram is a target physical layout, and the generating the target design diagram corresponding to the first design diagram according to the components and the association relations among the components includes:

determining the number of levels of the target physical layout, physical components to be generated in each level and connection relations among the physical components to be generated in each level according to the components and the incidence relations among the components;

generating a layer structure corresponding to each level according to a preset generation rule corresponding to each level and the physical component to be generated;

connecting the layer structures corresponding to all the layers according to the connection relation to generate a target physical layout corresponding to the circuit schematic diagram;

the method for determining the physical components to be generated in each level comprises the steps of:

Acquiring the number of scanning signal input ends and the number of thin film transistors in each GOA unit;

determining a physical component to be generated in the first metal layer according to the scanning signal input end and the thin film transistor, wherein the physical component to be generated comprises a scanning line to be generated and a thin film transistor grid electrode;

and determining the number of scanning lines to be generated in the first metal layer according to the number of the scanning signal input ends, and determining the number of the thin film transistor gates according to the number of the scanning signal input ends and the number of the thin film transistors in each GOA unit.

2. The method for processing a design drawing according to claim 1, wherein the components further comprise a clock signal input terminal and a data signal input terminal, the physical components to be generated in each level layer comprise a second metal layer, and the determining the physical components to be generated in each level according to each component and the association relation between each component comprises:

acquiring the number of clock signal input ends and the number of data signal input ends;

determining a physical component to be generated in the second metal layer according to the clock signal input end, wherein the physical component to be generated comprises clock signal ends to be generated, and determining the number of the clock signal ends to be generated according to the number of the clock signal input ends;

And determining a physical component to be generated in the second metal layer according to the data signal input end and the thin film transistor grid electrode, wherein the physical component to be generated also comprises a data line to be generated, a thin film transistor source electrode and a thin film transistor drain electrode, determining the number of the data line to be generated according to the number of the data signal input end, and determining the number of the thin film transistor source electrode and the thin film transistor drain electrode according to the number of the thin film transistor grid electrode.

3. The method of claim 2, wherein the components further include storage capacitors, and the determining the physical components to be generated in each level according to the components and the association relationships between the components includes:

acquiring the number of storage capacitors in each GOA unit;

determining a physical component to be generated in the first metal layer according to the storage capacitors, wherein the physical component to be generated also comprises first polar plates of the storage capacitors, and determining the number of the first polar plates of the storage capacitors according to the number of the storage capacitors and the number of scanning signal input ends;

and determining a physical component to be generated in the second metal layer according to the storage capacitor, wherein the physical component to be generated also comprises a second polar plate of the storage capacitor, and determining the number of the second polar plates of the storage capacitor according to the number of the first polar plates of the storage capacitor.

4. The method for processing a design drawing according to claim 1, wherein the first design drawing is a physical layout, the second design drawing is a schematic circuit drawing, the target design drawing is a schematic circuit drawing, and the generating the target design drawing corresponding to the first design drawing according to the first design drawing includes:

acquiring a device symbol corresponding to each preset component and a connection symbol corresponding to a preset association relation;

and generating a target circuit schematic diagram corresponding to the physical layout according to the components and the connection relation among the components, the device symbols and the connection symbols.

5. A design drawing processing apparatus, comprising:

the device comprises an acquisition unit, a first control unit and a second control unit, wherein the acquisition unit is used for acquiring a first design diagram and a second design diagram, the first design diagram is one of a circuit schematic diagram and a physical layout, and the second design diagram is the other of the circuit schematic diagram and the physical layout;

the generating unit is used for generating a target design diagram corresponding to the first design diagram according to the first design diagram;

the generating unit comprises an identifying unit and a graph generating unit, wherein the identifying unit is used for identifying the first design graph to obtain each component in the first design graph and the association relation among the components; the map generating unit is used for generating a target design map corresponding to the first design map according to each component and the association relation among the components;

The first design diagram is a circuit schematic diagram, the second design diagram is a physical layout, the target design diagram is a target physical layout, and the diagram generating unit comprises a construction determining unit, a layer structure generating unit and a layout generating unit;

the construction determining unit is used for determining the number of levels of the target physical layout, physical components to be generated in each level and the connection relation among the physical components to be generated in each level according to each component and the association relation among the components;

when the components include scanning signal input ends and the physical components to be generated in each level include a first metal layer, the construction determining unit specifically performs when determining the physical components to be generated in each level according to each component and the association relation among the components: acquiring the number of scanning signal input ends and the number of thin film transistors in each GOA unit; determining a physical component to be generated in the first metal layer according to the scanning signal input end and the thin film transistor, wherein the physical component to be generated comprises a scanning line to be generated and a grid electrode of the thin film transistor; determining the number of scanning lines to be generated in the first metal layer according to the number of scanning signal input ends; determining the number of thin film transistor gates in the first metal layer according to the number of scanning signal input ends and the number of thin film transistors in each GOA unit;

The layer structure generating unit is used for generating a layer structure corresponding to each level according to a preset generating rule corresponding to each level and the physical component to be generated;

the layout generating unit is used for connecting the layer structures corresponding to all the layers according to the connection relation to generate a target physical layout corresponding to the circuit schematic diagram;

6. A computer device, the computer device comprising:

one or more processors; a memory; and one or more computer programs, wherein the processor is coupled to the memory, the one or more computer programs being stored in the memory and configured to be executed by the processor to implement the design drawing processing method of any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program that is loaded by a processor to perform the design drawing processing method of any one of claims 1 to 4.