CN1514475A - Detecting method of silicon material quality in dielectrode integrated circuit - Google Patents
Detecting method of silicon material quality in dielectrode integrated circuit Download PDFInfo
- Publication number
- CN1514475A CN1514475A CNA021605378A CN02160537A CN1514475A CN 1514475 A CN1514475 A CN 1514475A CN A021605378 A CNA021605378 A CN A021605378A CN 02160537 A CN02160537 A CN 02160537A CN 1514475 A CN1514475 A CN 1514475A
- Authority
- CN
- China
- Prior art keywords
- type
- buried layer
- quality
- integrated circuit
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The method includes following three steps. (1) Structure of NPN tube possessing N buried layer is built for the testing procedure to validate breakdown voltage BVceo between emitter and collector of NPN tube in model PVM. (2) Structure of diode possessing N buried layer i.e. collector structure of NPN tube possessing N buried layer is built to test quality of N type epitaxy. (3) Structure of diode without N buried layer i.e. collector structure of NPN tube without N buried layer is built to test breakdown voltage between base and collector of NPN tube without N buried layer so as to determine whether the quality of the breakdown voltage is relevant to quality of the silicon material. Steps (2) and (3) eliminate issues of quality for preparing IC, i.e. problems in N type epitaxy and base electrode. Thus, issues of quality in original single crystal chip i.e. first order defect causing creepage out of criterion are found.
Description
Technical field
The present invention relates to a kind of method of inspection of quality of materials, relate in particular to the detection method of silicon materials quality in a kind of bipolar integrated circuit of differentiating employed silicon single crystal flake quality problems in the integrated circuit.
Background technology
The quality of employed silicon single crystal flake is very important in the production of integrated circuits, and this is the basic guarantee of integrated circuit qualification rate.The quality of silicon single crystal flake can be divided into two kinds, promptly, one causes the integrated circuit qualification rate to descend because of former quality of the single crystal wafer problem causes electric leakage supergage (perhaps being called defective one time), and two quality problems because of silicon chip manufacturing (integrated circuit manufacturing) cause electric leakage supergage (perhaps being called secondary defect).Therefore the quality or the quality problems of silicon chip manufacturing how to distinguish former single-chip seem especially important, it can make monocrystalline manufacturer and wafer fabrication plant man act in accordance with the division of their functions and duties and improve its technology, makes it to reach the state that integrated circuit (IC) products can be stable at high qualification rate.
And prior art processes confirms model PVM (Process Validation Module) test, its PVM figure only can detect testing integrated circuits NPN pipe puncture voltage BV ceo, to judge NPN pipe quality in the integrated circuit, but for the puncture under the drain conditions of 1uA, the quality problems (defective) that then can't the judge former single-chip still secondary defect that causes of silicon chip manufacturing cause the big reason of electric leakage.
Summary of the invention
The object of the present invention is to provide the detection method of silicon materials quality in a kind of bipolar integrated circuit, it can make simplifies the problem of judging quality of the single crystal wafer, thereby the qualification rate that guarantees integrated circuit tends towards stability.
The object of the present invention is achieved like this:
The detection method of silicon materials quality in a kind of bipolar integrated circuit is characterized in may further comprise the steps:
Step 1 is set up the NPN tubular construction with N buried regions, confirms the puncture voltage BV ceo of the emitter of NPN pipe among the model PVM to collector electrode in order to test technology, to judge NPN pipe quality in the integrated circuit;
Step 2 is set up the diode structure with n type buried layer, the NPN pipe collector junction structure of n type buried layer is promptly arranged, in order to the quality of measuring N type extension;
Step 3, foundation does not have the diode structure of n type buried layer, the NPN pipe collector junction structure that does not promptly have n type buried layer, the base stage of NPN pipe that does not have n type buried layer in order to measurement is to the puncture voltage BVceo of collector electrode, so that judge further whether the quality of this puncture voltage is relevant with the silicon materials quality;
Through the detection of step 2 and step 3, by getting rid of the quality problems that integrated circuit is made, promptly get rid of the problem of N type extension and base, thereby find because of former quality of the single crystal wafer problem promptly a defective cause the electric leakage supergage.
In above-mentioned bipolar integrated circuit, in the detection method of silicon materials quality, wherein, in described step 1, set up NPN tubular construction and may further comprise the steps with n type buried layer,
1) select suitable substance P type silicon single crystal flake as substrate;
2) at P type silicon single crystal flake superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer;
3) removing the oxide layer N type extension of growing later on;
4) at N type epitaxial surface growthing silica, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters the zone, and making the zone form collector junction is P type base;
5) adopt photoetching, the oxide layer that forms when lithographic technique is opened boron diffusion is carried out squama or arsenic diffusion, forms N type emitter region.
In above-mentioned bipolar integrated circuit, in the detection method of silicon materials quality, wherein, in described step 2, set up diode structure and may further comprise the steps with n type buried layer,
1) select suitable substance P type silicon single crystal flake as substrate;
2) at P type silicon single crystal flake superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer;
3) removing the oxide layer N type extension of growing later on;
4) at N type epitaxial surface growthing silica, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters the zone, and making the zone form collector junction is P type base.
In the detection method of silicon materials quality, wherein, in described step 3, setting up does not have the diode structure of n type buried layer may further comprise the steps in above-mentioned bipolar integrated circuit,
1) select suitable substance P type silicon single crystal flake as substrate;
2) in P type silicon single crystal flake growth N type extension;
3) at N type epitaxial surface growthing silica, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters the zone, and making the zone form collector junction is P type base.
The detection method of silicon materials quality in the bipolar integrated circuit of the present invention owing to adopted above-mentioned technical scheme, makes it compared with prior art, has tangible advantage and good effect.The present invention is owing to set up the NPN tubular construction (PVM figure) with N buried regions, NPN pipe collector junction (diode) structure that n type buried layer is arranged, and increased this new construction of NPN pipe collector junction (diode) structure that does not have n type buried layer, adopt the PVM new construction can distinguish quality problems (defective) that integrated circuit the makes NPN pipe electric leakage problem that still (secondary defect) causes in the silicon chip manufacture process, thereby the abnormal NPN of characteristic is managed the analysis refinement and the correct judgment of electric leakage problem.
Description of drawings
Embodiment by following detection method to silicon materials quality in the bipolar integrated circuit of the present invention can further understand purpose of the present invention, specific structural features and advantage in conjunction with the description of its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 is the structural representation of NPN tubular construction in the step 1 integrated circuit in the detection method of silicon materials quality in the bipolar integrated circuit of the present invention;
In Fig. 2 bipolar integrated circuit of the present invention in the detection method of silicon materials quality step 2 the structural representation of n type buried layer diode structure is arranged;
In Fig. 3 bipolar integrated circuit of the present invention in the detection method of silicon materials quality step 3 do not have the structural representation of the diode structure of n type buried layer.
Embodiment
See also Fig. 1 to shown in Figure 3, the present invention, the detection method of silicon materials quality in a kind of bipolar integrated circuit may further comprise the steps:
Step 1 is set up the NPN tubular construction with N buried regions, confirms the puncture voltage BV ceo of the emitter of NPN pipe among the model PVM to collector electrode in order to test technology, to judge NPN pipe quality in the integrated circuit.See also shown in Figure 1, Fig. 1 is a NPN tubular construction in the integrated circuit, and confirm that in technology the structure of NPN transistor in the active device NPN transistor of testing among the model PVM (Process Validation Module) and the actual integrated circuit is identical usually, therefore, Fig. 1 also is a NPN tubular construction among the PVM simultaneously; Label 10 is P type silicon single crystal flakes among Fig. 1, the 11st, and n type buried layer, the 12nd, growth N type extension on 11 monocrystalline, the 13rd, P type base, the 14th, N type emitter region; Formed N buried regions NPN pipe thus.
There is the manufacturing step of N buried regions NPN pipe as follows: at first to select suitable substance P type silicon single crystal flake 20 as substrate; At P type silicon single crystal flake 20 superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer 21; Removing the oxide layer N type extension 22 of growing later on; At N type extension 22 superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone 23, and making zone 23 form collector junction is P type base 23; Adopt photoetching, the oxide layer that forms when lithographic technique is opened boron diffusion is carried out squama or arsenic diffusion, forms N type emitter region 24.
Above-mentioned steps one has formed N buried regions NPN pipe; In order to NPN pipe puncture voltage BV ceo among the test PVM, can judge NPN pipe quality in the integrated circuit; But how to judge the quality problems that " defective " or " secondary defect " cause, ask for an interview step 2 and step 3.
Step 2 is set up the diode structure with n type buried layer, the NPN pipe collector junction structure of n type buried layer is promptly arranged, in order to the quality of measuring N type extension.
Ask for an interview shown in Figure 2ly, Fig. 2 is the structural representation that step 2 of the present invention has the n type buried layer diode structure.Among the figure, label 20 is P type silicon single crystal flakes, the 21st, and n type buried layer, the 22nd, growth N type extension on 21 monocrystalline, the 23rd, P type base; Numbering on Fig. 2 is identical with Fig. 1, then is to do this technology together, has formed N buried regions diode thus.
The concrete step of setting up the diode structure with n type buried layer is at first to select suitable substance P type silicon single crystal flake 20 as substrate; At P type silicon single crystal flake 20 superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer 21; Removing the oxide layer N type extension 22 of growing later on; At N type extension 22 superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone 23, and making zone 23 form collector junction is P type base 23.
Step 3, foundation does not have the diode structure of n type buried layer, the NPN pipe collector junction structure that does not promptly have n type buried layer, there is not the base stage of NPN pipe of n type buried layer to the puncture voltage BV ceo of collector electrode, so that judge further whether the quality of this puncture voltage is relevant with the silicon materials quality in order to measure in order to measurement.
See also shown in Figure 3ly, this is the structural representation that step 3 of the present invention does not have the diode structure of n type buried layer.Among the figure, label 20 is P type silicon single crystal flakes, the 22nd, and growth N type extension on 20 monocrystalline, the 23rd, P type base; Numbering on Fig. 3 is identical with Fig. 1, then is to do this technology together, and having formed does not thus have N buried regions diode.
The concrete step of setting up the diode structure that does not have n type buried layer is at first to select suitable substance P type silicon single crystal flake 20 as substrate; In P type silicon single crystal flake 20 growth N type extensions 22; At N type extension 22 superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone 23, and making zone 23 form collector junction is P type base 23.
Through the detection of step 2 and step 3, by getting rid of the quality problems that integrated circuit is made, promptly get rid of the problem of N type extension and base, thereby can find because of former quality of the single crystal wafer problem promptly a defective cause the electric leakage supergage.
In integrated circuit is made, integrated circuit to scrap reason more, quite disperse if run into the qualification rate of 50 on a whole card, from monolithic 5% to monolithic 90%.At first test MOS structure among the PVM, discharge is that the puncture voltage that surface leakage causes descends; Test then N buried regions among the PVM the NPN tubular construction, have the diode structure of n type buried layer and do not have the diode structure of n type buried layer; And make the correlation diagram of three kinds of structures and qualification rate thereof respectively by Computer Processing, can obtain coefficient R (Correlation) by Computer Processing; The result who obtains is: three extreme pipe coefficient R=0.84 of Fig. 1; The buried regions two that has of Fig. 2 is extremely managed coefficient R=0.1; The buried regions two that do not have of Fig. 3 is extremely managed coefficient R=0.96.
This situation can be interpreted as:
Fig. 1 is a triode, and technology is than diode complexity, and promptly influencing factor is more, thus correlation is arranged, but can not be the highest;
The buried regions diode that has of Fig. 2 finds that through test its puncture voltage all reaches desirable avalanche breakdown voltage value, and the antimony ion implantation dosage of its n type buried layer is from 6*10
14Individual atom/CM
2To 4*10
15Individual atom/CM
2, promptly the change in concentration of n type buried layer is bigger, but its puncture voltage is constant, and this can be understood as n type buried layer has a kind of phosphorus of and high concentration (greater than 10
21Individual atom/CM
2) same impurity absorption phenomenon, make the avalanche breakdown voltage value that reaches desirable; But antimony element saturation solubility limited (only 10
19Individual antimony atoms/CM
3), therefore in fact do not have the impurity absorption function, so its coefficient correlation is very low;
And the coefficient correlation of the diode that does not have buried regions of Fig. 3 C is the highest, and the technology that while Fig. 3 is correlated with is minimum, and is therefore relevant with which procedure than being easier to judgement;
This shows, from having done minimum processing technology, obtained maximum correlation, the quality of the single-chip of correlation and P type or N type extension is relevant as can be seen, in the problem of getting rid of N type extension 22 and base 23, promptly can find the quality (i.e. defective) of single-chip is key factor, so just can determine corresponding standard to the single-chip quality of materials according to the performance requirement of integrated circuit.
In sum, the present invention, produce needs tens procedures according to actual integrated circuit, and analyze because the electric leakage supergage causes quality problems and decomposes, three kinds of structures of design are judged in the PVM structure, not only can make problem reduction, and can be with the refinement of the abnormal NPN pipe of characteristic electric leakage problem, with correct difference is that the electric leakage supergage that secondary defect causes in monocrystal material quality problems (defective) or the silicon chip manufacture process causes the integrated circuit qualification rate to descend, thereby improve technology accurate data are provided for monocrystalline manufacturer and wafer fabrication plant man act in accordance with the division of their functions and duties, make integrated circuit (IC) products reach the level that can be stable at high qualification rate.
Claims (4)
1. the detection method of silicon materials quality in the bipolar integrated circuit is characterized in that may further comprise the steps:
Step 1 is set up the NPN tubular construction with N buried regions, confirms the puncture voltage of the emitter of NPN pipe in the model to collector electrode in order to test technology, to judge NPN pipe quality in the integrated circuit;
Step 2 is set up the diode structure with n type buried layer, the NPN pipe collector junction structure of n type buried layer is promptly arranged, in order to the quality of measuring N type extension;
Step 3, foundation does not have the diode structure of n type buried layer, the NPN pipe collector junction structure that does not promptly have n type buried layer, the base stage of NPN pipe that does not have n type buried layer in order to measurement is to the puncture voltage of collector electrode, so that judge further whether the quality of this puncture voltage is relevant with the silicon materials quality;
Through the detection of step 2 and step 3, by getting rid of the quality problems that integrated circuit is made, promptly get rid of the problem of N type extension and base, thereby find because of former quality of the single crystal wafer problem promptly a defective cause the electric leakage supergage.
2. the detection method of silicon materials quality in the bipolar integrated circuit as claimed in claim 1 is characterized in that: in described step 1, sets up NPN tubular construction and may further comprise the steps with n type buried layer,
1) select suitable substance P type silicon single crystal flake (20) as substrate;
2) at P type silicon single crystal flake (20) superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer (21);
3) removing the oxide layer N type extension (22) of growing later on;
4) at N type extension (22) superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone (23), and making zone (23) form collector junction is P type base (23);
5) adopt photoetching, the oxide layer that forms when lithographic technique is opened boron diffusion is carried out squama or arsenic diffusion, forms N type emitter region (24).
3. the detection method of silicon materials quality in the bipolar integrated circuit as claimed in claim 1 is characterized in that: in described step 2, sets up diode structure and may further comprise the steps with n type buried layer,
1) select suitable (P) type silicon single crystal flake (20) as substrate;
2) at P type silicon single crystal flake (20) superficial growth silicon dioxide, adopt photoetching and corrosion technology to remove oxide layer, there not being oxide layer zone ion to inject antimony, carry out high temperature and advance, form n type buried layer (21);
3) removing the oxide layer N type extension (22) of growing later on;
4) at N type extension (22) superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone (23), and making zone (23) form collector junction is P type base (23).
4. the detection method of silicon materials quality in the bipolar integrated circuit as claimed in claim 1 is characterized in that: in described step 3, setting up does not have the diode structure of n type buried layer may further comprise the steps,
1) select suitable substance P type silicon single crystal flake (20) as substrate;
2) in P type silicon single crystal flake (20) growth N type extension (22);
3) at N type extension (22) superficial growth silicon dioxide, adopt photoetching, lithographic technique limits the boron diffusion of P type and enters zone (23), and making zone (23) form collector junction is P type base (23).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021605378A CN100365786C (en) | 2002-12-31 | 2002-12-31 | Detecting method of silicon material quality in dielectrode integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021605378A CN100365786C (en) | 2002-12-31 | 2002-12-31 | Detecting method of silicon material quality in dielectrode integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1514475A true CN1514475A (en) | 2004-07-21 |
| CN100365786C CN100365786C (en) | 2008-01-30 |
Family
ID=34237900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021605378A Expired - Fee Related CN100365786C (en) | 2002-12-31 | 2002-12-31 | Detecting method of silicon material quality in dielectrode integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100365786C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101191250B (en) * | 2006-11-21 | 2010-09-08 | 上海华虹Nec电子有限公司 | Method for detecting normal growth of epitaxy single-crystal |
| CN101606239B (en) * | 2007-01-05 | 2011-05-04 | 信越半导体股份有限公司 | Silicon wafer evaluation method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3037191B2 (en) * | 1997-04-22 | 2000-04-24 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor device |
| US6323668B1 (en) * | 1997-11-20 | 2001-11-27 | Advantest Corporation | IC testing device |
| JP2002076281A (en) * | 2000-08-30 | 2002-03-15 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| US6444551B1 (en) * | 2001-07-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | N-type buried layer drive-in recipe to reduce pits over buried antimony layer |
-
2002
- 2002-12-31 CN CNB021605378A patent/CN100365786C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101191250B (en) * | 2006-11-21 | 2010-09-08 | 上海华虹Nec电子有限公司 | Method for detecting normal growth of epitaxy single-crystal |
| CN101606239B (en) * | 2007-01-05 | 2011-05-04 | 信越半导体股份有限公司 | Silicon wafer evaluation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100365786C (en) | 2008-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1605127A (en) | Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same | |
| CN1148271A (en) | Semiconductor device and method of mfg. the same | |
| CN1514475A (en) | Detecting method of silicon material quality in dielectrode integrated circuit | |
| CN1494162A (en) | Semiconductor substrate and its mfg. method, and semiconductor device and its mfg. method | |
| CN1596464A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN1977374A (en) | Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement | |
| US7388256B2 (en) | Semiconductor device and a method of manufacturing the same | |
| KR102029708B1 (en) | Semiconductor wafer evaluation method | |
| CN102074454B (en) | Monitoring method and system of etching process | |
| CN1079168C (en) | Method for measuring leakage current in junction region of semiconductor device | |
| CN101043027A (en) | Anti-fuse and stylization method thereof | |
| CN115360172A (en) | Method for manufacturing silicon carbide semiconductor device | |
| US6313480B1 (en) | Structure and method for evaluating an integrated electronic device | |
| US20070231934A1 (en) | Classification apparatus for semiconductor substrate, classification method of semiconductor substrate, and manufacturing method of semiconductor device | |
| CN111933694B (en) | Polycrystalline self-doped smooth top gate JFET device and manufacturing method thereof | |
| KR100490333B1 (en) | Bipolar Transistors and Manufacturing Method | |
| KR0161869B1 (en) | A semiconductor device | |
| JP3104265B2 (en) | Ion implantation method | |
| Roggenbauer et al. | An electrical monitor of deep trench depth | |
| Hayase et al. | Applications of site-specific scanning spreading resistance microscopy (SSRM) to failure analysis of production lines | |
| Kröner | Knock-on of contaminants causing instabilities of transistor characteristics | |
| CN111430305A (en) | Method for manufacturing electrostatic discharge protection device and electrostatic discharge protection device | |
| JPH0691145B2 (en) | Semiconductor wafer sorting method | |
| Roedel et al. | The fabrication of Ga/sub 1-x/Al/sub x/As-GaAs heterojunction bipolar transistors for rapid material analysis | |
| JPH01187854A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080130 Termination date: 20151231 |
|
| EXPY | Termination of patent right or utility model |