JP3104265B2 - Ion implantation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation method for suppressing the occurrence of defects in an ultra-high density semiconductor device.

[0002]

2. Description of the Related Art A conventional semiconductor device is in a state in which stress is increased due to an increase in element density and defects are liable to grow. The occurrence of defects in a conventional semiconductor device will be described using the MOS transistor shown in FIG. 6 as an example.

[0003] As in FIG. 6 (a), on a semiconductor substrate 1, M
Gate electrode 2 of OS transistor and LDD (lightly doped
forming an oxide film sidewall region 3 for forming the drain) structure, then using the arsenic ion beam 4 for forming the source and drain regions, the high concentration n + region 5 formed by arsenic ion implantation To form . At this time,
At the same time, an amorphous region 6 is formed in the silicon substrate 1 by implantation damage.

When the amorphous region 6 grows by heat treatment, as shown in FIG. 1 (b), there are two types of vertical growth which grow in the horizontal direction 9 and those which grow upward from the lower side of the substrate. Crystal growth from the direction of. Therefore, a crystal discontinuity of the void 10 exists at a portion where the both collide and hit at the end, and a defect is formed. When some kind of stress is applied to the defect area, a defect grows from the void 10. Tamura et al. Commented on the creation of voids in this part by Nuclear Instrument Ant.
clear Instruments and Methods) B37 / 38 (1989) p.329.

[0005]

In the conventional implantation method configured as described above, since the voids 10 are formed, the incidence of crystal defects is inevitably increased, and even the pn junction of a precise element is formed. Leakage current flows because it extends and crosses the pn region sensitive to defects. Therefore, sufficient characteristics cannot be expected, and the yield of non-defective products is remarkably reduced. The element at this time is not limited to the source / drain, but is always a problem when an amorphous region is formed by performing high-concentration implantation using a mask. For these reasons, at the present time when the ultra-high density has been advanced, the mechanical stress becomes large, so that a leak current is large and a good product cannot be produced.

In view of the foregoing, it is an object of the present invention to provide an ion implantation method that suppresses defects caused by changing the shape of an amorphous region formed by ion implantation from the conventional one.

[0007]

According to the ion implantation method of the present invention, a mask material having a predetermined pattern is arranged on a semiconductor substrate.
And ion implantation angle with respect to the normal line of the step and the substrate main surface to set formed by largely inclined 20 degrees to 60 degrees, by performing an active ion species implanted, sufficient amorphous region to under said mask material by entering, the frontmost tangent slope of the amorphous region Ru der those with <br/> a more Engineering be formed to less than 90 degrees.

[0008]

According to the present invention, active ion species are implanted into a masked substrate with a relatively large inclination in the range of 20 to 60 degrees with respect to the normal to the main surface of the substrate. it is the shape of the formation of the amorphous region, in the injection near vertical to a conventional substrate main surface, as compared with those injected distribution area immediately below the mask material is formed into an inverted tapered shape, amorphous At the edge of the amorphous region,
It has a gentle bowl shape with a line inclination of less than 90 degrees . As a result, recrystallization during the heat treatment does not grow from two directions with a cross angle of 90 degrees or more.
It is difficult to form a defect nucleus called a void. Therefore, even in a relatively large stress in a later process,
Razz growth of defects Oko, less abnormal due to the occurrence of defects
LSI can be realized.

[0009]

Embodiment 1 FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

In FIG. 1A, reference numeral 1 denotes a p-type silicon substrate, 2 denotes a polysilicon gate, and 3 denotes an oxide film sidewall. Arsenic ion beam 4 is implanted from an injection angle of 20 degrees to 6
The injection was performed by changing the angle to 0 degrees and using a rotation or step rotation injection method. Dose is about 1 × 10 necessary for forming the amorphous region at the time of 20 degrees
As long ¹⁴ cm ^-2 or higher, in the present embodiment using a dose of 4 × 10 ¹⁵ cm ^-2. At other angles, the injection angle 2
Cosine ( co) of each angle with reference to the dose at 0 degree
The injection amount of the plane was matched in the factor of sine ) . Under these ion implantation conditions, an n-type region 5 and an amorphous region 6 are formed.

FIG. 1B is an enlarged view of the lower portion of the side wall 3. As shown in FIG. This form, in comparison with FIG. 6, n-type territory in bowl shape curved portion of the bottom of the side wall 3
The tangent slope of the normal on the forefront of the region 5 and the amorphous region 6 is 90
Less than a degree . By that , amorphous
The intersection angle in two directions indicated by arrows 7 and 8 in the tangential direction of the normal line on the front surface of the quality region 6 is an acute angle. Therefore, even after the heat treatment, the generation of voids generated in FIG. 6 is suppressed, and no defect nucleus is formed. Further, since the n-type region 5 entirely takes in the amorphous region 6, the defective layer does not cross the junction, and the leak current at the junction caused by the defective layer can be eliminated.

Thereafter, oxidation of 10 nm was performed, a protective oxide film was deposited to a thickness of 300 nm, contacts were formed in the source / drain regions, and a test transistor group having a scale equivalent to 1 MDRAM was formed. The current flowing when 5 V is applied to the source / drain is 10
A test transistor group of 0 nA or less was determined to be non-defective, and the device yield was determined. The result is shown in FIG.

In the figure, a remarkable improvement in the yield can be seen by making the implantation angle larger than 20 degrees. Also, increasing the injection angle to 60 degrees, exchange in the frontmost normal of two directions (arrows 7, 8) in the amorphous region 6
The difference angle becomes more acute, and the probability of occurrence of voids decreases. However, exceeding 60 degrees is a factor of the above cosine.
Injection energy to maintain the plane
Is not practical.

The element isolation employed here was a selective oxidation by depositing a 160 nm nitride film on a 20 nm underlying oxide film. The element isolation width used was 0.5 μm in the mask dimensions. In the case of trench burying isolation, the yield is further reduced because a larger stress is applied. However, when implantation is performed at an inclination angle of 20 degrees with respect to the normal to the main surface of the substrate , the yield does not decrease even in trench burying isolation. Was. In other words, since the nucleus of the defect disappeared, the influence of the stress was hardly affected.

[0015] In the present embodiment has formed the amorphous region 6 by using arsenic ions, phosphorus other than arsenic ions Io
Down, active ionic species the same effect even in the case of such boron fluoride (e.g. BF ₂₎ ions are obtained. In this embodiment, an n-type region 5 is formed in the p-type substrate 1 and the n-type region 5 is formed.
Although the amorphous region 6 is formed inside, the p-type region may be formed in the n-type substrate, and the n-type region including the amorphous region may be formed inside the p-type region. It goes without saying that the amorphous regions may be formed by setting the molds to the opposite conductivity types.

(Embodiment 2) Next, a second embodiment will be described with reference to FIG. FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

In the method shown in the first embodiment, since electrically active ions sufficiently enter under the mask, there is a strong influence on the electrical characteristics such as a short channel effect. Abnormality occurs. Therefore, the present embodiment provides a method for forming only an amorphous region gently using ions that are less affected electrically, that is, ions that are electrically inactive in silicon.

As shown in FIG. 1A, an n-type region 5 and a first amorphous region 6a are formed by implanting arsenic ions 4 almost vertically, for example, at 7 degrees . Thereafter, as shown in FIG. 3B, the silicon ions 12 are rotated at an implantation angle of 20 degrees or by a step rotation implantation method.
By implanting at a dose of × 10 ¹⁵ cm ⁻² , the second amorphous region 6 b is formed at the end of the first amorphous region 6 a, so that the portion that has penetrated under the arsenic mask is formed. Only the shape of the amorphous region 6 is made the same gentle shape as in FIG. As a result, generation of defects can be suppressed.

In this embodiment, silicon ions are implanted after arsenic ions are implanted to make the shape of the amorphous region under the mask material gentle. However, as shown in FIG. Under the same ion implantation conditions used in
After forming the first amorphous region 6a by performing silicon ion implantation, arsenic ion implantation is performed to form the second amorphous region 6b overlapping the first amorphous region 6a. Has the effect of

Further, in this embodiment, since there is a high risk that the amorphous region 6 protrudes from the n-type region 5, the first region shown in FIG.
Before forming the amorphous region 6a of FIG.
5A and 5B by implanting at a dose of 0 ¹³ cm ^-2 .
The low-concentration n-type region 15 is
By using the LDD structure (see FIG. 5) or the LATID structure formed therein, the low-concentration n-type region 15 takes in the amorphous region 6 and eliminates the cause of the leakage current.

In this embodiment, silicon ions are used as electrically inactive ions. However, at least one ion of the group consisting of germanium, argon, nitrogen, fluorine and the like is used or these ions are contained. molecular ion, the same effect can be obtained by using the ion ₂ such example <br/> in SiF _2, GeF. In particular, when ions having a larger mass number than silicon ions, for example, germanium ions, are used, amorphousization can be realized at a low dose. Furthermore, with the sample kept at a low temperature such as liquid nitrogen temperature, the inclination angle with respect to the normal line of the main surface of the substrate
When the amorphous region is formed below the mask material using the large-angle ion implantation of 20 to 60 degrees, the formation of the amorphous region can be realized with a lower dose. Although arsenic ions were used to form the impurity regions, the same effect as arsenic can be obtained by using active ion species such as phosphorus and BF ₂ ions other than arsenic ions.

In the first and second embodiments, a silicon substrate is used. However, it is needless to say that a compound semiconductor substrate such as GaAs or InP may be used.

[0023]

As described above, according to the present invention,
Since nuclei of defects are not formed even in a state where stress is large, a reduction in the yield of LSI due to an increase in leakage current of electrical characteristics is not seen, and its practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing an injection angle dependency of a diode leak yield in the example.

FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a process chart showing another method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a process chart showing a method for manufacturing a semiconductor device using the LDD structure of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 substrate 3 LDD sidewall 4 ion beam 5 n + layer 6 amorphous region 7, 8 crystal growth direction 12 Si ion

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/265 H01L 29/78 H01L 21/336

Claims (3)

(57) [Claims] 1. A mass of predetermined pattern on a semiconductor substrate
The step of disposing and forming a mask material and the step of ion-implanting an active ion species with the ion implantation angle with respect to the normal line of the main surface of the substrate being greatly inclined to 20 to 60 degrees are performed. until down by sufficient penetration, ion implantation method frontmost tangent slope with a more Engineering be formed to less than 90 degrees of the amorphous region. Wherein the active ionic species in the ion implantation for forming the amorphous region is arsenic, according to claim 1, characterized in that at least one of phosphorus and boron fluoride (e.g. BF ₂₎ Ion implantation method. The 3. A junction to capture amorphous region, the ion implantation method according to claim 1 or 2, comprising the step of forming.