CN1512410A - 集成电路的最优化设计装置和方法、以及记录媒体 - Google Patents
集成电路的最优化设计装置和方法、以及记录媒体 Download PDFInfo
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- CN1512410A CN1512410A CNA200310124440XA CN200310124440A CN1512410A CN 1512410 A CN1512410 A CN 1512410A CN A200310124440X A CNA200310124440X A CN A200310124440XA CN 200310124440 A CN200310124440 A CN 200310124440A CN 1512410 A CN1512410 A CN 1512410A
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 238000013461 design Methods 0.000 title claims description 78
- 238000005457 optimization Methods 0.000 claims abstract description 152
- 238000004458 analytical method Methods 0.000 claims abstract description 81
- 238000010206 sensitivity analysis Methods 0.000 claims abstract description 65
- 230000008859 change Effects 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 description 50
- 238000011369 optimal treatment Methods 0.000 description 42
- 238000010586 diagram Methods 0.000 description 20
- 230000006870 function Effects 0.000 description 18
- 230000008569 process Effects 0.000 description 17
- 230000035945 sensitivity Effects 0.000 description 16
- 230000001052 transient effect Effects 0.000 description 13
- 238000003860 storage Methods 0.000 description 9
- 238000013500 data storage Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 239000000284 extract Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 4
- 210000000352 storage cell Anatomy 0.000 description 4
- 238000012552 review Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 235000013599 spices Nutrition 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000013386 optimize process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP381336/2002 | 2002-12-27 | ||
JP2002381336A JP4202120B2 (ja) | 2002-12-27 | 2002-12-27 | 集積回路の最適化設計装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1512410A true CN1512410A (zh) | 2004-07-14 |
CN100437592C CN100437592C (zh) | 2008-11-26 |
Family
ID=32708483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200310124440XA Expired - Fee Related CN100437592C (zh) | 2002-12-27 | 2003-12-26 | 集成电路的最优化设计装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7155685B2 (zh) |
JP (1) | JP4202120B2 (zh) |
KR (1) | KR100849764B1 (zh) |
CN (1) | CN100437592C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106326507A (zh) * | 2015-06-24 | 2017-01-11 | 中国科学院微电子研究所 | 一种模拟集成电路约束提取方法及系统 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7315993B2 (en) * | 2004-11-30 | 2008-01-01 | Lsi Logic Corporation | Verification of RRAM tiling netlist |
US7289859B2 (en) * | 2005-09-30 | 2007-10-30 | Hitachi, Ltd. | Method for determining parameter of product design and its supporting system |
US7716612B1 (en) * | 2005-12-29 | 2010-05-11 | Tela Innovations, Inc. | Method and system for integrated circuit optimization by using an optimized standard-cell library |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US7943967B2 (en) | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
US8935146B2 (en) * | 2007-03-05 | 2015-01-13 | Fujitsu Semiconductor Limited | Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US7949985B2 (en) * | 2007-06-01 | 2011-05-24 | Synopsys, Inc. | Method for compensation of process-induced performance variation in a MOSFET integrated circuit |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101739709B1 (ko) | 2008-07-16 | 2017-05-24 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
JP5171595B2 (ja) * | 2008-12-15 | 2013-03-27 | 公立大学法人首都大学東京 | 回路入力及び回路状態評価方法並びに評価装置 |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
CN112906329A (zh) * | 2021-03-19 | 2021-06-04 | 苏州复鹄电子科技有限公司 | 一种基于系统级模拟集成电路设计参数自动优化方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63143901A (ja) * | 1986-12-09 | 1988-06-16 | Kurita Mach Mfg Co Ltd | スラリ−の濃縮装置 |
KR950000273B1 (ko) * | 1992-02-21 | 1995-01-12 | 삼성전자 주식회사 | 불휘발성 반도체 메모리장치 및 그 최적화 기입방법 |
US6253351B1 (en) * | 1998-03-24 | 2001-06-26 | Matsushita Electric Industrial Co., Ltd. | Circuit optimization system |
US6314390B1 (en) * | 1998-11-30 | 2001-11-06 | International Business Machines Corporation | Method of determining model parameters for a MOSFET compact model using a stochastic search algorithm |
-
2002
- 2002-12-27 JP JP2002381336A patent/JP4202120B2/ja not_active Expired - Fee Related
-
2003
- 2003-12-26 CN CNB200310124440XA patent/CN100437592C/zh not_active Expired - Fee Related
- 2003-12-26 KR KR1020030097360A patent/KR100849764B1/ko active IP Right Grant
- 2003-12-29 US US10/745,648 patent/US7155685B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106326507A (zh) * | 2015-06-24 | 2017-01-11 | 中国科学院微电子研究所 | 一种模拟集成电路约束提取方法及系统 |
CN106326507B (zh) * | 2015-06-24 | 2019-07-16 | 中国科学院微电子研究所 | 一种模拟集成电路约束提取方法及系统 |
Also Published As
Publication number | Publication date |
---|---|
JP2004213267A (ja) | 2004-07-29 |
US7155685B2 (en) | 2006-12-26 |
KR100849764B1 (ko) | 2008-07-31 |
US20040139405A1 (en) | 2004-07-15 |
CN100437592C (zh) | 2008-11-26 |
JP4202120B2 (ja) | 2008-12-24 |
KR20040060796A (ko) | 2004-07-06 |
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Owner name: SEIKO INSTR INC. Free format text: FORMER OWNER: LIERLAICI HI-TECH JOINT STOCK CO., LTD.; APPLICANT Effective date: 20060623 |
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Address after: Chiba County, Japan Patentee after: EPPs Lingke Co. Ltd. Address before: Chiba County, Japan Patentee before: SEIKO INSTR INC |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20081126 Termination date: 20191226 |