CN1501490A - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

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Publication number
CN1501490A
CN1501490A CNA031526179A CN03152617A CN1501490A CN 1501490 A CN1501490 A CN 1501490A CN A031526179 A CNA031526179 A CN A031526179A CN 03152617 A CN03152617 A CN 03152617A CN 1501490 A CN1501490 A CN 1501490A
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CN
China
Prior art keywords
circuit arrangement
weld pad
pad
groove
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA031526179A
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Chinese (zh)
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CN100492632C (en
Inventor
高桥幸嗣
明
坂本则明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1501490A publication Critical patent/CN1501490A/en
Application granted granted Critical
Publication of CN100492632C publication Critical patent/CN100492632C/en
Anticipated expiration legal-status Critical
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

A circuit device, to prevent outflow of a solder material 19 from a die pad 11. A groove 14 is made in the peripheral part on the surface of the die pad 11 to surround a region for mounting a semiconductor device 13. In the production step for mounting the semiconductor device 13 on the die pad 11 through the solder material 19, the solder material 19 spreads when the semiconductor device 13 is mounted on the fused solder material 19 but the groove 14 functions as a region for blocking outflow. Consequently, short circuit of the die pad 11 and a bonding pad 12 due to the spread solder material 19 can be prevented.

Description

Circuit arrangement and manufacture method thereof
Technical field
The present invention relates to prevent to connect circuit arrangement and manufacture method thereof that the scolder of semiconductor element flows out.
Background technology
Now, because the circuit arrangement that is installed on the electronic equipment is used on mobile phone, the portable electronic computer etc., so require miniaturization, slimming, lightweight.For example, if be changed to example explanation circuit arrangement with semiconductor device, as general semiconductor device, the plug-in type semiconductor device that now useful common transmission mould encapsulates.This semiconductor device such as Figure 11 are installed on the printed substrate PS.
Have, these plug-in type semiconductor device 61 usefulness tree resin layers 63 cover around the semiconductor chip 62, and draw the conductor terminal 64 that is used to connect the outside from the sidepiece of this tree resin layer 63 again.But these plug-in type semiconductor device 61 its conductor terminals 64 are outwards drawn from tree resin layer 63, and all sizes increase, and do not satisfy miniaturization, slimming and lightweight.Each producer's competition exploitation can realize miniaturization, slimming and light-weighted various structure for this reason.Recently, developed chip-scale CSP that equates with chip size or the size CSP bigger that is called CSP (chip size plug-in unit) than chip.
Figure 12 represent to adopt glass epoxide resin substrate 65 as support substrate, than the bigger CSP66 of chip size.At this, describe as the plug-in unit that transistor chip T has been installed on glass resin substrate 65.
Form first electrode 67, second electrode 68 and weld pad 69 on the surface of this glass epoxide resin substrate 65, form first backplate 70 and second backplate 71 overleaf.And, be electrically connected by above-mentioned first electrode 67 of through hole TH and first backplate 70, second electrode 68 and second backplate 71.Have, fix above-mentioned naked transistor chip T on weld pad 69, transistorized emitter is connected by metal fine 72 with first electrode 67, and transistorized base stage is connected by metal fine 72 with second electrode 68.Have again, on glass epoxide resin substrate 65, tree resin layer 73 is set, make its covering transistor chip T.
Although above-mentioned CSP66 adopts glass epoxide resin substrate 65, yet different with chip-scale CSP, just simply be drawn out to the outside structure that connects the backplate 70,71 of usefulness from chip T, have the low advantage of manufacturing price.Have, as shown in figure 11, above-mentioned CSP66 is installed on the printed substrate PS again.Electrode, the distribution of forming circuit are set on the printed substrate PS, are electrically connected fixing above-mentioned CSP66, plug-in type semiconductor device 61, chip-resistance CR or chip capacity CC etc.And the circuit that constitutes with this printed substrate has been installed in the various devices.
But, the reflow process fixed crystal pipe T that in semiconductor device as described above, melts by the brazing materials such as scolding tin that will be coated on the weld pad 69.Thereby when on the scolding tin that transistor T is placed on fusing, scolding tin flows out from weld pad 69, and the problem of weld pad 69 and other electric pole short circuit takes place.
Have, in order to prevent to flow on second electrode 68 from the scolding tin that weld pad 69 flows out, make the weld pad 69 and second electrode 68 separate the gap, this has caused the whole maximization of device.
Summary of the invention
The present invention produces in view of such problem.Main purpose of the present invention provides a kind of circuit arrangement, and it can prevent that brazing material from flowing out from weld pad when on weld pad semiconductor element being installed with brazing material.
A first aspect of the present invention, circuit arrangement comprises: by the semiconductor element and the almost equal big or small weld pad of formation of brazing material installation; Pad near described weld pad setting; Surround described semiconductor element, around described weld pad, form and prevent the groove that described brazing material flows out; The back side of described weld pad and described pad is exposed, seal the insulating resin of described weld pad, described pad and described semiconductor element.
A second aspect of the present invention, described groove forms than the thickness of described weld pad more shallowly.
A third aspect of the present invention, the described insulating resin of filling in described groove.
A fourth aspect of the present invention, described semiconductor device are the IC chips.
A fifth aspect of the present invention, described semiconductor device is electrically connected with desirable described conduction artwork by lametta.
A sixth aspect of the present invention, described brazing material are scolding tin or Ag welding paste.
A seventh aspect of the present invention replaces described brazing material with insulating binder.
A eighth aspect of the present invention forms groove again in the described groove area surrounded by described weld pad.
A ninth aspect of the present invention forms groove by clathrate in by the described groove area surrounded of described weld pad.
A tenth aspect of the present invention, the manufacture method of circuit arrangement comprises: the operation of preparing conductive foil; When forming weld pad and pad, form the operation of groove, wherein said weld pad and pad form on described conductive foil and constitute a plurality of circuit arrangement portion than the also shallow separation trough of its thickness, and it is also more shallow than described separation trough on described weld pad that described groove surrounds the zone of semiconductor element of pre-determined constant; On described weld pad with the fixing operation of semiconductor element of brazing material; Described semiconductor element is carried out the operation that lead is connected with desirable described pad; Cover described semiconductor element,, fill the common molding procedure of described separation trough and described groove with the common moulding of insulating resin; Remove the described conductive foil back side, up to the operation of exposing described insulating resin; By with described insulating resin stripping and slicing, be separated into the operation of each circuit arrangement.
A eleventh aspect of the present invention, described groove forms than described weld pad also shallowly.
A twelveth aspect of the present invention, described brazing material are scolding tin or Ag welding paste.
A thirteenth aspect of the present invention replaces described brazing material with insulating binder.
Description of drawings
Fig. 1 (A) is that plane graph, Fig. 1 (B) of explanation circuit arrangement of the present invention is profile;
Fig. 2 (A) is that back view, Fig. 2 (B) of explanation circuit arrangement of the present invention is profile;
Fig. 3 (A) is that profile, Fig. 3 (B) of explanation circuit arrangement of the present invention is plane graph;
Fig. 4 (A) is that profile, Fig. 4 (B) of explanation circuit arrangement manufacture method of the present invention is plane graph;
Fig. 5 is the profile of the manufacture method of explanation circuit arrangement of the present invention;
Fig. 6 (A) is that profile, Fig. 6 (B) of explanation circuit arrangement manufacture method of the present invention is plane graph;
Fig. 7 (A) is that profile, Fig. 7 (B) of the manufacture method of explanation circuit arrangement of the present invention is plane graph;
Fig. 8 (A) is that profile, Fig. 8 (B) of the manufacture method of explanation circuit arrangement of the present invention is plane graph;
Fig. 9 (A) is that profile, Fig. 9 (B) of the manufacture method of explanation circuit arrangement of the present invention is plane graph;
Figure 10 is the plane graph of the manufacture method of explanation circuit arrangement of the present invention;
Figure 11 is the profile of the existing circuit arrangement of explanation;
Figure 12 is the profile of the existing circuit arrangement of explanation.
Embodiment
(first execution mode of the structure of circuit arrangement 10 is described)
With reference to Fig. 1, the formation of circuit arrangement 10 of the present invention etc. is described.Fig. 1 (A) is the plane graph of circuit arrangement 10, and Fig. 1 (B) is the profile of circuit arrangement 10.
With reference to Fig. 1 (A) and Fig. 1 (B), circuit arrangement 10 has following structure.Promptly be made of weld pad 11, pad 12, groove 14, insulating resin 16, its weld pad 11 forms with the semiconductor element of installing 13 big or small much at one by brazing material 19; Its pad 12 is provided with near weld pad 11; Its groove 14 surrounds semiconductor element 13, forms and prevent brazing material 19 outflows around weld pad 11; Its insulating resin 16 exposes the back side of weld pad 11 and pad 12, sealing weld pad 11, pad 12 and semiconductor element 13.Below such element that respectively constitutes is described.
Weld pad 11 is conduction artworks that semiconductor element 13 is installed, and is made by metals such as Copper Foils, exposes the back side and imbeds in the insulating properties resin 16.And the plane that forms weld pad 11 is bigger than the semiconductor element of installing, and forms groove 14 around it.At Fig. 1 (A), form weld pad 11 at central portion, be installed in the semiconductor element of making by the IC chip 13 by brazing material 19, have again, forming electroplating film with the surface of the corresponding weld pad 11 of scope that semiconductor element 13 is installed with Ag etc.
Pad 12 is the conduction artworks in conjunction with lametta 15, exposes the back side and imbeds in the insulating properties resin 16.At this, the weld pad 11 that is enclosed in the central portion formation of device forms the pad 12 of a plurality of circles.At Fig. 1 (A), electric independent setting of the pad 12A that forms in the left and right sides of weld pad 11.And the pad 12B and the weld pad 11 that form in the both sides up and down of weld pad 11 are electrically connected.And, for the associativity of the metal fine that improves combination, form electroplating film with Ag etc. on the surface of pad 12.
By the mounted on surface semiconductor element 13 of brazing material 19 at weld pad 11.At this, being installed in the semiconductor element by brazing material 19 also is bigger IC chip.And, be electrically connected electrode and the pad 12 that forms on the surface of semiconductor element 13 by lametta 15.Have again and pad 12 that weld pad 11 is electrically connected also is electrically connected by lametta 15 and semiconductor element 13.At this, can use conductivity bond materials such as scolding tin or silver soldering paste as brazing material.And, also can semiconductor element 13 be installed on the weld pad 11 with insulating resin.
Groove 14 forms around weld pad 11 around semiconductor element 13, and fills insulating resin 16.The thickness of the depth ratio weld pad 11 of formation groove 14 is also shallow.Form groove 14 by surrounding the zone that semiconductor element 13 is installed, can prevent in the operation on brazing material 19 tops that semiconductor element 13 are installed in fusing that brazing material 19 from flowing out from weld pad 11.Particularly, even brazing material 19 flows out from the zone that semiconductor element 13 is installed, brazing material 19 also stores in groove 14.Thereby groove 14 performances are as preventing the function of brazing material 19 from the prevention zone that weld pad 11 flows out.In addition, the manufacture method of relevant groove 14 will be told about in the back, groove 14 with separation trough 16 by the etching manufacturing.Thereby the sectional width that forms groove 14 is narrower than the width of separation trough 16.
Insulating properties resin 16 exposes the back side of weld pad 11 and pad 12 and seals all.Have again, in the groove 14 that on weld pad 11 surfaces, forms also filling insulating properties resin 16.At this, seal semiconductor element 13, metal fine 15, weld pad 11 and pad 12.Material as insulation resin 16 can adopt by thermohardening resin that transmits mould formation or the thermoplasticity resin that passes through injection molded.
Brazing material 19 is welding pastes of conductivity such as scolding tin or silver soldering paste, has the effect in conjunction with semiconductor element 13 and weld pad 11.Brazing material 19 is conductive materials, so the back side of semiconductor element 13 and weld pad 11 forms and be electrically connected.Have, the pad 12B that forms in the both sides up and down of weld pad 11 electrically is connected with weld pad 11 again.Thereby, by connecting the electrode and the pad 12B of semiconductor element 13 with metal wire, just can be electrically connected the circuit that on the surface of semiconductor element 13, forms and the back side of semiconductor element 13.
With reference to Fig. 2, the outer electrode 17 that the back side at circuit arrangement is formed describes.Outer electrode 17 forms at the back side of the pad 12 that surrounds weld pad 11 settings.And, also be provided with a plurality of outer electrodes at the back side of weld pad 11.Thereby, outer electrode 17 in the whole zone at circuit arrangement 10 back sides rectangular equally spaced be provided with a plurality of.Therefore, can reduce stress on circuit arrangement 10 being installed in mounted substrate such as main substrate the time by outer electrode 17 to outer electrode 17 effects.
With reference to Fig. 2 (B), the position of the outer electrode 17 that forms at the back side of weld pad 11 and size are limited by the peristome of protective layer 18.And the position of the outer electrode 17 that forms at the back side of pad 12 forms with the back side of size by pad 12.Metals such as copper as the material of pad 12 are the good materials of wetability.Limit the position and the size of outer electrode 17 by this wetability.Like this, be limited to the position and the size of the outer electrode 17 that the back side of pad 12 forms by wetability, even the peristome position deviation of protective layer 18 also can form the good outer electrode of precision 17 with pad 12.
Feature of the present invention is to form groove 14 to surround semiconductor element 13 around weld pad 11.Promptly after on the brazing material 19 that has melted semiconductor element 13 being installed, brazing materials such as weight 19 by semiconductor element 13 spread towards periphery, because the brazing material 19 of diffusion stores in groove 14 towards periphery, can prevent that therefore brazing material 19 from flowing out from the surface of weld pad 11.Thereby can prevent the brazing material 19 that flows out from contacting and short circuit between the pad that produces with pad 12.Therefore, can form weld pad 11 with the semiconductor element of on weld pad 11, installing 13 about the samely.And then can make weld pad 11 and pad 12 near forming, circuit arrangement 10 overall dimensions are diminished.And, owing to, weld pad 11 and insulating resin 16 contacts area are increased, can improve the adhesion of weld pad 11 and insulating resin 13 by on the surface of weld pad 11, forming groove 14 like this.
With reference to Fig. 3, the circuit arrangement 10A that another is routine is described.Fig. 3 (A) is the profile of circuit arrangement 10A, and Fig. 3 (B) is the X-X ' plane graph of Fig. 3 (A).Circuit arrangement 10A has and circuit arrangement illustrated in fig. 1 10 structure much at one, in by 14 area surrounded of the groove that forms on the surface of weld pad 11, further forms clathrate groove 14A.
It is purpose that groove 14 flows out from the surface of weld pad 11 with the brazing material 19 that prevents fixing semiconductor element 13, be located at weld pad 11 around.And at this, groove 14A forms clathrate in groove 14 area surrounded.Form cancellate groove 14A and also have the section shape identical with groove 14.Owing to can store more brazing material 19 in groove 14 by the cancellate groove 14 of such formation, flow out from the surface of weld pad 11 so can prevent brazing material 19.In addition, because weld pad 11 further increases with insulating resin 16 contacts area, can improve the adhesion of weld pad 11 and insulating resin 16.
Narration is provided with the advantage of groove 14.The machinery of supply brazing materials such as brazing material 19 usefulness distributors is coated on the surface of weld pad 11, the minimum coating weight of the brazing material 20 that can be supplied with by the decision of this distributor.Thereby the minimum coating weight of distributor than the situation big for the amount that semiconductor element 13 is installed in the desired brazing material of wanting 19 on the weld pad 11 under, the problem that exists brazing material 19 to flow out from the surface of weld pad 11.Therefore, by being set, groove 14 can prevent that brazing material 19 from flowing out.
(second embodiment of the manufacture method of circuit arrangement 10 is described)
At present embodiment, the manufacture method of circuit arrangement 10 is described.In present embodiment, the operation manufacturing that circuit arrangement 10 usefulness are following, that is: the operation of preparation conductive foil 40; Form the operation of weld pad 11 and pad 12, it forms on conductive foil 40 and constitutes a plurality of circuit arrangement portion 45 than the shallow separating tank 16 of the thickness of conductive foil 40; Form the operation of groove 14 on weld pad 11, it surrounds the zone of pre-determined constant semiconductor element 13, and this groove is also more shallow than separation trough 16; Installation procedure, it installs semiconductor element 13 by brazing material 19 on weld pad 11; The wire-bonds operation, it carries out the wire-bonds of semiconductor element 13 and desirable pad 12; Common molding procedure, it covers semiconductor element 13, with insulating resin 16 common moulding, fills separation trough 16 and groove 14; Clearing process, it removes the back side of conductive foil 40, up to exposing insulating resin 16; Separate operation, it is separated into each circuit arrangement 10 by cutting insulating resin 16.Below with reference to Fig. 4～Figure 10 each operation of the present invention is described.
As Fig. 4～shown in Figure 6, first operation of the present invention is to prepare conductive foil 40 to form weld pad 11 and pads 12, promptly forms to constitute a plurality of circuit arrangement portion 45 than the shallow separating tank 16 of its thickness on conductive foil 40.Simultaneously, on weld pad 11, surround the zone formation groove 14 also more shallow of pre-determined constant semiconductor element 13 than separation trough 16.
In this operation,, prepare the conductive foil 40 of sheet at first as Fig. 4 (A).This conductive foil 40 will consider the tack, associativity, plating of brazing material and select its material, as material to adopt with Cu be the conductive foil of main material, be the conductive foil of main material or the conductive foil that forms by the alloy of Fe-Ni etc. etc. with Al.
The thickness of conductive foil will be considered later etching work procedure, is preferably 10 μ m～300 μ m degree, however 300 μ m are above, below the 10 μ m also substantially can, as described later, can form just than the shallow separating tank 16 of the thickness of conductive foil 40.
Have, the conductive foil 40 of sheet can width in accordance with regulations for example be prepared to that 45mm is rolled into tubular, is transported to each operation of back more again, also can prepare the conductive foil 40 that in accordance with regulations size is cut into short volume shape, is transported to each operation described later again.
Shown in Fig. 4 (B), on the conductive foil 40 of short volume shape, leave the square 42 that spacing parallel arranging four～five a plurality of circuit arrangement of formation portions 45 particularly.42 of each squares gap 43 is set, is used for being absorbed in forming process because the stress of the conductive foil 40 that heat treated produces.Have again, with predetermined distance indicator hole 44 was set on the end, be used to determine position in each operation in last next week of conductive foil 40.Then, form the conduction artwork.
At first, as shown in Figure 5, form fast light protective layer (corrosion resistant etching mask) PR on conductive foil 40, the mould that charts on fast light protective layer exposes the conductive foil of removing outside the zone that becomes conduction artwork 51 40.And shown in Fig. 6 (A), selectively the etching conductive foil 40.At this, conduction artwork 51 forms the weld pad 11 and the pad 12 of each circuit arrangement portion 45.
With reference to Fig. 6 (A), the peristome of fast light protective layer is set in the place that forms groove 14 and separation trough 16.And the peristome width in the place of formation groove 14 is narrower than the local width that forms separation trough 16.Particularly, its width forms below half.Owing to remove conductive foil 40 with etching and have isotropism, so by form the peristome of the fast light protective layer corresponding with groove 14 so very narrowly, can be than the degree of depth of the also shallow landform grooving 14 of separation trough 16.In addition, above-mentioned etching work procedure can be undertaken by conductive foil 40 is immersed in the etching solution.
Expression forms the conduction artwork 51 of weld pad 11 and pad 12 among Fig. 6 (B).The corresponding square 42 that amplifies of this figure in Fig. 4 (B) expression.A hachure partly is a circuit arrangement portion 45, and a plurality of circuit arrangements 45 in the two column matrix shape ground assortments of two row in a square 42, and identical conduction artwork 51 is set on each circuit arrangement 45.On the surrounding of each square, establish the artwork 46 of frame shape, leave the telltale mark 47 when a bit at interval cutting being set in the inboard of Figure 46.The artwork 46 of frame shape is used for mould chimeric, and has the effect of reinforced insulation resin 16 behind the back etched of conductive foil 40.Have, in each circuit arrangement portion, that pad 12 that forms in the both sides up and down of weld pad 11 and weld pad 11 form is integrated, both also are electrically connected again.
As shown in Figure 7, second operation of the present invention is by brazing material 19 semiconductor element 13 to be fixed on the weld pad 11 of each circuit arrangement portion 45.
With reference to Fig. 7 (A), semiconductor element 13 is installed on the weld pad 11 by brazing material 19.At this,, use conductions such as scolding tin or Ag welding paste to stick with paste as brazing material 19.This operation is because brazing material 19 is molten states, by semiconductor element 13 being placed on the top of brazing material 19, by the weight of semiconductor element 13 etc. brazing material 19 spread towards periphery.At this, owing to around weld pad 11, form groove 14, make its zone that surrounds bearing semiconductor element 13, so the brazing material 19 of diffusion does not flow out from weld pad 11.Because the brazing material 19 of arrival slot 14 becomes the state that flows into groove 14, so groove 14 performances are as the function in the prevention zone that stops scolding tin to flow out.In addition, also can be installed in semiconductor element 13 on the weld pad 11 with insulating resin.
The 3rd operation of the present invention is that the lead that carries out semiconductor element 13 and desirable pad 12 is connected as shown in Figure 8.
Particularly, by hot pressing with ball bonding and use the electrode and the desirable pad 12 of the semiconductor element 13 of the blanket wire-bonds tipping of hyperacoustic V-arrangement weldering in each circuit arrangement portion.
The 4th operation of the present invention is to cover semiconductor element 13 as shown in Figure 9, with insulating resin 16 common moulding, fills separation trough 16 and groove 14.
Shown in Fig. 9 (A), fully covered semiconductor element 13, a plurality of weld pad 11 and pad 12 at this operation insulation resin 16, in separating tank 16 and groove 14 filling insulation resin 16, and combine securely with separating tank 41 is chimeric.And, support weld pad 11 and pad 12 by insulation resin 16.
Have again, can finish by transmitting mold forming method, injection molding method or casting in this operation.As the resin material, thermohardening resins such as epoxy resin are with transmitting mold forming method, thermoplasticity resin injection molding methods such as polyimides, polyphenylene sulfide.
Have again, when this operation is transmitted mold forming or injection mo(u)lding, as shown in Fig. 9 (B) circuit arrangement portion 63 folding and unfoldings of each square 42 in a common mould, each square carries out common moulding with a kind of insulation resin 16.Therefore, with present transmission mold forming etc. like that with each circuit arrangement portion individually the method for moulding compare, realized reducing significantly the resin use amount.
This operation is characterised in that, before covering insulation resin 16, becomes support substrate as the conductive foil 40 of conduction artwork 51.Prior art is to adopt originally to form the conduction artwork with regard to unnecessary support substrate, yet the conductive foil 40 that becomes support substrate in the present invention is the materials as necessity of electrode.Therefore, have the advantage that very to economize constituent material and make, and also can realize reducing cost.
Have again, because it is more shallow than the thickness of conductive foil to form separating tank 41, therefore conductive foil 40 is not separated into conduction artwork 51 one by one, thereby, can integrally handle the conductive foil 40 of sheet, have the operation feature as snug as a bug in a rug of when profiled insulation resin 16, transporting, on mould, installing to mould.
The 5th operation of the present invention is to remove the back side of conductive foil 40 up to the operation of exposing the resin that insulate.
This operation is the back side of removing conductive foil 40 with chemical method or physical method, is separated into the operation of conduction artwork 51.This operation is undertaken by grinding, etching, laser evaporation metal etc.
Comprehensive wet etching conductive foil 40 in experiment makes insulation resin 16 expose from separating tank 41.Dot this at Fig. 9 (A) and expose face.As a result, be separated into conduction artwork 51, be formed on insulation and expose on the resin 16 and conduct electricity the structure at the back side of artwork 51.That is, become surface that is filled in the insulation resin 16 in the separating tank 41 and the consistent in fact structure in surface that conducts electricity artwork 51.
Have again, conduct electricity the surface treatment of artwork 51, obtain final structure for example shown in Figure 1.That is, on the conduction artwork 51 that exposes, cover electric conducting materials such as scolding tin as required, finish circuit arrangement.
In addition, in this operation, the insulating resin 16 of filling separation trough 16 exposes overleaf, and the insulating resin 16 of filling slot 14 does not expose overleaf.
As shown in figure 10, the 6th operation of the present invention is that insulation resin 16 is separated by each circuit arrangement 45 cutting.
In this operation, square 42 usefulness vacuum suction on the mounting table of cutter sweep, with the insulation resin 16 of cutting blade 49 along line of cut (chain-dotted line) the cutting and separating groove 41 between each circuit arrangement 45, are separated into independent circuit arrangement.
In this operation, cutter 49 carry out with the cutting depth that almost cuts off insulating properties resin 16, resemble with roller afterwards at taking-up square 42 from cutter sweep and cut apart chocolate with its disconnection just.Confirming the telltale mark 47 at each square of above-mentioned first operation setting during cutting in advance, is that benchmark carries out with telltale mark 47.
Below the well-known cutting mode of explanation after longitudinal direction has cut whole lines of cut, makes 90 ° of mounting table rotations, cuts along the line of cut 70 of transverse direction.
The effect of invention
Can produce following effect in the present invention.
The first, in the present invention, surround semiconductor element 13 and at the surrounding edge of weld pad 11 groove 14 is set, Prevented from flowing out in conjunction with the brazing material 19 of semiconductor element 13, therefore can prevent because the soldering of flowing out Material 19 causes short circuit between the conduction artwork.
The second, because can prevent that brazing material 19 from flowing out by groove 14, so can make weld pad 11 and knot Close pad 12 and approach, can make the device integral miniaturization.
The 3rd, in the operation that semiconductor element 13 is installed, be located at pad 12 groove 14 on every side and do Prevention zone performance function for stoping brazing material to flow out can prevent because brazing material 19 flows to The outside causes conducting electricity the short circuit between the artwork.

Claims (13)

1, a kind of circuit arrangement is characterized in that, comprising: by the semiconductor element and the almost equal big or small weld pad of formation of brazing material installation; Pad near described weld pad setting; Surround described semiconductor element, around described weld pad, form and prevent the groove that described brazing material flows out; The back side of described weld pad and described pad is exposed, seal the insulating resin of described weld pad, described pad and described semiconductor element.
2, circuit arrangement as claimed in claim 1 is characterized in that, described groove forms than the thickness of described weld pad more shallowly.
3, circuit arrangement as claimed in claim 1 is characterized in that, the described insulating resin of filling in described groove.
4, circuit arrangement as claimed in claim 1 is characterized in that, described semiconductor device is the IC chip.
5, circuit arrangement as claimed in claim 1 is characterized in that, described semiconductor element is electrically connected with desirable described conduction artwork by lametta.
6, circuit arrangement as claimed in claim 1 is characterized in that, described brazing material is scolding tin or Ag welding paste.
7, circuit arrangement as claimed in claim 1 is characterized in that, replaces described brazing material with insulating binder.
8, circuit arrangement as claimed in claim 1 is characterized in that, forms groove again in the described groove area surrounded by described weld pad.
9, circuit arrangement as claimed in claim 1 is characterized in that, forms groove by clathrate in by the described groove area surrounded of described weld pad.
10, a kind of manufacture method of circuit arrangement is characterized in that, comprising: the operation of preparing conductive foil; When forming weld pad and pad, form the operation of groove, wherein said weld pad and pad form on described conductive foil and constitute a plurality of circuit arrangement portion than the also shallow separation trough of its thickness, and it is also more shallow than described separation trough on described weld pad that described groove surrounds the zone of semiconductor element of pre-determined constant; On described weld pad with the fixing operation of semiconductor element of brazing material; Described semiconductor element is carried out the operation that lead is connected with desirable described pad; Cover described semiconductor element,, fill the common molding procedure of described separation trough and described groove with the common moulding of insulating resin; Remove the described conductive foil back side, up to the operation of exposing described insulating resin; By with described insulating resin stripping and slicing, be separated into the operation of each circuit arrangement.
11, the manufacturing side of circuit arrangement as claimed in claim 10 separation method is characterized in that, described groove forms than described weld pad also shallowly.
12, the manufacture method of circuit arrangement as claimed in claim 10 is characterized in that, described brazing material is scolding tin or Ag welding paste.
13, the manufacture method of circuit arrangement as claimed in claim 10 is characterized in that, replaces described brazing material with insulating binder.
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JP4093818B2 (en) 2008-06-04
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TW200405779A (en) 2004-04-01
TWI240603B (en) 2005-09-21

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