JP6500562B2 - Semiconductor module - Google Patents

Description

  The present disclosure relates to a semiconductor module.

  Conventionally, a switching element unit using a semiconductor switching element is known (see, for example, Patent Document 1). For example, in the switching element unit described in Patent Document 1, the capacitor connection electrode and the inter-element connection electrode are disposed on the element mounting surface of the smoothing capacitor, the switching elements are disposed on these, and one switching is performed. The terminal on the upper surface of the element and the inter-element connection electrode on the above-described element mounting surface are connected by a columnar connection member.

JP, 2013-179261, A

  However, in the configuration described in Patent Document 1 described above, the columnar connection member connecting the terminal and the electrode in the thickness direction of the switching element maintains a certain degree of mechanical strength during manufacturing of the switching element unit. It has to be configured much higher than the switching element. In such a configuration, the wiring distance is extended, the inductance is increased, and it is difficult to miniaturize the switching element unit.

  Therefore, the present disclosure aims to provide a semiconductor module that can realize low loss while having a low inductance structure and can achieve miniaturization.

In order to achieve the above object, a semiconductor module according to an aspect of the present disclosure includes: a first insulating substrate;
First and second connection electrodes provided apart from each other on the first insulating substrate;
First and second semiconductor elements respectively provided on the first and second connection electrodes;
Third and fourth connection electrodes respectively provided on the first and second semiconductor elements;
Columnar wiring electrically connecting the first connection electrode and the fourth connection electrode;
The first semiconductor element and the third connection electrode, the columnar wiring, and the second semiconductor element and the fourth connection electrode are individually accommodated , and are opposed to the first insulating substrate. The first semiconductor element and the third connection electrode, the columnar wiring, the second semiconductor element, and the fourth semiconductor device are provided in the housing portion. And a second insulating substrate joined to the first insulating substrate in a state in which the connection electrode is accommodated.

  According to the present disclosure, the semiconductor module can be miniaturized.

It is a figure showing the section composition of an example of the semiconductor module concerning this embodiment. It is a disassembled block diagram of an example of the semiconductor module concerning this embodiment. It is a figure showing an example of the conventional semiconductor module concerning a comparative example. It is explanatory drawing of the structure which provided the cavity which absorbs the dimensional tolerance of the semiconductor module which concerns on this embodiment. FIG. 4A is a view showing a configuration example in which a cavity is provided on the side of the bonding material. FIG.4 (b) is the figure which showed the structural example which provided the cavity of the groove shape different from Fig.4 (a). FIG. 4C is a view showing a configuration example in which a cavity is provided in the connection electrode. It is explanatory drawing of the structure which reduces the stress by the thermal expansion coefficient difference of the semiconductor module which concerns on this embodiment. It is the figure which showed the structural example of the gate wiring different from FIG. It is a figure which shows the planar-arrangement structure of the upper part of an example of the semiconductor module which concerns on this embodiment. FIG. 7A is a view showing a cross-sectional configuration of an example of the semiconductor module according to the present embodiment corresponding to FIGS. 7B to 7D. FIG.7 (b) is the figure which showed the structure of the CC 'horizontal cross section of Fig.7 (a). FIG.7 (c) is the figure which showed the structure of the BB 'horizontal cross section of Fig.7 (a). FIG.7 (d) is the figure which showed the structure of the AA 'horizontal cross section of Fig.7 (a). It is a figure which shows the planar-arrangement structure of the lower part of an example of the semiconductor module concerning this embodiment. Fig.8 (a) is a figure which shows the cross-sectional structure of an example of the semiconductor module concerning this embodiment made to respond | correspond to FIG.8 (b)-(d). FIG.8 (b) is the figure which showed the structure of the FF 'horizontal cross section of Fig.8 (a). FIG.8 (c) is the figure which showed the structure of the EE 'horizontal cross section of Fig.8 (a). FIG. 8D is a view showing the configuration of the horizontal cross section taken along the line DD 'of FIG. 8A. It is a figure showing the section composition in each position on the plane of the example of the semiconductor module concerning this embodiment. FIG. 9A is a top view showing a plan configuration of an example of the semiconductor module according to the present embodiment corresponding to FIGS. 9B to 9E. FIG.9 (b) is the figure which showed the structure of the JJ 'longitudinal cross section of Fig.9 (a). FIG.9 (c) is the figure which showed the structure of the II 'longitudinal cross section of Fig.9 (a). FIG.9 (d) is the figure which showed the structure of the HH 'longitudinal cross section of Fig.9 (a). FIG.9 (e) is the figure which showed the structure of the GG 'longitudinal cross section of Fig.9 (a).

  Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

  FIG. 1 is a view showing a cross-sectional configuration of an example of a semiconductor module according to the present embodiment. As shown in FIG. 1, the semiconductor module according to the present embodiment includes a first substrate 10, a second substrate 20, first and second semiconductor elements 31 and 32, and first to fourth ones. The connection electrodes 41 to 44, the columnar wirings 50 to 52, the gate wiring 60, the bonding material 70, and the ceramic capacitor 80 are provided. Further, a gap 90 may be formed between the second substrate 20 and the ceramic capacitor 80. Furthermore, the semiconductor module according to the present embodiment may include the cooler 100 as a related component. In the following description, each component may be distinguished only by the reference numeral without the words “first, second, third, fourth” or the like being attached to each component.

  The first substrate 10 is made of an insulating material. Further, since the first substrate 10 can be heated to a high temperature by the heat generation of the semiconductor elements 31 and 32, it is preferable that the first substrate 10 be made of a material having high heat resistance. Examples of the material having insulating properties and high heat resistance include ceramics. Thus, the first substrate 10 may be made of, for example, a ceramic. Further, in FIG. 1, the first substrate 10 is disposed on the surface of the cooler 100. Thus, the first substrate 10 efficiently dissipates the heat generated by the semiconductor devices 31 and 32, and efficiently transfers the cooling heat from the cooler 100 to the semiconductor devices 30 and 31. Also, it may be composed of a material having high heat conductivity. Even if the first substrate 10 is made of a ceramic, such selection is possible because there are various materials in the ceramic.

  The first substrate 10 is formed in a flat plate shape in order to install flat connection electrodes 41 and 42 on the surface. Moreover, it is preferable that the first substrate 10 be configured as thin as possible from the viewpoint of the above-described improvement in thermal conductivity and the viewpoint of miniaturization of the semiconductor module. Therefore, the first substrate 10 may be thinner than the second substrate 20 and may be thinner than the semiconductor elements 30 and 31.

  The semiconductor elements 31 and 32 are configured as semiconductor chips that can be used as switching elements, and for example, a bipolar transistor, a MOS transistor including a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), etc. It may be composed of a transistor. Thus, the semiconductor elements 31 and 32 are configured to have control terminals such as gates and bases. The material of the semiconductor elements 31 and 32 may be generally used Si or the like, or may be a wide band gap semiconductor such as SiC. The semiconductor elements 31 and 32 can be made of various materials depending on the application.

  The semiconductor elements 31 and 32 have terminals (input terminal / output terminal) on both sides. Therefore, the first semiconductor element 31 is physically and electrically not only via the first connection electrode 41 disposed on the lower surface and the third connection electrode 43 disposed on the upper surface, and the bonding material 70. Are also connected. Similarly, the second semiconductor element 32 is also physically and electrically connected to the second connection electrode 42 disposed on the lower surface and the fourth connection electrode 44 disposed on the upper surface through the bonding material 70. Be done.

  The semiconductor elements 31 and 32 may be connected to a diode element as necessary, and may be configured as a set with the diode element. For example, in the case where the semiconductor module is configured as a DC / DC converter, the semiconductor elements 31 and 32 and the diode element may be configured in pairs. However, in the present embodiment, for easy understanding, only the semiconductor elements 31 and 32 are shown to explain the semiconductor module.

  The connection electrodes 41 to 44 are wiring connection means for leading out and wiring the respective terminals of the semiconductor elements 31 and 32, and are formed in a flat plate shape using a conductive metal material for wiring such as Al, Cu or the like. As shown in FIG. 1, the first connection electrode 41 is connected to the columnar wiring 50 by drawing out the terminal on the lower surface of the first semiconductor element 31 to the second semiconductor element 32 side (center side), The third connection electrode 43 is connected to the columnar electrode 51 by drawing out the terminal on the upper surface of the first semiconductor element 31 to the outside. Similarly, the second connection electrode 42 is connected to the pillar wiring 52 by drawing out the terminal on the lower surface of the second semiconductor element 32 to the outside, and the fourth connection electrode 44 is connected to the second semiconductor element 32. The terminal on the upper surface is drawn to the first semiconductor element 31 side (central side) and connected to the columnar wiring 50.

  The columnar wirings 50 to 54 are wirings extending in the thickness direction of the semiconductor elements 31 and 32, and are wirings for electrically connecting the upper layer and the lower layer. Therefore, the columnar wirings 50 to 54 are configured using a conductive metal material for wiring, such as Al or Cu, similarly to the connection electrodes 41 to 44, but the shape is in the thickness direction of the semiconductor elements 31 and 32. It has an extending columnar shape.

  The columnar wiring 50 electrically connects the first connection electrode 41 and the fourth connection electrode 44 in the central region. The columnar wiring 51 is electrically connected to the third connection electrode 43 at the end outside the first semiconductor element 31, and this electrical connection is drawn out to the outer upper part of the semiconductor module, and further above It is connected to the columnar wiring 53. In addition, the columnar wiring 52 is electrically connected to the second connection electrode 42 at the end outside the second semiconductor element 32, and this connection is drawn out to the outer upper part of the semiconductor module, and further upward It is connected to the columnar wiring 54.

  The gate wiring 60 is connected to the gate terminals of the semiconductor elements 31 and 32, and is a wiring for drawing out the gate to the outside. Therefore, the gate wiring 60 may also be made of a conductive metal for wiring such as Al or Cu. The gate wiring 60 may be drawn out above the ceramic capacitor 80 through the second substrate 20 and the ceramic capacitor 80 as shown in FIG. In this case, a through hole is formed at a predetermined position of second substrate 20 and ceramic capacitor 80, and gate interconnection 60 is drawn out through the formed through hole. In the case where the gate interconnection 60 penetrates the ceramic capacitor 80, the gap 90 between the ceramic capacitor 80 and the upper surface of the second substrate 20 may not be particularly provided. In this case, the gap 90 may be provided as needed.

  The gate wiring 60 may be drawn as a wiring pattern on the upper surface of the second substrate 20 without being penetrated through the ceramic capacitor 80 and drawn outside. In this case, it is preferable to provide a gap 90 between the upper surface of the second substrate 20 and the ceramic capacitor 80 to facilitate the installation of the gate wiring 60.

  The bonding material 70 is bonding means for physically bonding the semiconductor elements 31 and 32 and the connection electrodes 41 to 44 and for electrically connecting them. As the bonding material 70, various bonding materials may be used as long as the semiconductor elements 31, 32 and the connection electrodes 41 to 44 can be physically and electrically connected, but for example, silver nano paste or solder may be used. These bonding materials 70 are excellent in conductivity and bonding property, and can be suitably used for bonding the semiconductor elements 31 and 32 and the connection electrodes 41 to 44.

  In particular, silver nanopaste has a low melting point at the time of the first melting, and once fixed, has the property of increasing the melting point, so that bonding can be performed at a relatively low temperature, for example, lower than solder. Since it has high temperature resistance, it can be said that the bonding material 70 is more advantageous than solder.

  The second substrate 20 functions as an insulating support member that insulates and holds the first semiconductor element 31, the columnar wiring 50, and the second semiconductor element 32. The second substrate 20 has a recess-shaped receiving portion for separately receiving each of the first semiconductor element 31, the columnar wiring 50 and the second semiconductor element 20, and the first semiconductor element 31 is provided in the receiving portion. And the second semiconductor element 20 are housed and held.

  FIG. 2 is an exploded configuration view of an example of the semiconductor module according to the present embodiment. As shown in FIG. 2, the second substrate 20 accommodates the accommodating portion 21 capable of accommodating the first semiconductor element 31, the accommodating portion 22 capable of accommodating the second semiconductor element 32, and the columnar wire 50. And a possible housing 23. The housing portion 21 is configured to be capable of housing the third connection electrode 21 in addition to the first semiconductor element 31, and the housing portion 22 is a fourth connection electrode other than the second semiconductor element 32. 44 is also configured to be accommodated. Further, as shown in FIG. 2, the second substrate 20 may further include an accommodating portion 24 capable of accommodating the columnar wires 51 and an accommodating portion 25 capable of accommodating the columnar wires 52 as necessary. . Here, the housing portions 21 to 23 have a recess shape having a plurality of side surfaces that are recessed in the vertical direction and surround the bottom surface and the bottom surface. On the other hand, the housing portions 24 and 25 have a hollow shape having a hollow only in the horizontal direction, and a bottom surface and only one side surface or only a side surface.

  In FIG. 2, the connection electrodes 43 and 44 and the columnar wirings 50 to 52 are already provided in the housings 21 to 25. As described above, the connection wirings such as the connection electrodes 43 and 44 and the columnar wirings 50 to 52 are first disposed inside the housings 21 to 25, and only the semiconductor elements 31 and 32 are housed later in the housings 21 and 22 respectively. However, the semiconductor module may be manufactured according to a manufacturing procedure in which the first substrate 10 and the second substrate 20 are bonded. The connection wirings such as the connection electrodes 43 and 44 and the columnar wirings 50 to 52 can be installed in the housing portions 21 to 25 of the second substrate 20 without using the bonding material 70, but the semiconductor elements 31 and 32 are accommodated. In the case of being accommodated in the portions 21 and 22, the bonding of the third electrode 43 and the first semiconductor element 31 by the bonding material 70 and the bonding material 70 of the fourth electrode 44 and the second semiconductor element 32. Such a manufacturing procedure may be used because bonding is required. In addition, the depths of the housing portions 21 to 23 are the electrical connection between the first semiconductor element 31 and the connection electrodes 41 and 43 when the first substrate 10 and the second substrate are joined, the second The depth is set such that the electrical connection between the semiconductor element 32 and the connection electrodes 42 and 44 and the electrical connection between the connection electrode 41 and the columnar wiring 50 and the connection electrode 44 are realized.

  The second substrate is similar to the first substrate 10 in that it needs to be made of an insulating material. Further, as in the case of the first substrate 10, since the semiconductor elements 31, 32 can be heated to a high temperature, it is preferable to be made of a material having heat resistance. As described above, since the ceramic has high insulation and heat resistance, the second substrate 20 may also be made of ceramic.

  However, in the second substrate 20, the accommodating portions 21 to 25 having a size capable of accommodating the semiconductor elements 31 and 32 are formed. Therefore, the second substrate 20 is preferably made of a material excellent in processability. On the other hand, unlike the first substrate 10, the second substrate 20 is not in contact with the cooler 100, and has no role of transferring the cooling heat of the cooler 100. Therefore, the second substrate 20 may be made of a material having better processability than the first substrate 10. As described above, since there are various materials for ceramics, appropriate materials can be selected. If the first substrate 10 is made of a material having better thermal conductivity than the second substrate 20, and the second substrate 20 is made of a material having better processability than the first substrate 10, The configuration can be made to match each other to the properties required for the first and second substrates 10, 20.

  As shown in FIG. 1, in the first substrate 10 and the second substrate 20, the second substrate 20 includes the semiconductor elements 31 and 32, the connection electrodes 43 and 44, and the storage portions 21 for columnar wirings 50 to 52. And the first substrate 10 is covered so as to be bonded. At this time, bonding of the first substrate 10 and the second substrate 20 may be performed by various known methods.

  The ceramic capacitor 80 is provided to cover the upper surface of the second substrate 20. As shown in FIG. 2, columnar wirings 53 and 54 may be connected to the ceramic capacitor 80. The ceramic capacitor 80 may be installed with a gap 90 apart from the upper surface of the second substrate 20 depending on the application as described above, or installed in contact with the upper surface of the second substrate 20 It may be done.

  The cooler 100 is a cooling means for cooling the semiconductor elements 31 and 32. The cooler 100 may have various configurations as long as the semiconductor elements 31 and 32 can be cooled efficiently. The cooler 100 is not essential, and may be provided as necessary.

  As described above, by using the second substrate 20 including the semiconductor elements 31 and 32 and the housing portions 21 to 23 for housing the columnar wires 50, the columnar wires 50 are supported from the periphery by the second substrate 20. There is no need to secure mechanical strength of the columnar wiring 50. Therefore, it is sufficient to secure the height necessary for the electrical connection, and the height of the columnar wiring 50 can be reduced.

  FIG. 3 is a view showing an example of a conventional semiconductor module according to a comparative example. As shown in FIG. 3, in order to ensure the strength of the columnar interconnection 250, the columnar interconnection 250 has a height in which the semiconductor elements 231 and 232 and the bus bars 241 and 242 are added, and miniaturization can not be achieved.

  By comparison, as shown in FIGS. 1 and 2, in the semiconductor module according to the present embodiment, the height of the columnar interconnections 50 can be made very low, and miniaturization can be achieved, and at the same time the wiring path is reduced. Inductance can be reduced. Therefore, it can be configured as a semiconductor module capable of reducing loss.

  FIG. 4 is a view for explaining the structure in which the cavity for absorbing the dimensional tolerance of the semiconductor module according to the present embodiment is provided.

  As described above, the semiconductor module can be miniaturized and have a low inductance structure by providing the recess-like housing portions 21 to 25 in the second substrate 20. However, the bonding material 70 is provided in the housing portions 21 and 22. When the semiconductor elements 31 and 32 are accommodated in the state where the bonding material 70 is used, the bonding material 70 wraps around to the outside because the interiors of the accommodation portions 21 and 22 are close to a sealed state when the bonding material 70 is excessively supplied. There is a risk that the insulation will be impaired. In addition, since the volumes of the housing portions 21 and 22 also vary within the tolerance range, the above-described problems occur even if the amount of the bonding material 70 is precisely managed. Therefore, it is preferable to adopt a configuration in which some measures are taken in advance so that such a situation does not occur. In FIG. 4, a structure for preventing such wraparound of the bonding material 70 will be described.

  FIG. 4A is a view showing a configuration example in which the cavity 110 is provided on the side of the bonding material 70. The cavity 110 can be provided by forming a groove-like cavity 110 on the side surface of the location facing the location where the bonding material 70 is disposed in the housing portion 21. By providing the cavity 110, it is possible to secure an escape path for the bonding material 70, and it is possible to store the excess supplied bonding material 70 and prevent it from flowing out. In FIG. 4A, the cavity 110 is formed in a groove having a cross-sectional shape close to a sharp V-shape. For example, the side of the outer end of the bonding material 70 may be provided with a cavity 100 having such a V-shaped groove shape.

  FIG. 4B is a view showing a configuration example in which a groove-shaped cavity 111 different from that of FIG. 4A is provided. In FIG. 4 (b), the groove is provided at the side position of the accommodating portion 21 opposite to the position where the outer end of the bonding material 70 is arranged, as in FIG. 4 (a). It differs from FIG. 4A in that it has a cross-sectional shape. Thus, the cavity 111 may be provided with a rectangular groove shape. As shown in FIGS. 4A and 4B, the cavities 110 and 111 provided at positions corresponding to the bonding material 70 on the side surface of the housing portion 21 can have various groove shapes depending on the application. . By providing such groove-like cavities 110, 111, it is possible to absorb the excess bonding material 70, and to prevent a decrease in the insulation due to the wraparound of the bonding material 70.

  FIG. 4C is a view showing a configuration example in which the cavity 112 is provided in the connection electrodes 41 and 43. 4A and 4B show the configuration in which the cavity is provided on the side surface of the bonding material 70, the example in which the cavity 112 is provided in contact with the horizontal surface of the bonding material 70 is shown in FIG. 4C. Show. Since the bonding material 70 is provided so as to be sandwiched between the semiconductor element 31 and the connection electrodes 41 and 43, the bonding material 70 is in contact with the connection electrodes 41 and 43 over almost the entire surface. Therefore, by forming the through-hole-like cavities 112 partially in the connection electrodes 41 and 43, it is possible to store the excess bonding material 70 and prevent the outflow to the outside. As described above, the through hole-like cavity 112 may be formed in the connection electrodes 41 and 43.

  In FIGS. 4A to 4C, although the first semiconductor element 31 has been described as an example, the cavities 110 to 112 may be similarly formed corresponding to the second semiconductor element 32. Needless to say. Further, the cavities 110 and 111 shown in FIGS. 4 (a) and 4 (b) and the cavity 112 shown in FIG. 4 (c) can be combined with each other, and the side surfaces of the receiving portions 21 and 22 are connected. The cavities 110 and 111 and the cavity 112 may be provided on both of the electrodes 41 to 44.

  FIG. 5 is a view for explaining a structure for reducing stress due to the thermal expansion coefficient difference of the semiconductor module according to the present embodiment.

  The semiconductor module according to the present embodiment has a configuration in which the semiconductor elements 31 and 32 and the bonding electrodes 41 to 44 are bonded with the bonding material 70 in the housing portions 21 and 22, but the semiconductor elements 31 and 32 and the connection electrodes Due to the difference in thermal expansion coefficient between 41 and 44, when the semiconductor elements 31, 32 generate heat, stress may be applied to the bonding material 70 interposed between the semiconductor elements 31, 32 and the connection electrodes 41 to 44. Furthermore, since the bonding material 70 itself has a thermal expansion coefficient different from that of the semiconductor elements 31 and 32 and the connection electrodes 41 to 44, stress may be applied to the bonding material 70 also from the difference in thermal expansion coefficient. Here, if there is a space in the periphery, even if there is a difference in the expansion amount, the difference can be tolerated, but in the semiconductor module according to the present embodiment, since the sealed housing is performed in the housing portions 21 to 22, It is preferable to take measures in advance.

  As shown in FIG. 5, it is conceivable to form vias 71 in the form of through holes in the bonding material 70 or apply the bonding material 70 to the eye pattern of the eyelids. As described above, by forming the space in the bonding material 70 itself, it is possible to reduce the stress generated due to the difference in thermal expansion coefficient between the semiconductor elements 31 and 32 and the connection electrodes 41 to 44. In addition, while the vias 71 are formed in the bonding material 70, the bonding material 70 may be applied to a wrinkle pattern.

  FIG. 6 is a view showing a configuration example of gate wiring different from FIGS. 1 and 2 show a configuration in which through holes are formed in the ceramic capacitor 80 and the gate wiring 60 is provided to penetrate the ceramic capacitor 80, but the gate pad 61 is provided on the upper surface of the second substrate 20, A wiring portion may be formed on the upper surface of the second substrate 20 to form connection wiring with the gate terminal. The gate interconnection 60 penetrates only the through hole 26 of the second substrate 20 and does not penetrate the ceramic capacitor 80. By forming a wiring portion on the upper surface of the second substrate 20, wiring by a flexible substrate or the like becomes possible, and by providing a gap 90 between the ceramic capacitor 80 and the second substrate 20. , Floor space can be minimized.

  The respective configurations shown in FIGS. 4 to 6 can be combined with one another as long as there is no contradiction, and a necessary configuration can be appropriately adopted according to the application.

  FIG. 7 is a diagram showing a planar layout configuration of an upper portion of an example of the semiconductor module according to the present embodiment. FIG. 7A is a view showing a cross-sectional configuration of an example of the semiconductor module according to the present embodiment corresponding to FIGS. 7B to 7D.

  FIG.7 (b) is the figure which showed the structure of the CC 'horizontal cross section of Fig.7 (a). As shown in FIG. 7B, the bonding material 70 is provided corresponding to the semiconductor elements 31 and 32. Further, the gate is provided on the back side, and the bonding material 70 is also provided corresponding to the gate. In addition, it is shown that the columnar wiring 50 has a square columnar shape.

  FIG.7 (c) is the figure which showed the structure of the BB 'horizontal cross section of Fig.7 (a). As shown in FIG. 7C, the connection electrode 44 is provided so as to continuously cover both the second semiconductor element 32 and the columnar wiring 50. The gate interconnection 60 is disposed on the back side not overlapping the connection electrodes 43 and 44. In addition, the connection electrodes 43 and 44 may be provided with a cavity 112 formed of a through hole, if necessary. FIG. 7C shows an example in which nine cavities 112 are provided in each of the connection electrodes 43 and 44.

  FIG.7 (d) is the figure which showed the structure of the AA 'horizontal cross section of Fig.7 (a). As shown in FIG. 7 (d), elongated square pillar-shaped columnar wirings 51 and 52 are provided at both ends of the second substrate 20. The gate wiring 60 is provided to penetrate the second substrate 20.

  FIG. 8 is a diagram showing a planar layout configuration of a lower portion of an example of the semiconductor module according to the present embodiment. Fig.8 (a) is a figure which shows the cross-sectional structure of an example of the semiconductor module concerning this embodiment made to respond | correspond to FIG.8 (b)-(d).

  FIG.8 (b) is the figure which showed the structure of the FF 'horizontal cross section of Fig.8 (a). As shown in FIG. 8B, the connection electrode 41 is provided so as to continuously connect both the first semiconductor element 31 and the columnar wiring 50. The lower gate wiring 60 is disposed on the back side not overlapping the connection electrode 42. In addition, the connection electrodes 41 and 42 may be provided with a cavity 112 as necessary. FIG. 8B shows an example in which nine cavities 112 are provided in each of the connection electrodes 41 and 42 in correspondence with the upper connection electrodes 43 and 44.

  FIG.8 (c) is the figure which showed the structure of the EE 'horizontal cross section of Fig.8 (a). As shown in FIG. 8C, the bonding material 70 is provided corresponding to the semiconductor elements 31 and 32. Further, a bonding material 70 is provided on the back side corresponding to the gate wiring 60. In addition, it is shown that the columnar wiring 50 has a square columnar shape.

  FIG. 8D is a view showing the configuration of the horizontal cross section taken along the line DD 'of FIG. 8A. As shown in FIG. 8D, the second semiconductor element 32 is provided so as to entirely cover the bonding material 70 on the right side shown in FIG. 8C. Together with c), it is shown that the gate wiring 60 is drawn to the lower side of the semiconductor element 32, and the connection between the terminal on the lower surface and the second connection electrode 42 is made. The first semiconductor element 31 has a shape that matches the bonding material 70 because the gate wiring 60 is not drawn downward.

  As shown in FIGS. 7 and 8, it can be seen that the gate line 60 is disposed on the back side.

  FIG. 9 is a view showing a cross-sectional configuration at each position on a plane of an example of the semiconductor module according to the present embodiment. FIG. 9A is a top view showing a plan configuration of an example of the semiconductor module according to the present embodiment corresponding to FIGS. 9B to 9E.

  FIG.9 (b) is the figure which showed the structure of the JJ 'longitudinal cross section of Fig.9 (a). As shown in FIG. 9B, the gate wiring 60 is drawn vertically from the second semiconductor element 32 at the back side of the semiconductor module.

  FIG.9 (c) is the figure which showed the structure of the II 'longitudinal cross section of Fig.9 (a). As shown in FIG. 9C, the vicinity of the center of the semiconductor module has substantially the same configuration as that described in FIGS. The gate wiring 60 is not provided near the center.

  FIG.9 (d) is the figure which showed the structure of the HH 'longitudinal cross section of Fig.9 (a). As shown in FIG. 9D, the wiring connected to the second semiconductor element 32 is not present near the back side of the semiconductor module, and the gate wiring 60 is not present.

  FIG.9 (e) is the figure which showed the structure of the GG 'longitudinal cross section of Fig.9 (a). As shown in FIG. 9E, in the vicinity of the back side of the semiconductor module, the gate terminal of the first semiconductor element 31 is drawn upward, and the gate terminal of the second semiconductor element 32 is drawn downward. Gate wiring 60 is provided. Thus, the gate interconnection 60 is provided along the end of the semiconductor module.

  The configuration of the semiconductor module according to the present embodiment has been described above, but the semiconductor module according to the present embodiment can be used for various circuits. For example, it is possible to add necessary components and configure as an inverter or as a DC-DC converter. Further, although the configuration has been described using two semiconductor elements 31 and 32 in the present embodiment, it is also natural to prepare two more sets of semiconductor modules having the same configuration and to configure them as three-phase semiconductor modules. It is possible.

  Further, according to the semiconductor module according to the present embodiment, the height of the columnar wiring can be reduced, and the low inductance structure can be achieved, whereby the loss reduction and the miniaturization of the semiconductor module can be achieved.

  Although the preferred embodiments of the present disclosure have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions may be made to the above-described embodiments without departing from the scope of the present disclosure. It can be added. In particular, the left, right, upper and lower arrangement relationships and the like can be variously changed according to the application.

The following further discloses the above embodiment. In addition, the effects described below may not always always be exhibited. Also, the effect on the feature of the dependent type is the effect on the feature and is an additional effect.
(1)
A first insulating substrate (10),
First and second connection electrodes (41, 42) provided apart from each other on the first insulating substrate (10);
First and second semiconductor elements (31, 32) respectively provided on the first and second connection electrodes (41, 42);
Third and fourth connection electrodes (43, 44) respectively provided on the first and second semiconductor elements (31, 32);
Columnar wiring (50) electrically connecting the first connection electrode (41) and the fourth connection electrode (44);
The first semiconductor element (31) and the third connection electrode (43), the columnar wiring (50), and the second semiconductor element (32) and the fourth connection electrode (44) are individually accommodated. The first semiconductor element (31), the third connection electrode (43), the columnar wiring (50), and the second semiconductor are provided in the housing portion (21 to 23). And a second insulating substrate (20) joined to the first insulating substrate (10) in a state in which the element (32) and the fourth connection electrode (44) are accommodated.

According to the configuration described in (1), since the columnar wiring (50) can be held in the housing portion (23) of the second insulating substrate (20), the mechanical strength of the columnar wiring (50) can be increased. There is no need to make a request, and the columnar wiring (50) can be configured to the minimum height necessary for the wiring. As a result, the semiconductor module can be miniaturized, and the wiring can be shortened to provide a low inductance structure, thereby achieving low loss.
(2)
First semiconductor element (31) and first connection electrode (41) and third connection electrode (43), and second semiconductor element (32) and second connection electrode (42) and fourth connection The electrode (44) is bonded via a conductive bonding material (70),
At least one of the housing portion (21 to 23) of the second insulating substrate (20) and the first to fourth connection substrates (41 to 44) is a cavity (110) capable of storing an excess bonding material (70). ~ 112) semiconductor module.

According to the configuration described in (2), it is possible to prevent the excessive bonding material (70) from being stored in the cavity (110 to 112) and flowing out to the outside, and the insulation property of the insulating component of the semiconductor module can be reduced. You can keep it right.
(3)
The semiconductor module provided with the cavity (110, 111) by forming a groove in the side surface of the accommodating part (21, 22) which opposes the outer side of the side edge part of a bonding material (70).

According to the configuration described in (3), the outflow of the bonding material (70) can be effectively suppressed by providing the cavities (110, 111) in the outflow path of the bonding material (70).
(4)
A semiconductor module provided with a cavity (112) by forming a through hole in at least one of the first to fourth connection electrodes (41 to 44).

According to the configuration described in (4), the cavity (112) can be easily formed, and an arbitrary number of cavities (112) can be easily formed at an arbitrary position of one connection electrode (41 to 44). Can be formed. In addition, the outflow of the bonding material (70) can be effectively prevented before the bonding material (70) reaches the outer end.
(5)
The cavity (110 to 112) is a bonding material (70) for bonding the first semiconductor element (31) and the first connection electrode (41), and the first semiconductor element (31) and the third connection electrode (43). A bonding material (70) for bonding, a bonding material (70) for bonding a second semiconductor element (32) and a second connection electrode (42), and a second connection between a second semiconductor element (32) and a fourth connection The semiconductor module provided corresponding to all the bonding materials (70) which bond an electrode (44).

According to the configuration described in (5), it is possible to take measures against the outflow for all the bonding materials (70), and it is possible to ensure the insulation of the insulating component of the semiconductor module.
(6)
A semiconductor module in which a via (71) is formed in a bonding material (70).

According to the configuration described in (6), a space can be provided inside the bonding material (70), and the thermal expansion between the semiconductor element (31, 32), the connection electrodes (41 to 44) and the bonding material (70) It is possible to reduce the influence of residual stress caused by the difference in coefficients.
(7)
The bonding material (70) is a semiconductor module coated with a wrinkled pattern.

According to the configuration described in (7), a space can be provided in the bonding material (70) layer by the application pattern of the bonding material (70), and the residual stress can be easily obtained without introducing complicated processes and processing. It can be mitigated.
(8)
The semiconductor module wherein the bonding material (70) is silver nano paste or solder.

According to the configuration described in (8), the joining step can be easily performed by using the fluid bonding material (70). In addition, a high quality semiconductor module can be configured by the good bonding property and the conductivity.
(9)
A semiconductor module in which the first insulating substrate (10) and the second insulating substrate (20) are made of ceramic.

According to the configuration described in (9), the first insulating substrate (10) and the second insulating substrate (20) can be made of a material excellent in insulation and heat resistance, and the semiconductor element (31, It can cope with the heat of 32).
(10)
The first insulating substrate (10) is made of a material having higher thermal conductivity than the second insulating substrate (20),
The second insulating substrate (20) is a semiconductor module made of a material having a processability higher than that of the first insulating substrate (10).

According to the configuration described in (10), different functions of heat release by the first insulating substrate (10) and holding of the components by the second insulating substrate (20) are properly shared, and each function is performed. Each can play effectively.
(11)
There is further provided a ceramic capacitor (80) covering the upper surface of the second insulating substrate (20),
The first and second semiconductor elements (31, 32) have a gate to which a control signal can be input, and the gate wiring (60) connected to the gate penetrates the ceramic capacitor (80) to be connected to the ceramic capacitor (80). 80) The semiconductor module pulled out to the upper part.

According to the configuration described in (11), even if the second insulating substrate (20) is covered with the ceramic capacitor (80), the gate wiring (60) can be drawn out of the ceramic capacitor (80) Wiring to the gate can be performed without any problem.
(12)
There is further provided a ceramic capacitor (80) covering the upper surface of the second insulating substrate (20) with a gap (90),
The first and second semiconductor elements each have a gate to which a control signal can be input, and a gate wiring (61) connected to the gate is provided on the upper surface of the second insulating substrate (20).

According to the configuration described in (12), wiring to the gate can be performed in a space-saving manner without necessarily passing the ceramic capacitor (80).
(13)
A semiconductor module further comprising a cooler (100) on the opposite side of the first insulating substrate (10) to the first and second connection electrodes (41, 42).

According to the configuration described in (13), the semiconductor elements (31, 32) can be effectively cooled through the first insulating substrate (10) holding no component.
(14)
Semiconductor module configured as an inverter.

According to the configuration described in (14), a configuration having a small size and a low inductance structure can be adopted for the inverter, and a small size and an inverter having a low inductance structure can be realized.
(15)
The first and second semiconductor elements (31, 32) are transistor elements,
A semiconductor module further comprising first and second diode elements respectively connected to the first and second semiconductor elements (31, 32).

According to the configuration described in the above, it is possible to configure a compact semiconductor module having a low inductance structure together with the diode element, and, for example, it is possible to configure a DC / DC converter or the like.
(16)
A semiconductor configured for three phases, each having two sets of first and second semiconductor elements (31, 32), first to fourth connection electrodes (41 to 44), and columnar wirings (50). module.

  According to the configuration described in the above, it is possible to construct a three-phase semiconductor module having a small size and low inductance structure, and the number of units is increased in the three-phase configuration, so the advantage of miniaturization is sufficient. Can be

DESCRIPTION OF SYMBOLS 10 1st board | substrate 20 2nd board | substrate 21-25 accommodation part 31, 32 semiconductor element 41-44 connection electrode 50-54 columnar wiring 60 gate wiring 61 gate pad 70 bonding material 71 via 80 ceramic capacitor 90 space | gap 100 cooler 110 ~ 112 cavity

Claims (16)

A first insulating substrate,
First and second connection electrodes provided apart from each other on the first insulating substrate;
First and second semiconductor elements respectively provided on the first and second connection electrodes;
Third and fourth connection electrodes respectively provided on the first and second semiconductor elements;
Columnar wiring electrically connecting the first connection electrode and the fourth connection electrode;
The first semiconductor element and the third connection electrode, the columnar wiring, and the second semiconductor element and the fourth connection electrode are individually accommodated , and are opposed to the first insulating substrate. The first semiconductor element and the third connection electrode, the columnar wiring, the second semiconductor element, and the fourth semiconductor device are provided in the housing portion. A second insulating substrate joined to the first insulating substrate in a state in which a connection electrode is accommodated. A first insulating substrate,
First and second connection electrodes provided apart from each other on the first insulating substrate;
First and second semiconductor elements respectively provided on the first and second connection electrodes;
Third and fourth connection electrodes respectively provided on the first and second semiconductor elements;
Columnar wiring electrically connecting the first connection electrode and the fourth connection electrode;
It has a recess-like housing portion for individually housing the first semiconductor element and the third connection electrode, the columnar wiring, and the second semiconductor element and the fourth connection electrode, respectively. A first bonding substrate is connected to the first insulating substrate in a state where the first semiconductor element and the third connection electrode, the columnar wiring, the second semiconductor element, and the fourth connection electrode are accommodated in the housing portion. And 2 insulating substrates,
The first semiconductor element and the first connection electrode and the third connection electrode, and the second semiconductor element and the second connection electrode and the fourth connection electrode are made of a conductive bonding material. Joined through
Wherein at least one of the second the receiving portion of the insulating substrate and the first through fourth connection electrode, a semi-conductor module that have a possible reservoir cavity the bonding material surplus. The first semiconductor element and the first connection electrode and the third connection electrode, and the second semiconductor element and the second connection electrode and the fourth connection electrode are made of a conductive bonding material. Joined through
2. The semiconductor module according to claim 1, wherein at least one of the accommodation portion of the second insulating substrate and the first to fourth connection electrodes has a cavity capable of storing an excess of the bonding material. The cavity semiconductor module according to claim 2 or 3 provided by forming a groove on a side surface of the housing part which faces the outer side edge of the bonding material. The semiconductor module according to any one of claims 2 to 4, wherein the cavity is provided by forming a through hole in at least one of the first to fourth connection electrodes. The cavity includes a bonding material for bonding the first semiconductor element and the first connection electrode, a bonding material for bonding the first semiconductor element and the third connection electrode, and the second semiconductor element and the bonding material. the bonding material, and any one of claims 2 to 5 provided corresponding to all of the bonding material for bonding the fourth connection electrode and the second semiconductor element joining the second connecting electrode The semiconductor module as described in. The semiconductor module according to any one of claims 2 to 6 , wherein a via is formed in the bonding material.   The semiconductor module according to any one of claims 2 to 7, wherein the bonding material is silver nano paste or solder.   The semiconductor module according to any one of claims 1 to 8, wherein the first insulating substrate and the second insulating substrate are made of ceramic. The first insulating substrate is made of a material having a higher thermal conductivity than the second insulating substrate,
The semiconductor module according to any one of claims 1 to 9, wherein the second insulating substrate is made of a material having higher processability than the first insulating substrate. A ceramic capacitor is further provided covering the upper surface of the second insulating substrate,
The first and second semiconductor devices each have a gate to which a control signal can be input, and a gate line connected to the gate penetrates the ceramic capacitor and is drawn to the top of the ceramic capacitor. 11. The semiconductor module according to any one of to 10. A ceramic capacitor is further provided to cover the upper surface of the second insulating substrate with a gap,
11. The semiconductor device according to claim 1, wherein the first and second semiconductor elements have a gate to which a control signal can be input, and a gate wiring connected to the gate is provided on the upper surface of the second insulating substrate. The semiconductor module as described in any one.   The semiconductor module according to any one of claims 1 to 12, wherein a cooler is further provided on the surface of the first insulating substrate opposite to the first and second connection electrodes.   The semiconductor module according to any one of claims 1 to 13, configured as an inverter. The first and second semiconductor elements are transistor elements,
The semiconductor module according to any one of claims 1 to 14, further comprising first and second diode elements respectively connected to the first and second semiconductor elements.   The device according to any one of claims 1 to 15, further comprising two sets of each of the first and second semiconductor elements, the first to fourth connection electrodes, and the columnar wirings, and configured for three phases. The semiconductor module of description.

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