WO2023035101A1

WO2023035101A1 - Chip packaging structure and method for preparing chip packaging structure

Info

Publication number: WO2023035101A1
Application number: PCT/CN2021/116878
Authority: WO
Inventors: 潘伟健; 赵航
Original assignee: 华为技术有限公司
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2023-03-16
Also published as: CN117529804A

Abstract

Provided in embodiments of the present application are a chip packaging structure and a preparation method. The chip packaging structure comprises a first chip and a carrier board. The first chip is fixed on a first surface of the carrier board by means of a material. The carrier board comprises a groove structure, a groove bottom of the groove structure being buried in the carrier board, a groove opening of the groove structure being exposed at the first surface of the carrier board, and the groove structure at least partially surrounding a region of the first surface of the carrier board used for affixing the first chip. A side edge of the first chip extends to the groove opening of the groove structure, and an orthographic projection of the side edge of the first chip towards the carrier board is at least partially located within the groove structure. The present chip packaging structure can increase the reliability of a packaged chip.

Description

Chip package structure and method for preparing chip package structure

technical field

The embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a chip packaging structure and a method for preparing the chip packaging structure.

Background technique

With the development of semiconductor technology, electronic devices are becoming thinner and smaller, integrating more performance and features into smaller and smaller spaces. Therefore, chips are developing in the direction of smaller volume and thinner thickness. Therefore, the requirements for chip packaging technology are getting higher and higher.

In traditional chip packaging technology, when the chip is placed on the substrate by chip mounting processes such as bonding or welding, if the chip is too thin (for example, the thickness of the chip is less than or equal to 2mil), the materials used for mounting the chip (such as glue or Solder) is easy to overflow to the active surface of the chip, which will lead to open circuit or short circuit of the circuit integrated in the chip, which will lead to chip failure and reduce the reliability of the chip packaging process. Therefore, for thinner chips, how to improve the reliability of packaged chips becomes a problem to be solved.

Contents of the invention

The chip packaging structure and the method for preparing the chip packaging structure provided by the present application can improve the reliability of the packaged chip.

In order to achieve the above object, the application adopts the following technical solutions:

In the first aspect, the embodiment of the present application provides a chip packaging structure, the chip packaging structure includes a first chip and a carrier; the first chip is fixed on the first surface of the carrier through materials; the carrier includes A groove structure, the groove bottom of the groove structure is buried inside the carrier, the notch of the groove structure is exposed on the first surface of the carrier, and the groove structure at least partially surrounds the carrier An area for fixing the first chip on the first surface of the board; the side of the first chip is arranged on the notch of the groove structure, and the side of the first chip faces the The orthographic projection of the carrier is at least partially within the channel structure.

In the embodiment of the present application, the material may include, for example, insulating glue, conductive glue or solder; the side of the first chip may also refer to the edge of the first chip. By setting the groove structure on the carrier, and when the first chip is fixed on the carrier, the side of the first chip is extended above the notch of the groove structure, and the orthographic projection to the carrier is located in the groove structure Inside, the overflowing material can flow into the groove structure along the groove wall, preventing the material from climbing to the surface of the first chip along the side of the first chip, thereby preventing the chip from opening and shorting due to the material on the surface of the chip. In addition, since the carrier plate is equipped with a groove structure for receiving materials, when coating materials on the carrier plate, there is no need to reduce the amount of materials, and the amount of materials shown in the standard process can be used, thereby avoiding the shortage of materials and causing the second A chip is broken or the heat dissipation performance is degraded. Therefore, the chip packaging structure provided by the embodiment of the present application can improve the reliability of the chip packaging.

In the embodiment of the present application, the trough structure may be a continuous structure or a discontinuous structure, and the at least partially surrounding may refer to the trough structure surrounding the first surface of the carrier for fixing the first One round of the area of a chip can also refer to the half circle, quarter circle, etc. of the area where the groove structure surrounds the first surface of the carrier and is used to fix the first chip, or it can also mean that the groove structure is intermittent Around the area on the first surface of the carrier board for fixing the first chip.

The carrier board described in the embodiments of the present application may include various structures. The carrier board may be a substrate, which may also be called a printed circuit board (PCB, printed circuit board); it may also be a lead frame. For the two cases where the carrier board is a substrate and a lead frame, the chip packaging structure may also include multiple types.

If the carrier is a substrate:

In a possible implementation manner, a metal pad is formed on the first surface of the substrate, and the first chip is fixed on the metal pad by a material; the groove structure at least partially surrounds the metal pad.

In a possible implementation manner, a plurality of first bonding pads are further formed on the first surface of the substrate; multiple lead-out ends of the first chip are correspondingly connected to the plurality of first bonding pads through wires.

The metal pad and the first pads, and the first pads may be separated by a solder resist material.

In a possible implementation manner, the substrate further includes a multilayer wiring layer, and each wiring layer in the multilayer wiring layer includes a patterned conductive circuit and an insulating material isolating the patterned conductive circuit, The conductive lines of each layer are connected through a plurality of via holes; the second surface of the substrate also includes a plurality of conductive bumps; the lead-out end of the first chip is connected to the plurality of conductive bumps through the multi-layer wiring layer Blocks correspond to connections.

In a possible implementation manner, the multilayer wiring layer includes a first wiring layer disposed on the first surface of the substrate, and the plurality of via holes include first via holes; the first via holes are set between the groove bottom of the groove structure and the other wiring layers; the groove bottom of the groove structure is filled with conductive material, and the conductive lines on the first surface pass through the groove structure and the first Vias connect to conductive traces on other routing layers.

In a possible implementation manner, the chip packaging structure further includes packaging material; the packaging material is deposited on the first chip and the first surface of the substrate to wrap the first chip and the The exposed portion of the first surface of the substrate.

In a possible implementation manner, the chip packaging structure further includes a second chip, and the second chip is bonded on the first chip through an epoxy resin film.

In a possible implementation manner, a plurality of second bonding pads are further formed on the first surface of the substrate; lead ends of the second chip are correspondingly soldered to the plurality of second bonding pads.

If the carrier board is a lead frame:

In a possible implementation manner, the lead frame includes a metal pad; the groove bottom of the groove structure is buried inside the metal pad, and the notch of the groove structure is exposed to the first edge of the metal pad. On one surface, the groove structure at least partially surrounds a region of the metal pad for fixing the first chip.

In a possible implementation manner, the lead frame further includes a plurality of first bonding pads; the plurality of first bonding pads are arranged on the side of the metal pad; the plurality of lead ends of the first chip Correspondingly connected to the plurality of first pads through wires.

In a possible implementation manner, the chip packaging structure further includes an encapsulation material, and the encapsulation material is used to enclose the first chip, the metal pad, and the plurality of first pads.

In a possible implementation manner, the chip packaging structure further includes a second chip; the second chip is bonded on the first chip through an epoxy resin film.

In a possible implementation manner, the chip packaging structure further includes a plurality of second bonding pads; the leads of the second chip are correspondingly soldered to the plurality of second bonding pads.

In the second aspect, the embodiment of the present application provides a chip packaging structure, including a chip and a lead frame;

The lead frame includes a metal pad, the first surface of the metal pad includes a raised structure; the chip is fixed on the raised structure by a material, and the side of the chip exceeds the edge of the raised structure preset distance.

In the embodiment of the present application, the material may include, for example, insulating glue, conductive glue or solder, and the side of the chip may also refer to the edge of the chip. In the chip packaging structure described in the embodiment of the present application, by providing a raised structure on the surface of the metal pad, when the chip is fixed on the raised structure through the material, the side of the chip exceeds the preset distance from the edge of the raised structure, which can The overflowing material flows under the raised structure along the side wall of the raised structure, preventing the material from climbing to the surface of the first chip along the side of the first chip, thereby preventing the chip from opening and shorting due to the material on the surface of the chip. In addition, there is no need to reduce the amount of material when coating the protruding structure, and the amount of material shown in the standard process can be used, so as to avoid chip breakage or heat dissipation performance reduction caused by insufficient material. Therefore, the chip packaging structure provided by the embodiment of the present application can improve the reliability of the chip packaging.

In a possible implementation manner, the chip packaging structure further includes an encapsulation material, and the encapsulation material is used to enclose the first chip, the metal pad and the plurality of first pad.

In a third aspect, an embodiment of the present application provides an electronic device, the electronic device includes the chip packaging structure described in the first aspect or the second aspect.

The chip packaged by the chip packaging structure may include but not limited to: system on chip (system on chip), memory (memory), discrete device, application processor (application processor, AP), micro-electro-mechanical system (micro-electro-mechanical system) , MEMS), microwave radio frequency chip, application specific integrated circuit (ASIC for short) and other chips. The above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (central processing unit, CPU), an image processing unit (graphics processing unit, GPU), an artificial intelligence processor, for example, a neural network processor (network processing unit) in a specific application. unit, NPU), etc. The memory may be cache memory (cache), random access memory (random access memory, RAM), read only memory (read only memory, ROM), or other memory. Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like, for example. The electronic device may also be an integrated circuit product, wherein the integrated circuit product may include other integrated circuits in addition to the chip packaging structure described in the embodiment of the present application, so that the chip packaging structure shown in the embodiment of the present application is the same as Other integrated circuits cooperate with each other to realize various circuit functions.

In a fourth aspect, the embodiment of the present application provides a method for preparing a chip packaging structure, the method comprising: providing a carrier; forming a groove structure on the carrier, the groove bottom of the groove structure is buried in Inside the carrier plate, the notch of the channel structure is exposed to the first surface of the carrier plate; depositing material on the first surface of the carrier plate, the area at least partially surrounded by the channel structure; The chip is fixed on the first surface of the carrier board through the material, wherein, the side of the chip extends above the notch of the groove structure, and the side of the chip faces the side of the carrier board The orthographic projection is located at least partially within the channel structure.

Based on the fourth aspect, in a possible implementation manner, the carrier is a substrate, and a metal pad is formed on the first surface of the substrate, and forming a groove structure on the carrier includes: adopting laser opening A groove process, forming a groove structure at least partially surrounding the metal pad.

Based on the fourth aspect, in a possible implementation manner, the carrier is a substrate, and a metal pad is formed on the first surface of the substrate, and forming a groove structure on the carrier includes: A first via hole for connecting the conductive circuit on the first surface of the substrate and the conductive circuit on other wiring layers of the substrate is formed on the substrate; for the part of the substrate located above the first via hole further etching to form the groove structure; wherein, the groove bottom of the groove structure communicates with the first via hole.

Based on the fourth aspect, in a possible implementation manner, the carrier is a lead frame, and the forming the groove structure on the carrier includes: etching the metal pad on the lead frame to form the The trough structure.

In the fifth aspect, the embodiment of the present application provides a method for preparing a chip package structure, the method comprising: providing a lead frame, the lead frame is provided with a metal pad; on the first surface of the metal pad, Etching around the area for mounting the chip to form a raised structure; depositing material on the raised structure; fixing the chip on the raised structure, wherein the sides of the chip exceed the raised structure edge of the structure.

Based on the fifth aspect, in a possible implementation, the lead frame is further provided with a plurality of first pads; the method further includes: connecting the plurality of lead ends of the chip with the plurality of lead ends The first pad corresponds to the connection.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application , for those skilled in the art, other drawings can also be obtained according to these drawings without paying creative labor.

FIG. 1A and FIG. 1B are a schematic diagram of a chip packaging structure in a conventional technology provided by an embodiment of the present application;

2A-2D are structural schematic diagrams of the chip packaging structure 100 provided by the embodiment of the present application;

3A-3B are structural schematic diagrams of a chip packaging structure 200 provided by an embodiment of the present application;

4A-4B are structural schematic diagrams of a chip packaging structure 300 provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a chip packaging structure 400 provided in an embodiment of the present application;

6A-6B are structural schematic diagrams of a chip packaging structure 500 provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a chip packaging structure 600 provided by an embodiment of the present application;

FIG. 8 is a flowchart of a method for preparing a chip package structure as shown in FIG. 2B provided in an embodiment of the present application;

FIGS. 9A-9D are schematic diagrams of various structures during the preparation process of the chip packaging structure shown in FIG. 2B .

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a" or "one" do not denote a limitation in number, but indicate that there is at least one.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more. For example, a plurality of outlets refers to two or more outlets.

Please refer to FIG. 1A , which is a side view of a conventional packaging structure. In FIG. 1A , the packaging structure includes a substrate 01 coated with a material 02 for mounting a chip 03 on the surface of the substrate 01 . The material 02 may include but not limited to one of conductive glue, insulating glue and solder. The chip 03 is mounted on the substrate 01 through the material 02 . The thickness of chip 03 is less than or equal to 2mil. It can be seen from FIG. 1A that because the thickness of the chip 03 is too thin, the overflowing material 02 climbs along the side of the chip 03 to the upper surface of the chip 03 , that is, the active surface of the chip 03 . Since structures such as integrated circuits or electrodes are formed on the upper surface of the chip 03 , the material 02 climbs to the upper surface of the chip 03 and easily causes the chip 03 to open or short circuit. In order to prevent the material 02 from climbing to the surface of the chip 03, the industry further proposes to use a small amount of material 02 to mount the chip 03 on the substrate 01, as shown in Figure 1B, Figure 1B shows a substrate 01 coated with material 02 top view. In Fig. 1B, the area a on the substrate 01 is the area for mounting the chip 03. Assuming that the length and width of the chip 03 are the same as the length and width of the area a, when the material 02 is coated in the area a, when it is close to the area a No material is coated on the edge area of the substrate. When the chip 03 is mounted on the substrate 01, the material 02 cannot overflow to the upper surface of the chip 03. However, when the chip 03 is mounted with a small amount of material as shown in FIG. 1B , it is easy to cause poor heat dissipation of the chip, and also cause the chip 03 to break.

The chip packaging structure provided by the embodiment of the present application can ensure that the amount of materials used to mount the chips meets the packaging standards, and the materials will not overflow to the active surface of the chips, thereby improving the reliability of the packaged chips.

The chip packaging structure provided in the embodiment of the present application can package one or more chips in the same package. When multiple chips are packaged in the same package, the multiple chips can be arranged horizontally at intervals or stacked. Each chip is connected to other chips through structures such as leads and carrier boards, so as to realize signal exchange between multiple chips. The chip described in the embodiment of the present application may be a bare chip (Die), or a chip formed by simple packaging of a bare chip and other chips or components (active devices or passive devices, etc.), or may be packaged The encapsulation structure formed later is not limited here. The chip packaging structure described in the embodiment of the present application will be described below through the embodiments shown in FIGS. 2A-7 .

Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a top view of the chip packaging structure provided by the embodiment of the present application, and FIG. 2B is a cross-sectional view along AA' of the chip packaging structure shown in FIG. 2A. As shown in FIG. 2A and FIG. 2B , the chip package structure 100 includes a chip 10 and a substrate 11 . Chip 10 has a relatively thin thickness, generally less than or equal to 2mil. The surface D1 of the chip 10 is formed with functional structures, such as but not limited to integrated circuit structures or electrode structures. Wherein, the electrodes may include, but not limited to, the source, the drain and the gate of the transistor, for example. The surface D2 of the chip 10 is adhered to the surface S1 of the substrate 11 by glue 12 . The glue 12 described in the embodiment of the present application may be a kind of conductive glue or insulating glue. Preferably, the glue 12 is conductive glue, so as to improve the heat dissipation performance of the chip 10 . The surface S1 of the substrate 11 includes a metal pad 111 . The surface D2 of the chip 10 is bonded to the metal pad 111 by glue 12. In addition, the substrate 11 further includes a groove structure 112 surrounding the metal pad 111 . The groove bottom of the groove structure 112 is buried inside the substrate 11 , and the groove is exposed on the surface S1 of the substrate 11 . The side of the chip 10 (also called the edge of the chip 10 ) exceeds the notch of the groove structure 112 , and the orthographic projection of the side of the chip 10 to the substrate 11 is located in the groove structure 112 . It can be seen from FIG. 2B that the edge of the chip 10 exceeds the notch of the groove structure 112 , and the orthographic projection of the edge of the chip 10 to the substrate 11 is located in the groove structure 112 .

In the embodiment of the present application, by setting the groove structure 112 on the substrate 11, and when the chip 10 is bonded to the metal pad 111, the side of the chip 10 exceeds the notch of the groove structure 112, so that the overflowing glue can flow smoothly. Flowing into the groove structure 112 along the groove wall prevents the glue from climbing up to the surface D1 of the chip 10 along the side of the chip 10 , thereby avoiding short-circuiting of the chip caused by the glue on the surface D1 of the chip. In addition, since the metal pad 111 is provided with a groove structure 112 for receiving glue, when coating glue on the metal pad 111, it is not necessary to reduce the amount of glue, and the amount of glue shown in the standard process can be used, thereby avoiding insufficient glue The chip 10 is broken or the heat dissipation performance is reduced. Therefore, the chip packaging structure provided by the embodiment of the present application can improve the reliability of the chip packaging.

It should be noted that, in the chip packaging structure 100 shown in FIG. 2B , the chip 10 is bonded to the metal pad 111 by glue 12 . In other possible implementation manners, the reference numeral 12 shown in FIG. 2B may also be solder (such as lead-tin solder), and the chip 10 may be soldered to the metal pad 111 through solder.

Please continue to refer to FIGS. 2A and 2B. The substrate 11 shown in FIG. 2B may include at least one wiring layer, and each wiring layer in the at least one wiring layer includes patterned conductive lines and isolated patterned conductive lines. 2B schematically shows the situation that the substrate 11 includes four wiring layers, and the four wiring layers are respectively arranged on the upper surface S1, the lower surface S2, and the upper surface S1 and the lower surface of the substrate 11. The middle two wiring layers between S2. The conductive material used to form the conductive circuit can be a metal, such as one or more combinations of metals such as copper (Cu), silver (Ag), aluminum (Al), and the conductive material used to form the conductive circuit can also be Button tin oxide (ITO), graphite, graphene, etc.; the insulating material can be an inorganic insulating material or an organic insulating material, etc. When the substrate 11 includes multiple wiring layers, vias may also be provided on the substrate 11 , and the vias may include but not limited to: through holes or buried holes. The vias may be filled or plated with conductive material. The conductive circuits on the wiring layers in the substrate 11 are connected through via holes. In the embodiment of the present application, on the substrate 11, the via holes V1 for connecting the conductive circuit on the surface S1 of the substrate 11 and the conductive circuit on other wiring layers of the substrate 11 can be arranged at the groove bottom of the groove structure 112 and other wiring layers. between. The groove bottom of the groove structure 112 may be filled with conductive material, and the conductive lines on the surface S1 of the substrate 11 are connected to other wiring layers through the groove structure 112 and the via hole V1 , as shown in FIG. 2B . In FIG. 2B , the groove structure 112 and the via hole V1 are used to connect the conductive circuit on the surface S1 of the substrate 11 with the conductive circuit on the wiring layer S3 of the substrate 11 . It can be seen from FIG. 2B that the bottom of the groove structure 112 communicates with the via hole V1. By arranging the groove structure 112 on the via hole V1, and the bottom of the groove communicates with the via hole V1, the groove structure can be prepared together in the process of preparing the via hole on the substrate, simplifying the preparation process of the chip packaging structure .

Further, in addition to forming the metal pad 111 for bonding the chip on the surface S1 of the substrate 11, a plurality of mutually insulated pads 113 are also formed in the area around the metal pad 111, and the pads 113 are used for bonding with the chip 10. Bond. In addition, the part of the surface S1 of the substrate 11 that is not provided with the pad 113 and the metal pad 111 is covered by an insulating material. The insulating material may also be called a solder resist material, and the solder resist material may be an ink material, such as green oil. In FIG. 2A and FIG. 2B , the surface D1 of the chip 10 is provided with a plurality of leads 101 . Each lead-out end 101 of the chip 10 is respectively connected to each pad 113 on the substrate 11 by wire bonding. Fig. 2A schematically shows that the chip 10 includes eight lead-out ends 101, and eight bonding pads 113 are formed on the substrate 11, and the eight lead-out ends 101 of the chip 10 are respectively connected with the eight bonding pads 113 on the substrate 11 through wires. One-to-one connection. In order to improve the firmness of the leads and avoid breakage of the leads, in a possible implementation manner, the leads used to connect the leads 101 of the chip 10 and the bonding pads 113 may be gold wires. Thus, the leads of the chip 10 are drawn to the surface S1 of the substrate 22 .

Further, a ball grid array 114 (BGA, ball grid array) may also be provided on the surface S2 of the substrate 11 opposite to the surface S1 , as shown in FIG. 2C , the ball grid array 114 includes a plurality of conductive bumps. Thus, the lead-out end 101 of the chip 10 is drawn out to the surface S1 of the substrate 11 through the lead wire, and then is drawn from the surface S1 of the substrate 11 to the surface S2 of the substrate 11 through the wiring layer in the substrate 11, thereby being compatible with the ball grid array 114. The conductive bumps are correspondingly connected. In addition, in order to better protect the chip 10, an encapsulation material 115 for protecting the chip 10, leads, and pads on the surface of the substrate 11 can also be provided on the surface D1 of the chip 10 and the surface S1 of the substrate 11. The encapsulation material 115 may be a plastic encapsulation material, as shown in FIG. 2C , which is a cross-sectional view of the chip packaging structure 100 after the encapsulation material is provided.

In the embodiment of the present application, in the chip packaging structure shown in FIGS. 2A-2C , the groove structure 112 surrounds the area on the surface S1 of the substrate 11 for mounting the chip 10 for a week. In other possible implementations, the groove structure 112 may also partially surround the area on the surface S1 of the substrate 11 for mounting the chip 10 , as shown in FIG. 2D , which is another top view of the chip packaging structure 100 . In FIG. 2D, the groove structure 112 is a discontinuous structure. The groove structure 112 includes a first part 1121, a second part 1122, a third part 1123 and a fourth part 1124. The first part 1121 to the second part 1124 are all arranged on In the area around the area on the surface S1 of the substrate 11 where the chip 10 is mounted, each part is discontinuous. In addition, when the groove structure 112 is in the shape shown in FIG. 2D , the orthographic projection of the edge of the chip 10 to the substrate 11 is located inside the groove structure 112 . That is to say, as shown in FIG. 2D , the orthographic projections of the four corners of the chip 10 to the substrate 11 are not located inside the groove structure 112 , and the orthographic projections of the rest of the chip 10 to the substrate 11 are all located inside the groove structure 112 .

One chip is packaged in the chip packaging structure 100 shown in FIG. 2A-FIG. The chips may be arranged at intervals along the same horizontal plane in the chip package structure. Taking two chips packaged in the chip package structure as an example, the chip package structure packaged with multiple chips will be described below with reference to FIG. 3A and FIG. 3B . FIG. 3A is a top view of the chip packaging structure 200 ; FIG. 3B is a side view of the chip packaging structure 200 . As shown in FIGS. 3A and 3B , the chip packaging structure 200 includes a substrate 11, a chip 10 and a chip 20, the surface of the substrate 11 is provided with a metal pad 1111 and a metal pad 1112, and a groove structure 1121 and a groove structure are formed in the substrate 11. 1122, the specific shape of the groove structure 1121 and the groove structure 1122 and the relative position relationship with the chip are similar to the groove structure 112 shown in FIG. 2A and FIG. Let me repeat. The groove structure 1121 is used to receive the glue overflowing from the bottom of the chip 10 , and the groove structure 1122 is used to receive the glue overflowing from the bottom of the chip 20 . In addition, the surface S1 of the substrate 11 further includes a plurality of bonding pads 113 , and both the lead-out ends 101 of the chip 10 and the lead-out ends 201 of the chip 20 are correspondingly connected to the bonding pads 113 on the surface S1 of the substrate 11 by wire bonding. The substrate 11 also includes multi-layer wiring layers, and the chip 10 and the chip 20 can communicate with each other through the wiring layers on the substrate 11 for signal communication. The wiring layer in the substrate 11, the bonding pads on the surface S1 of the substrate 11, and the connection between the chip 10 and the chip 20 and the bonding pads on the substrate 11 are similar to each part in the chip package structure 100 shown in FIGS. 2A and 2B , For details, refer to related descriptions in the chip package structure 100 , and details are not repeated here.

The multiple chips packaged in the chip package structure 200 shown in FIG. 3A and FIG. 3B described above are arranged at intervals along the same horizontal plane. In a possible implementation manner, multiple chips packaged by the chip packaging structure may also be stacked vertically, that is, the chip packaging structure described in the embodiment of the present application may also be a stacked structure. On the basis of any of the embodiments shown in FIGS. 2A-3B , multiple chips can be stacked on the chip 10 , and the embodiment of the present application does not limit the number of chips stacked on the chip 10 . Taking one chip stacked on the chip 10 as an example, the chip package structure 300 for building a stacked structure provided by the embodiment of the present application will be described in more detail below with reference to FIG. 4A and FIG. 4B . 4A is a top view of the chip packaging structure 300 ; FIG. 4B is a side view of the chip packaging structure 300 . As shown in FIG. 4A and FIG. 4B, the chip package structure 300 includes a chip 10, a chip 30 and a substrate 11, and the chip 10 is mounted on the surface S1 of the substrate 11 by materials, wherein the structure of the substrate 11, the distance between the chip 10 and the substrate 11 The relative position and the bonding method between the chip 10 and the substrate 11 are the same as those of the chip package structure 100 shown in FIG. 2A and FIG. 2B . For details, refer to the related description of the chip package structure 100 , which will not be repeated here. Different from the above embodiments, the chip 30 is stacked on the chip 10, wherein the chip 30 can be pasted on the chip 10 through an epoxy resin film in the area where the lead-out terminal 101 is not provided. In addition, the surface D3 of the chip 30 also includes a plurality of lead-out ends 301 , and the lead-out ends 301 are respectively connected to the pads 113 on the surface S1 of the substrate 11 through wire bonding. Therefore, the chip 10 and the chip 30 are connected to the ball grid array bumps 114 on the surface S2 of the substrate 11 through the bonding pad 113 on the substrate 11 and the redistribution layer on the substrate 11 . In addition, the chip 10 and the chip 30 may also be connected through a redistribution layer for signal exchange.

The groove structure 112 in the chip packaging structure shown in FIGS. 2A-4B , the bottom of the groove communicates with the via hole V1, that is, the groove structure 112 is used to connect the conductive circuit on the surface S1 of the substrate 11 to the other parts of the substrate 11. The connection of conductive traces on a wiring layer. In a possible implementation, the bottom of the groove structure described in the embodiment of the present application may not be connected with the via hole, that is, the groove structure 112 may not be used to communicate with the via hole on the surface S1 of the substrate 11. The conductive lines and the conductive lines on other wiring layers of the substrate 11 . In this implementation manner, the groove structure 112 may also be obtained by laser grooving the metal pad and the insulating medium on the substrate 11 through a laser grooving process. Taking FIG. 5 as an example, the groove structure obtained through the laser groove process will be described below. FIG. 5 is a side view of a chip package structure 400 . In FIG. 5 , it schematically shows that the groove structure 116 penetrates the metal pad 111 and the bottom of the groove further extends to the inside of the substrate 11 . In other possible implementation manners, the groove bottom of the groove structure 116 may also be buried inside the metal pad 111 without penetrating through the metal pad 111 . In this embodiment of the present application, the depth of the groove structure 116 is not specifically limited, and it is determined according to the needs of the scene.

In the chip packaging structures shown in FIGS. 2A-5 above, the substrate 11 is used as the carrier, and the chip is mounted on the metal pad on the surface of the substrate 11 . That is, the chip packaging structures shown in FIGS. 2A-5 are all substrate packaging structures. In a possible implementation manner of the embodiment of the present application, the chip package structure may also be a lead-frame (lead-frame) package structure. At this time, no substrate is provided in the chip packaging structure, and the lead frame is used as the carrier board, and the chip is mounted on the metal pad of the lead frame through materials. The chip package structure 500 of the lead-frame package structure provided by the embodiment of the present application will be described in more detail below with reference to FIG. 6A and FIG. 6B . 6A is a side view of the chip packaging structure 500 , and FIG. 6B is a top view of the chip packaging structure 500 . As shown in FIG. 6A , the chip package structure 500 includes a lead frame 43 on which a metal pad 41 is disposed. The metal pad 41 is mounted on the inner surface of the lead frame 43 . The surface G1 of the metal pad 41 is provided with a groove structure 411, the shape of the groove structure 411 and the relative positional relationship with the chip 40 are the same as the groove structure 112 shown in Fig. 2A and Fig. 2B and the relationship between the groove structure 112 and the chip. The phase position relationship between 10 is the same, for details, please refer to related descriptions, and details will not be repeated here. The groove structure 411 is used to hold the overflowing solder and prevent the solder from climbing to the surface of the chip 40 through the side of the chip 40. In addition, a plurality of bonding pads 42 are mounted on the lead frame 43 and around the metal pad 41 . Lead-out terminals 401 are also provided on the chip 10 , and each lead-out terminal 401 of the chip 10 is respectively connected to each bonding pad through a lead wire by way of wire bonding. In the embodiment of the present application, the chip packaging structure 400 further includes a packaging material, which includes but not limited to: epoxy resin. The encapsulation material is used for encapsulating structures such as the chip 40 , the metal pad 41 and the pad 42 inside the encapsulation shell.

In the chip packaging structure 500 shown in FIG. 6A , the groove structure 411 is formed on the metal pad 41 to receive the overflowing solder. In other possible implementations, when the chip package structure is a lead-frame package structure, a bump structure can also be provided on the metal pad, and the chip is mounted on the bump structure by solder mounting, so that the overflowing solder can Flowing through the sidewall of the raised structure to the side of the raised structure prevents the solder from climbing to the surface of the chip through the side of the chip. The following description will be made through FIG. 7 . Wherein, FIG. 7 is a side view of the chip packaging structure 600 . As shown in FIG. 7 , the chip package structure 600 includes a chip 60 , a metal pad 61 , a bonding pad 62 and a lead frame 63 . The structures of the lead frame 63 and the pads 62 and the relative positional relationship with other structures are the same as those of the chip package structure 500 shown in FIGS. 6A-6B . Refer to related descriptions for details and will not be repeated here. Different from the chip packaging structure 500 as shown in FIGS. 6A-6B , in FIG. 7 , a protruding structure 611 is formed on the surface of the metal pad 61 , and the protruding structure 611 may be obtained by etching the metal pad 61 . The chip 60 is mounted on the surface of the protruding structure 611 by solder. After the chip 60 is mounted on the surface of the raised structure 611 , the edge of the chip 60 exceeds the edge of the raised structure 611 . Therefore, the overflowing solder can flow along the sidewall of the raised structure 611 to the area on the metal pad 61 and both sides of the raised structure 611 , preventing the solder from climbing to the surface of the chip 60 through the side of the chip 60 .

One chip is packaged in each of the chip packaging structures shown in Figures 6A-7. In other possible implementations, when the chip packaging structure is a lead-frame packaging structure, multiple chips can also be packaged in the chip packaging structure. , the plurality of chips can be arranged horizontally at intervals, or vertically stacked. When a plurality of chips are arranged at intervals horizontally, a plurality of metal pads for welding chips can be arranged in the chip package structure, and the structure of each metal pad can be as shown in FIG. 5B or the structure of the metal pad shown in FIG. 6 , please refer to related descriptions for details, and details will not be repeated here.

It should be noted that the groove structure described in the above embodiments is an annular groove structure surrounding the chip bonding (or soldering) area, and each part is connected. The groove structure in the connecting (or welding) area can also be a partially connected structure. In addition, the top view of the groove structure can also be a plurality of disconnected spherical structures. The embodiment of the present application does not specifically limit the specific shape of the groove structure, which can be set according to the needs of the application scenario.

The embodiment of the present application also includes an electronic device, and the electronic device includes the chip packaging structure as shown in the above embodiments. The chip packaged in the chip packaging structure may include but not limited to: system on chip (system on chip), memory (memory), discrete device, application processor (application processor, AP), micro-electro-mechanical system (micro-electro-mechanical System, MEMS), microwave radio frequency chip, application specific integrated circuit (ASIC for short) and other chips. The above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (central processing unit, CPU), an image processing unit (graphics processing unit, GPU), an artificial intelligence processor, for example, a neural network processor (network processing unit) in a specific application. unit, NPU), etc. The memory may be cache memory (cache), random access memory (random access memory, RAM), read only memory (read only memory, ROM), or other memory. Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like, for example. In addition, the electronic device can also be an integrated circuit product, wherein, in addition to the chip package structure described in the embodiment of the application, the integrated circuit product can also include other integrated circuits, so that the chip package shown in the embodiment of the application The structure cooperates with other integrated circuits to realize various circuit functions.

Based on the chip packaging structure described in the above embodiments, the embodiment of the present application also provides a method for the chip packaging structure. The following takes the preparation of the chip packaging structure 100 as shown in FIG. 2B as an example, as shown in FIG. 8 The flow 800 of the present invention describes in detail the process flow of preparing the chip package structure 100 . The process flow 800 includes the following steps:

In step 801, a substrate 11 is provided, and the substrate 11 may include multiple wiring layers.

In this step, standard processes such as photolithography, development, and etching can be used to prepare the substrate 11 with multi-layer wiring layers. The specific preparation process of the substrate 11 will not be described in detail again. Wherein, each wiring layer includes patterned conductive lines. The surface S1 of the substrate 11 includes a metal pad 111 , a pad, and a solder resist material 117 for isolating the metal pad 111 and the pad. The solder resist material 117 may be green oil. The structure formed after this step is shown in Figure 9A.

Step 802 , forming a plurality of via holes and groove structures 112 on the substrate 11 for connecting conductive lines on each wiring layer on the substrate 11 .

Multiple vias can be formed using standard processes. The plurality of via holes include a via hole V1 for connecting the conductive lines on the surface S1 of the substrate 11 and the conductive lines on other wiring layers of the substrate 11 (such as the wiring layer S3 shown in FIG. 9B ). A region near the surface S1 on the top of the via hole 112 is further etched to form a groove structure 112 . The notch of the groove structure 112 is exposed on the surface S1 of the substrate 11 , and the bottom of the groove communicates with the conductive circuit on one of the wiring layers of the substrate 11 . After this step, the formed groove structure 112 is shown in FIG. 9B .

Step 803 , coating the conductive glue 12 on the metal pad 111 and the area surrounded by the groove structure 112 , as shown in FIG. 9C .

Step 804, bonding the chip 10 on the metal pad 111 and the area where the conductive glue 12 is coated, wherein the side of the chip 10 exceeds the edge of the groove structure 112 by a predetermined distance, and the side of the chip 10 faces the groove structure 112 The orthographic projection of falls into the groove structure 112 interior. After this step, the formed groove structure 112 is shown in FIG. 8D .

After step 803 and step 804, in the process of bonding the chip 10, the overflowing conductive glue can flow into the groove along the side wall of the groove structure 112, avoiding climbing to the surface of the chip along the side of the chip 10, Improve chip reliability.

Step 805 , using a wire bonding process to respectively bond the leads on the surface D1 of the chip 10 to the pads 113 of the substrate 11 . After this step, the resulting structure is shown in Figure 2B.

After step 805, the lead-out end 101 of the chip 10 is led out to the surface S1 of the substrate 11 through the wire, and then is led from the surface S1 of the substrate 11 to the surface S2 of the substrate 11 through the wiring layer in the substrate 11, so that the connection with the substrate 11 can be realized. Communication and signal exchange between other chips or components.

Further, in order to better protect the chip 10, after step 805, pads for protecting the chip 10, leads, and the surface of the substrate 11 may also be formed on the surface of the chip 10 and the surface of the substrate 11. The encapsulation material, the encapsulation material may be a plastic encapsulation material.

It should be noted that the chip package structure as shown in FIG. 2B can be prepared through steps 801 to 805, and the method for preparing the chip structure 200 as shown in FIG. 3B is similar to the method for preparing the chip package structure as shown in FIG. 2A Similar, no more details. When it is necessary to prepare a chip package structure as shown in FIG. 4A , after the above-mentioned step 803 and before step 804, the chip 20 can be further bonded with an epoxy resin film on the surface D1 of the chip 10; in step 805, the The leads on the surface D3 of the chip 20 are bonded to the pads 113 of the substrate 11 by using a wire bonding process. When it is necessary to prepare the chip package structure as shown in FIG. 4, step 802 can be replaced with the following step: using a laser grooving process, laser grooving is performed on the metal pad 111 to form a groove around the mounting area of the chip structure116. The recessed depth of the groove structure 116 into the substrate 11 may not exceed the thickness of the metal pad, and may also be the thickness of a multi-layer wiring layer (for example, two wiring layers); when it is necessary to prepare a chip package structure as shown in FIG. 6B , The substrate 11 in step 801 can be replaced with a lead frame provided with metal pads and welding pads, and other processes are similar and will not be repeated here. When it is necessary to prepare a chip package structure as shown in FIG. 7, the substrate 11 in step 801 can be replaced with a lead frame provided with metal pads and pads, and the above step 802 can be replaced by the following steps: etching the metal pad to A raised structure for mounting chips is formed.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims

A chip packaging structure, characterized in that it includes a first chip and a carrier board;

The first chip is fixed on the first surface of the carrier by materials;

The carrier board includes a groove structure, the groove bottom of the groove structure is buried inside the carrier board, the notch of the groove structure is exposed on the first surface of the carrier board, and the groove structure is at least a region partially surrounding the first surface of the carrier for fixing the first chip;

The side of the first chip is disposed on the notch of the groove structure, and the orthographic projection of the side of the first chip to the carrier is at least partly located in the groove structure.
The chip packaging structure according to claim 1, wherein the carrier comprises a substrate;

A metal pad is formed on the first surface of the substrate, and the first chip is fixed on the metal pad through the material;

The groove structure at least partially surrounds the metal pad.
The chip packaging structure according to claim 2, wherein a plurality of first pads are further formed on the first surface of the substrate;

The multiple leads of the first chip are correspondingly connected to the multiple first pads through wires.
The chip packaging structure according to claim 2 or 3, wherein the substrate further comprises a multilayer wiring layer, and each wiring layer in the multilayer wiring layer includes patterned conductive lines and isolates the The insulating material of the patterned conductive circuit, and the conductive circuits of each layer are connected through a plurality of via holes;

The second surface of the substrate further includes a plurality of conductive bumps;

The leads of the first chip are correspondingly connected to the plurality of conductive bumps through the conductive lines on the multilayer wiring layer and the plurality of via holes.
The chip packaging structure according to claim 4, wherein the multilayer wiring layer includes a first wiring layer disposed on the first surface of the substrate, and the plurality of via holes include a first via hole;

The first via hole is arranged between the groove bottom of the groove structure and the other wiring layers;

The groove bottom of the groove structure is filled with conductive material, and the conductive circuit on the first surface communicates with the conductive circuit on other wiring layers through the groove structure and the first via hole.
The chip packaging structure according to any one of claims 2-5, wherein the chip packaging structure further comprises a packaging material;

The encapsulation material is deposited on the first chip and the first surface of the substrate to wrap the exposed parts of the first chip and the first surface of the substrate.
The chip packaging structure according to claim 1, wherein the carrier board is a lead frame;

the lead frame includes a metal pad;

The groove bottom of the groove structure is buried inside the metal pad, the notch of the groove structure is exposed on the first surface of the metal pad, and the groove structure at least partially surrounds the metal pad, An area for fixing the first chip.
The chip packaging structure according to claim 7, wherein the lead frame further comprises a plurality of first pads;

The plurality of first pads are disposed on the side of the metal pad;

The multiple leads of the first chip are correspondingly connected to the multiple first pads through wires.
The chip packaging structure according to claim 7 or 8, characterized in that, the chip packaging structure further comprises a packaging material for wrapping the first chip, the metal pad and the A plurality of first pads.
The chip packaging structure according to any one of claims 1-9, wherein the chip packaging structure further comprises a second chip;

The second chip is bonded on the first chip through an epoxy resin film.
The chip packaging structure according to claim 10, wherein the chip packaging structure further comprises a plurality of second pads;

Lead ends of the second chip are correspondingly welded to the plurality of second bonding pads through wires.
A chip packaging structure, characterized in that it includes a chip and a lead frame;

The lead frame includes a metal pad, the first surface of the metal pad includes a raised structure;

The chip is fixed on the raised structure by materials, and the side of the chip exceeds the edge of the raised structure.
The chip packaging structure according to claim 12, wherein the lead frame further comprises a plurality of first pads;

The plurality of first pads are disposed on the side of the metal pad;

The multiple leads of the first chip are correspondingly connected to the multiple first pads through wires.
The chip packaging structure according to claim 13, characterized in that, the chip packaging structure further comprises a packaging material for wrapping the first chip, the metal pad and the plurality of first solder pads. plate.
A method for preparing a chip packaging structure, characterized in that, comprising:

providing a carrier board;

A groove structure is formed on the carrier, the groove bottom of the groove structure is buried inside the carrier, and the notch of the groove structure is exposed on the first surface of the carrier;

depositing material on the first surface of the carrier in an area at least partially surrounded by the channel structure;

Fixing the chip on the first surface of the carrier plate through the material, wherein the side of the chip is arranged on the notch of the groove structure, and the side of the chip faces the carrier plate The orthographic projection of is at least partially within the channel structure.
The method according to claim 15, wherein the carrier is a substrate, a metal pad is formed on the first surface of the substrate, and forming a groove structure on the carrier comprises:

A laser groove process is used to form a groove structure at least partially surrounding the metal pad.
The method according to claim 15, wherein the carrier is a substrate, a metal pad is formed on the first surface of the substrate, and forming a groove structure on the carrier comprises:

forming a first via hole on the substrate for connecting the conductive lines on the first surface of the substrate to the conductive lines on other wiring layers of the substrate;

further etching a portion of the substrate above the first via hole to form the groove structure;

Wherein, the groove bottom of the groove structure communicates with the first via hole.
The method according to claim 15, wherein the carrier board is a lead frame, and forming a groove structure on the carrier board comprises:

Etching the metal pad on the lead frame to form the groove structure.
A method for preparing a chip packaging structure, characterized in that, comprising:

providing a lead frame, the lead frame is provided with a metal pad;

performing etching on the first surface of the metal pad, surrounding the area for fixing the chip, to form a raised structure;

depositing material on the raised structures;

The chip is fixed on the raised structure, wherein the side of the chip exceeds the edge of the raised structure.
The method according to claim 19, wherein the lead frame is further provided with a plurality of first pads; the method further comprises:

The plurality of lead-out terminals of the chip are correspondingly connected to the plurality of first pads through wires.